JPH03214818A - Digital analog conversion circuit - Google Patents

Abstract

PURPOSE:To convert directly a digital signal of 2's complement notation into an analog signal without need of any correction circuit by providing a capacitor whose capacitance is the same as a minimum capacitance of a capacitor array in parallel with the capacitor array weighted in 2's power. CONSTITUTION:An additional capacitor 17 having a unit capacitance C0 is provided in parallel with a capacitor array 18. The capacitor 17 connects to a reference level terminal 21 or 22 in response to a value of a control signal SA from a control circuit 23 with an additional switch 14 of the same constitution as a switch 15-0 or the like of a switch array 15. The circuit 23 outputs the control signal SA based on the combination of a most significant bit D5 of a digital signal to be inputted and a logic level of a clock signal CLK and a 1-step error in the case of 2's complement notation is corrected. Thus, a digital signal of 2's complement notation is directly converted into an analog signal without need of any correction circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital-to-analog conversion circuit that converts a digital signal to an analog signal, and particularly to a digital-to-analog conversion circuit having a capacitor array.

[Conventional technology]

Some commonly used electronic devices handle only analog signals such as audio or video, and others handle only digital signals, but many devices handle both types of signals. In such devices, digital signals must ultimately be converted into analog signals, and analog signals must be converted into digital signals. Of these, a so-called digital-to-analog conversion circuit is used to perform the former conversion.

FIG. 6 shows an example of a conventional digital-to-analog conversion circuit, which can convert a 6-bit digital signal to a 63-level analog signal.

This circuit is provided with a control circuit 11 and receives a 6-bit digital signal D from a digital signal input terminal section 12. -D
, and the clock signal CLK is manually input from the clock input terminal 13. A 6-bit control signal S is output from the output side of the control circuit 11. −
S4 and S0 are output and supplied to switches 15-0 to 15-4 of switch array section 15 and switch 16, respectively.

The switches 15-O to 15-4 are equipped with terminals G, R, and a common terminal C, among which the terminal G is connected to the reference potential V,
The terminal R is connected to the first reference potential terminal 2l to which a reference potential vR is applied, and the terminal R is connected to the second reference potential terminal 22 to which a reference potential vR is applied. In addition, the common Yasuko C each has a capacitor array l8.
It is connected to the analog output terminal 19 via capacitors 18-θ to 18-4. This analog 8 terminal l9
is also connected to the first reference potential terminal 21 via the switch 16. An analog output potential v0 is output from this analog output terminal 19.

Each capacitor forming the capacitor array 18 has a unit capacitance C. is weighted to the power of 2. That is, as shown in the figure, capacitors 18-0 to 18-4 are Co, respectively.
It has a capacity of 2c 4Co 8Co16C0.

For the switches 15-O to 15-4, the control signal So=34
When the logic is "0", the terminal G and the common terminal C are connected, and when the logic is "1", the terminal R and the common terminal C are connected. Further, the switch 16 is controlled so that it is turned off when the control signal S is at logic "0" and turned on when it is at logic "1".

FIG. 7 shows the control circuit 11 of FIG. 6 in detail. This circuit has five OR gates '25-0~
25-4 are provided, and the lower five bits Do to D of the digital signal applied to the digital signal human input terminal section 12 are inputted to one of the input sides of each. Among these, Do is the least significant bit (hereinafter, LSB
It is called. ) is shown. In addition, the most significant bit (hereinafter referred to as MSB) Ds of the digital code is branched into two,
The signal is input to one of the AND gate 27 and the OR game 1.28. The other input terminal of the AND gate 27 receives one of three branches of the clock signal CLK from the clock input terminal 13, and the other input terminal of the OR gate 28 receives this clock signal CLK. A second branch signal is manually input via an inverter 31. Further, the third branch signal of the clock signal CLK is output as is from the output terminal 35 of the control signal output terminal section 34 as the control signal S0.

The output side of the AND gate 27 is branched into five parts, each of which is connected to one input terminal of the OR game 25-0 to 25-4. These 5 or games}25-0~25-
The 8 sides of 4 are each an and game} 33-0 to 33-
It is connected to one input terminal of 4. The five branched a forces of the OR gate 28 are connected to the other input terminals of each of these AND gates. The outputs of these AND gates are each controlled by a control signal S.
. -S, is outputted from the control signal output terminal section 34.

In the end, in this control circuit 1l, the switches 15-0 to 15-4 and the switch 16 (FIG. 6) are controlled by control signals expressed by the following equations (1) to (6).

So = (CLK' + D,) ・<(CLK
- Ds) + IL)... (1) S = (CLK' + D,) ・ (
(CLK D.) + D. )...
...(2) S2=(CLκ' + D,,)・((CLK
D, ) + D. )(3) S3 −(CLκ' + [1,) ・((
CLK ・0,)+ [1,)(4) S4 −(CLK' + Ds) ・((CL
K − Ds>+D. )... (5) S, 1CLK...
(6) However, CLK' indicates a value obtained by inverting the logic of CLK.

Next, the operation of the conventional digital-to-analog conversion circuit configured as above will be explained.

Here, D is the MSB of the manually input digital signal.
Four cases based on combinations of logic levels of the clock signal CLK and the clock signal CLK will be explained.

(a) When Ds = '0'° (a-1) Timing of CLK = "1" In this case,
From equations (1) to (6), control signals S to S4 are all logic "0" and S0 is logic "1". Therefore, the common terminals C of the switches 15-0 to 15-4 are all connected to the terminal G side, and the switch 16 is turned on. As a result, the relationship between the reference potential terminals 21, 22 and the analog output terminal 19 in FIG. 6 is equivalently as shown in FIG. 8 (a1).
become that way. Here, CA represents the total combined capacitance of the capacitor array 18 as shown in equation (7) below.

CA=31co...(7) At this time, both ends of the capacitor array 18 are short-circuited, so the capacitors 1810 to 18- of this capacitor array
4 are all discharged and the accumulated charge becomes 0.

(a-2) CLK = "O" timing In this case, from equations (1) to (6), the control signals So"""S. D.

~D4, and the control signal SG becomes logic "0". For this reason, switch 15゛10~l5
-4 common terminals C are respectively connected to the side corresponding to the logic level of Do=D. In other words, the switch corresponding to the logic "0" pit of the digital manual input code is connected to the terminal G side, and the switch corresponding to the logic "1" bit is connected to the terminal R side.
connected to the side. As a result, the reference potential terminal 2 in FIG.
The relationship between i22 and the analog output terminal 19 is equivalently as shown in FIG. 8(a-2). Here, cX,
c, represents the combined capacitance of the group of capacitors connected to the terminal G side and the terminal R side, respectively, and the following (8)
There is a relationship between formulas.

CA= Cx + CY・・・・・・
(8) Therefore, the analog output potential VO outputted from the analog output terminal 19 at this time is expressed by the following equation (9).

Vo = (Cx-Vc + CY・VR) /
CA (CX-Vc + CY・VR) /
31Co... (9) For example, when a signal such as the following equation (10) is given as a digital human input signal, each switch 15-0 to 154 of the switch array 15 is as shown in FIG. state, Cx SCy are 28co 3Co respectively
becomes.

(D., D, J. D2, D,, Do
') = (0, (1, 0, 1.1)... (
1 0) Therefore, the analog output potential V. is the following (
11) The equation is as follows.

Vo = (28/31) ・v. + (3/31
) ・VR・・・・・・(11) Also, as the digital input signal D, ~D0 (0.0
．． 0, O. O) and (1, 1, 1,
1. 1) When the value is given, the analog output potential is V. are as shown in the following equations (12) and (13), respectively.

V. = VG ・・・・・・(
12〉Va = Vt ・-・・
(1 3) Eventually, the digital input signal becomes (0,'0...
0. 0. 0) to (1. 1. 1. 1.
1>, the analog output potential V changes accordingly. is the next (1
4) It will change by the amount ΔV shown in the equation.

Δv=(vR-'V.l, )/31'
−・−・・− (1 4) (b) When D5 = “1” (b-1) Timing of CLK = “1” At this time, (1
) to (6), the control signal S is obtained. ~S4, and S0
are all logical "1".

Therefore, all the common terminals C of the switches 15-0 to 15-4 are connected to the terminal R side, and the switch l6 is turned on. As a result, the reference potential terminal 21 in FIG.
22 and the analog output terminal I9 are equivalently as shown in FIG. 1 (b-1). Therefore, each of the capacitors 18-0 to 18-4 in the capacitor array 18 is charged and discharged.

(b-2) Timing of CLK=“0” In this case, as in the case of (a-2), the control signal S. -54 are equal to the logic levels of D0 to D, respectively, and the control signal S becomes logic "0". As a result, the relationship between the reference potential terminals 21, 22 and the analog output terminal 19 in FIG. 6 becomes equivalently as shown in 9th Em (b-2).

At this time, capacitors 18-0 to 18 of capacitor array 18
Since predetermined charges are accumulated in -4 at the timing (b-1) described above, the analog output potential Vo at this time is expressed by the following equation (15).

Vo = (Cx VG + Cy
ν. )/31 mouths G+ (VG-VR) ・・
(15) In this case, the digital input signals are (0, 0, 0.00) and (1, 1, 1.
1. 1) When the value is given, the analog output potential V. are as shown in the following equations (16) and (17), respectively.

Vo = Va + (Vc i'i) =
21'R-Vl1... (16) Vo = ll'R + (VG l/l) =
l/c...(17) In the end, the digital input signal becomes (0. O, 0, 0.
0) to (1, 1, 1. 1. 1) by 1 digit, the analog output potential Vo correspondingly changes from (2Vc-■,) to V, 1
4) It will change by the amount Δ shown in the equation.

As is clear from equations (12) and (17) among those explained above, the value of the digital input signal is (0. 0.
0, 0, 0. 0) and (1, 1, l
, 1. 1. 1>, the analog output potential V
. are both V.

FIG. 10 shows (a-1) to (b-2) T: the digital input signal D described above. -D, and control signal S0
~Ss, Sc and the relationship between analog output potential VO. As shown in this figure, the value of the digital input signal is (0, O, O, O, O, O)
and (1, 1. 1, 1. 1. 1)
The analog output levels will be the same when .

In this way, when the digital signal is expressed in sine magnitude such as a PCM code, the digital-to-analog converter circuit shown in FIG. 6 can be used, but in the case of two's complement expression used in normal digital signal processing, If this circuit is used as is, an error of one step will occur. Therefore, in order to avoid this, in the conventional digital-to-analog conversion circuit, it was necessary to provide a correction circuit in the preceding stage.

FIG. 11 shows an example of such a correction circuit. With this correction circuit 4l, the 5 bits other than the MSB of the digital signal input manually from the digital signal input terminal R42 are
Bits D0 to D are each branched into two. One of these is input to the selector 44 via the adder 43, and the other is input directly to the selector 44.

Further, D, which is the MSB, is input directly to the digital-to-analog conversion circuit 45 and is also input to the selector 44 .

The selector 44 selects the signal 47 to which 1 has been added by the adder 43 when the MSB, D, is logic "0", and sends it to the digital-to-analog conversion circuit 45. Further, when D5 is logic "1", the signal 48 from the digital signal input terminal 42 is directly transferred to the digital-to-analog conversion circuit 45.
give to Thereby, it is possible to correct a one-step error.

Such a correction circuit, as shown in FIG.
It is also possible to use a subtracter 49 instead of the adder 430 shown in the figure. In this case, when Ds is logic "1", the subtracter 49 selects the signal 51 from which 1 has been subtracted and sends it to the digital-to-analog conversion circuit 45. Further, when D is the logic "0", the signal 48 from the digital signal input terminal 42 is directly input to the digital-to-analog conversion circuit 4.
Give to 5. As a result, one-step error correction is performed.

[Problem to be solved by the invention]

As described above, when a conventional digital-to-analog conversion circuit converts a digital signal expressed in two's complement, a separate correction circuit is required, which has the disadvantage of increasing the amount of hardware.

Furthermore, when this correction is processed by software, there is a drawback that the processing amount of the processor increases and the burden becomes heavy.

Therefore, an object of the present invention is to eliminate the need for a correction circuit, etc., and to
An object of the present invention is to provide a digital-to-analog conversion circuit capable of directly converting a digital signal expressed in the complement of 2 to an analog signal.

[Means to solve the problem]

In the present invention, (1) a plurality of capacitors each having a capacitance weighted to a power of 2 so as to correspond to a bit other than the most significant bit of a digital signal, each having one electrode connected to a common electrode; A capacitive array consisting of (
ii) first and second reference potential terminals; and (iii) for connecting electrodes of the plurality of capacitors of the capacitance array opposite the electrode connected to the common electrode to the first or second reference potential terminal, respectively; (1v) a first switch for connecting the common electrode of the capacitor array to the first reference potential terminal; (■)
(V1) an additional capacitor having the same capacitance as the smallest of the plurality of capacitors in the capacitor array and having one electrode connected to the common electrode; and (V1) an electrode of this additional capacitor connected to the common electrode. Place the opposing electrodes in the first or second position.
a second switch for connecting to a reference potential terminal of (
vj) A digital-to-analog conversion circuit is provided with a switch control signal generation circuit that generates a plurality of control signals for controlling the switch array and the first and second switches based on manually input digital signals.

In the present invention, an additional capacitor having a capacitance equal to the minimum capacitance of this capacitor array is provided in parallel with the capacitor array weighted to the power of 2, and these capacitors of the capacitor array and the additional capacitor are manually operated. Switching control is performed so that the reference electrode is connected to the first or second reference electrode in accordance with the digital signal obtained.

5 Example 2 Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 shows a digital-to-analog conversion circuit in one embodiment of the present invention. This figure shows the conventional example (6th
The same parts as in FIG.

This circuit has a unit capacitance C. An additional capacitor 17 is provided which has a capacitance array l8 and is connected in parallel with the capacitor array l8. This additional capacitor 17 is operated by an additional switch 14 having the same configuration as the switch 15-0 of the switch array 15, depending on the value of the control signal SA from the control circuit 23.
First reference potential terminal 21 or second reference potential terminal 22
It is designed to be connected to. Other configurations are the 6th
This is similar to the conventional example shown in the figure.

FIG. 2 shows the control circuit 23 of FIG. 1 in detail. An output terminal 24 is separately provided in the control signal output terminal section 32 of this circuit, and the output of the OR gate 28 is output from this terminal as a control signal SA. The other configurations are similar to the conventional example shown in FIG.

In the end, in this control circuit 23, (1) to (
The switches 15-0 to 15-4 and the switches 16 and 14 (FIG. 1) are controlled by the equation (6) and the control signal shown by the following equation (18).

So = (CLK' + Ds) ' ((CLK
[15) + Do)... (1) S+ = (CLK' + Ds) ・((CLK
−Ds )+D,)・・・・・・(2》S2=(CLK' 10Os)・((CLK−Ds)
"D2)...(3) S3 = (CLK' + 05) ・
((CLK-Ds)" 03)...
... (4) S4 = (CLK' + Ds) ・((
CLK-Os)+D. )・・・・・・
(5) So = CLK
・・・=・ (6) General = CLK' + D
5 (1 8) However, CLK' indicates a value obtained by inverting the logic of CLK.

Next, the operation of the digital-to-analog conversion circuit configured as above will be explained.

Here, similarly to the conventional example, four cases will be explained based on combinations of the logic levels of D, which is the MSB of the input digital signal, and the clock signal CLK.

<a) When DS = “O” (a-1) Timing of CLK = “1” At this time, (
From equations 1) to (6) and (18), the control signal S0 to
34, and SA are all logic "0", and SG is logic "1". For this reason, switches 15-O to 15-4
, and the common terminal C of the additional switch 14 are all terminal G.
The switch 16 is turned on.

As a result, the relationship between the reference potential terminals 21, 22 and the analog output terminal 19 in FIG.
1).

At this time, the capacitors 1810 to 18 of the capacitor array 18
-4 and the additional capacitor 17 are all discharged, and the accumulated charge becomes zero.

(a-2) CLK= “O” (J) Timing At this time, from equations (1) to (6), the control signals S to S are the digital input signals D o input from the digital signal input terminal section 12, respectively. '= equal to the logic level of D-, and the control signal Sc becomes logic "0". Further, the control signal SA becomes logic "1". Therefore, the common terminals C of the switches 15-0 to 15-4 are Dl, to
It is connected to the side according to the logic level of D4. That is, the switch corresponding to the logic "0" bit of the digital human input signal is connected to the terminal G side, and the switch corresponding to the logic "1" bit is connected to the terminal R side. C is connected to the terminal R side.Thereby, the relationship between the reference potential terminals 21, 22 and the analog output terminal 19 is equivalently as shown in FIG. 3(a-2).

Therefore, the analog output potential V output from the analog output terminal 19 at this time. is expressed as the following equation (19).

vo = (Cx-Vc + (CY + CG)
・VR)/(CA Co) ”(CX − Vc, + (Cy + Co)
Va)/32C. −−−−−・(
19) For example, when a signal such as equation (10) shown below is given as a digital input signal, each switch 15-0 to 154 of the switch array 15
In order to reach the state shown in the figure, each CXC is 28Co
It becomes 3co.

(D., D3, D. D,, D
o) = (0, 0, 0, 1.1)...
(IO) Therefore, the analog output potential V. is expressed as the following equation (20) using equation (19).

し=(28/32). -Vc, -! - (4/3
2) ・v. ...... (2 0) Also, (0, 0. 0, 0. 0) and (1
, 1, 1. When a digital input signal L1) is given, the analog output potential V0 becomes as shown in the following equations (2l) and (22), respectively.

V. =(31/32) ・V.
+ (1/32) VR・・・・・・(
21) Vo = VR −−−・−(2
2) In the end, the digital human signal becomes (0, 0. 0,
0. 0) to (1, 1, 1, 1. 1)
Correspondingly, when the analog output potential V changes by 1 daigin l· up to V. changes from the value of equation (21) to the value of equation (22) by the amount Δ■' shown in equation (23) below.

ΔV' = (vu - VG) / 32 -=
-=- (2 3) (b) When Ds is "1" (b-1) Timing of CLK = "1" At this time, the control signals S.-S, SA, and S.. are all logic "1"
”. Therefore, the switches l5-0 to l5-4 and the common terminal C of the additional switch 14 are all connected to the terminal R side, and the switch 16 is turned on. As a result, the reference potential terminal 21 , 22, and the analog output terminal 19 are equivalently as shown in FIG.
0 to 18-4 and the additional capacitor 17 will be charged and discharged.

(b-2) Timing of CLK="0" In this case,
As in the case of (a-2), the control signal S. -34 is D respectively. -D, and the control signal S0 becomes logic "0" and SA becomes logic "1".Thereby, the relationship between the reference potential terminals 2l, 22 and the analog output terminal 19 is equivalently The result will be as shown in Fig. 4 (b-2).

In this case, capacitors 18-0 to 18 of capacitor array 18
-4 and the additional capacitor 17 have the above-mentioned (t)
-1), the analog output potential V at this time is the predetermined charge M multiplied at each timing. is the following (
24) It becomes as follows.

Vo = [(Cx-'l'G + ([:Y +
Co) ・VR)/32CO) +(VG −
VR )・・・・・・(2 4) Therefore, as a digital human signal (0, 0, 0,
0.0) and I: 1, 1, 1, 1. 1)
When the value is given, the analog output potential V
. are expressed as the following equations (25) and (26), respectively.

vo=2v. - VR:・-・(2
5) VO = v.・・・・・・
...(26) In the end, the digital human signal becomes (0, 0,
0, 0. 0) to (1,1,1.1.1)
), the analog output potential V corresponds to this change. changes from the value of equation (25) to the value of equation (26) by the amount ΔV' shown in equation (23).

As is clear from equations (21) and (26) among those explained above, the value of the digital input signal is (0, O,
0, 0. O, O) and (1, 1. 1
．． 1, 1. 1) Analog output potential V when
. will never have the same value.

FIG. 5 shows the digital human input signal D explained in (a-1) to (b-2). -D5, and the control signal So"'-S
This represents the relationship between s, Sc, , SA and the analog output potential V. As shown in this figure, the digital signal (0, 0, 0. 0, O, O)
The analog output levels corresponding to (1, 1 1, l, L 1) are "32" and "31", respectively.

Therefore, conversion to a 64-level digital signal can be performed without causing a single step error.

Note that in this embodiment, the clock signal CLK is at logic "0".
Although the additional capacitor 17 is connected to the second reference potential terminal 22 side at the timing of , it may be connected to the first reference potential terminal 21 side.

〔Effect of the invention〕

As explained above, according to this proposal, a capacitor having the same capacitance as the minimum capacitance of the capacitor array is provided in parallel with the capacitor array weighted to the power of two, so the two's complement The digital signal of the display can be directly converted to an analog signal. Therefore, there is no need for an additional circuit for correction, and there is an effect that the load placed on the blow sensor can be reduced.

[Brief explanation of drawings]

Figures 1 to 5 are for explaining one embodiment of the present invention, of which Figure 1 is a block diagram showing a digital-to-analog conversion circuit, and Figure 2 shows the control circuit in Figure 1 in detail. 3 is an explanatory diagram equivalently showing the state of the digital-to-analog conversion circuit when the most significant bit of the digital human input signal is logic "0," and FIG. 4 is an explanatory diagram equivalently showing the state of the digital to analog conversion circuit when the most significant bit of the digital human input signal is An explanatory diagram equivalently showing the state of the digital-to-analog conversion circuit when the signal is “1”; Figure 5 is an explanatory diagram showing the relationship between the digital input signal, the control signal, and the analog output level; and Figure 6 is the conventional digital-to-analog conversion circuit. FIG. 7 is a block diagram showing the control circuit of a conventional digital-to-analog conversion circuit in detail. FIG. 8 is a block diagram showing the conventional digital-to-analog conversion circuit when the most significant bit of the digital human input signal is logic "0". FIG. 9 is an explanatory diagram equivalently showing the state of the conversion circuit. FIG. 11 is an explanatory diagram showing the relationship between digital input signals, control signals, and analog output levels in a conventional digital-to-analog conversion circuit, and FIG. 11 is a block diagram showing an example of a correction circuit used in addition to the conventional digital-to-analog conversion circuit. , FIG. 12 is a block diagram showing another example of a correction circuit used in addition to a conventional digital-to-analog conversion circuit. 12...Digital signal input terminal section, 13...
...Clock signal input terminal, 14...Additional switch, l5...Switch array, 16...Switch, l7...Additional capacitor, 18. ...Capacitance array, 19...Analog output terminal, 2l...First reference potential terminal, 22...
- Second reference potential terminal, 23...control circuit, 25-0 to 25-4...OR gate, 27...
...and gate, 28...or gate,
33-0 to 33-4...AND gate, 32...Control signal output terminal section.

Claims (1)

[Claims] A capacitor having a capacitance weighted to a power of 2 so as to correspond to each bit other than the most significant bit of a digital signal, each having one electrode connected to a common electrode and connected to a plurality of capacitors. a capacitor array, first and second reference potential terminals, and electrodes of the plurality of capacitors of the capacitor array, which are opposite to the electrodes connected to the common electrode, connected to the first or second reference potential terminals, respectively; a switch array consisting of a plurality of switches for connection, a first switch for connecting the common electrode of the capacitor array to the first reference potential terminal; an additional capacitor having the same capacitance as the capacitance and having one electrode connected to the common electrode, and an electrode of the additional capacitor opposite to the electrode connected to the common electrode connected to the first or second reference capacitor; a second switch for connecting to a potential terminal; and a switch control signal generation unit that generates a plurality of control signals for controlling the switch array and the first and second switches based on the input digital signal. A digital-to-analog conversion circuit characterized by comprising a circuit.