JPH03214764A - Manufacture of semiconductor chip - Google Patents

Abstract

PURPOSE:To improve yield of a semiconductor chip by forming a plurality of functional blocks adjacent to a same wafer, sorting out the pass blocks from fail blocks, and dicing a plurality of pass and adjacent blocks as one chip. CONSTITUTION:Upper memory chip rows 20a having a plurality of upper memory chips A on a wafer 10 and lower memory chip rows 20b having a plurality of lower memory chips B are alternately formed. Accordingly, the laterally adjacent one of an arbitrary memory chip becomes a different memory chip. In this case, bonding pads 30 of the chip A to the chip B is formed only along upper and lower sides, and bonding pads are set at the same position in the same row. Then, the chips A, B are sorted to pass and fail ones. A plurality of pass and adjacent functional blocks are diced as one semiconductor chip 100. Thus, the yield of the chip 100 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor chip that improves the yield of a relatively large semiconductor chip composed of a plurality of types of functional blocks.

<Prior Art> A mask ROM will be described below as an example of a semiconductor chip.

Mask RO into which predetermined storage information is written during the manufacturing process
The M memory arrays can be roughly divided into an upper memory array belonging to an upper address and a lower memory array belonging to a lower address.

Only those memory arrays that are of good quality are commercialized as mask ROMs.

<Problems to be Solved by the Invention> However, the conventional mask ROM described above has the following problems.

That is, most of the area of the mask ROM is occupied by a high-density memory array. Therefore, most of the defects in mask ROMs occur in the memory array. That is,
If either the upper or lower memory array has a defect, the mask ROM will be defective even if the other memory array is good.

There are four combinations of good and defective products: ■ Both memory arrays are good, ■ Only the upper memory array is good, ■ Only the lower memory array is good, and ■ Both memory arrays are defective. Obtainable. Therefore, there is a certain limit to the improvement in yield.

The present invention was devised in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor chip that contributes to improving the yield of semiconductor chips composed of a plurality of functional blocks.

<Means for Solving the Problems> A method for manufacturing a semiconductor chip according to the present invention is a method for manufacturing a semiconductor chip consisting of a plurality of functional blocks, and includes a step of forming a plurality of functional blocks adjacent to each other on the same wafer. , a step of sorting the functional blocks into non-defective products and defective products, and a step of icing a plurality of non-defective and adjacent functional blocks as one semiconductor chip.

<Operation> Adjacent functional blocks among good functional blocks are glued together to form one semiconductor chip.

Embodiment> Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

The first part is an explanatory diagram showing one embodiment of the present invention, and the second part is an explanatory diagram showing another embodiment.

The method of manufacturing a semiconductor chip according to this embodiment is a method of manufacturing a mask ROM chip 100 that is composed of two functional blocks: an upper memory chip A belonging to an upper address and a lower memory chip B belonging to a lower address.

This manufacturing method will be explained step by step.

As shown in FIG. 1, an upper memory chip row 20a consisting of a plurality of upper memory chips A on each wafer 10;
Lower memory chip rows 20b each consisting of a plurality of lower memory chips B are alternately formed. Therefore, the horizontal neighbors of any given memory chip are different memory chips. Note that the bonding pads F'30 between the upper memory chip A and the lower memory chip B are formed only along the upper and lower two sides;
The bonding pads are set at the same position and in the same arrangement regardless of whether the upper memory chip A or the lower memory chip B is used. Further, the upper and lower memory chips A and B each have a chip selection terminal, and the active level of the chip selection terminal can be set to high or low when writing storage information.

Next, each of the memory chips A and B is sorted into non-defective products and defective products.

If we focus on a good upper memory chip A, we can see: ■Lower memory chip B is good on both sides, ■Lower memory chip B is good on the right and defective on the left, ■Lower memory chip is defective on the right and good on the left. The cases can be divided into four cases: (1) lower memory chip B, which is defective on both sides. At least, if good upper memory chip A and lower memory chip B are adjacent to each other, it is possible to form one mask ROM. Therefore, except in case (2), one mask ROM chip 100 can be obtained. I can do it. Therefore, one mask ROM chip 100 is obtained by guising the upper memory chip A and the lower memory chip B, which are good products, as a pair. At this time, there are two types of arrangement of the upper memory chip A and the lower memory chip B, as shown in FIGS. 1(b) and 1(C).

One mask ROM is completed through an assembly process in which this mask ROM chip 100 is bonded to a lead frame and sealed with a sealing resin. In addition, -F position memory chip A
The connection between the mask ROM chip 100 and the lower memory chip B is performed by bonding the mask ROM chip 100 on a lead frame or on a substrate on which the mask ROM is mounted.

Although the above embodiment describes a mask ROM consisting of two functional blocks, an upper memory chip A and a lower memory chip B, the present invention can also be applied to a case consisting of four functional blocks as follows. .

The semiconductor chip 100 according to this embodiment is composed of four functional blocks A, B, C, and D.

These four functional blocks A to D are arranged as shown in FIG. 2(a). Then, the four functional blocks A to D constituting one semiconductor chip 100 are 21F(b) to
Combination U is possible with the four types of arrangement shown in (e).

In this case, bonding pads 30 are formed along the upper and lower sides of each functional block A to D, but the upper and lower bonding pads 30 must be formed in exactly the same manner. This is because each functional block A-
This is because it has not been determined at the time when D is formed.

In the above-described embodiments, the mask ROM is used as an example of a semiconductor chip, but the present invention is not limited to this, and any semiconductor chip consisting of a plurality of functional blocks may be used. It is also possible to apply it to a composite chip that combines different chimps.

<Effects of the Invention> The method for manufacturing a semiconductor chip according to the present invention is a method for manufacturing a semiconductor chip for manufacturing a semiconductor chip consisting of a plurality of functional blocks, including the step of forming a plurality of functional blocks adjacent to the same wafer; This method is comprised of a process of sorting the functional blocks into good and defective products, and a process of dicing a plurality of non-defective and adjacent functional blocks as one semiconductor chip, so it is possible to improve the yield of semiconductor chips compared to conventional methods. can.

In particular, in semiconductor memories such as mask ROMs, the yield tends to deteriorate as the chip size increases, so it is possible to divide one semiconductor chip into multiple functional blocks and reduce the chip size of each as in the present invention. is an effective means of improving yield.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing one embodiment of the present invention, and FIG. 2 is an explanatory diagram showing another embodiment. 10... Wafer, 100... Mask ROM chip (semiconductor chip), A... Upper memory chip knob, B
...lower memory chip.

Claims (1)

[Claims] (1) In a semiconductor chip manufacturing method for manufacturing a semiconductor chip consisting of a plurality of functional blocks, a step of forming a plurality of functional blocks adjacent to the same wafer, and a step of sorting the functional blocks into good and defective products. and dicing a plurality of non-defective and adjacent functional blocks into one semiconductor chip.