JPH03214669A - Semiconductor storage device and redundant memory repair method - Google Patents

Abstract

PURPOSE:To attain a high speed and also a large storage capacity by disposing peripheral circuits in cross areas formed of a longitudinal central part and a lateral central part and by disposing memory arrays in four regions divided by the cross areas. CONSTITUTION:In a semiconductor chip or in each of areas divided by the longitudinal center line thereof, peripheral circuits are disposed in cross areas A to E formed of the longitudinal central part and the lateral central part thereof, while memory arrays M are disposed in four regions divided by the cross areas A to E. As the peripheral circuits are disposed in the central parts of the chip or in each of the areas according to this constitution, the maximum transmission path of signals can be shortened to the half of a chip size substantially, and therefore DRAM designed to have a large storage capacity can be made to operate at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device and a method for relieving defects thereof.
The present invention relates to a technique that is effective when used in a dynamic RAM (Random Access Memory) having a large storage capacity, for example, about 16M memory.

[Conventional technology]

Dynamic RAM having a large storage capacity of about 16M pinto is being developed.

An example of such a dynamic RAM is found in "Nikkei Microdevices" magazine, published by Nikkei McGraw-Hill on March 1, 1988, pages 67 to 81.

[Problem to be solved by the invention]

With the increase in storage capacity as described above, memory chips also inevitably become larger. Accordingly, special consideration must be given to reduction in speed due to miniaturization of elements and routing of wiring. In other words, in order to achieve a large storage capacity of approximately 16 Mbits, it is necessary to use 18 IM bits or approximately 4 Mbits.
This requires the development of new technology that is different from the technology used for AM.

An object of the present invention is to provide a semiconductor memory device with a large storage capacity.

Another object of the present invention is to provide a semiconductor memory device that achieves high speed and large storage capacity.

Another object of the present invention is to provide a rational defect relief method for a storage device with a large storage capacity.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, as a semiconductor memory device with a large storage capacity, peripheral circuits are arranged in a cross area consisting of a vertical center part and a horizontal center part of the semiconductor chip or both areas divided in half by the vertical center line. However, memory arrays are arranged in the four areas divided by the above-mentioned cross area. The X decoder and Y decoder are arranged at the edge of the cross area that is in contact with the memory array, and the main amplifier, common source switching circuit, and sense amplifier are placed in the area between the X decoders in the vertical or horizontal center. A control signal generation circuit, a mat selection control circuit, etc. are arranged. Among the peripheral circuits, circuits that have the possibility of injecting minority carriers into the substrate in principle are placed on or near the two center lines of the cross area. The memory array formed in the area divided into four by the above-mentioned cross area is constructed as an aggregate of a plurality of unit memory mats of the same size including sense amplifiers. The memory unit I-1 includes a control circuit that generates various timing signals for memory cell selection operations based on the Mbit selection signal. The control circuit is activated by the mat selection signal. The selection signal of the above memory mat is
It is assumed that it is formed by decoding an address signal input through a dedicated address buffer. Part or all of the honding pasodo is placed within the above-mentioned cross area. The bonding pad is bonded to the LOG lead frame. Among the above-mentioned bonding pads, a plurality of bands for supplying the power supply voltage and ground potential of the circuit are provided at appropriate intervals depending on the circuit block that requires them, and
A common LO that provides the circuit's power supply voltage and ground potential, respectively.
Connect each to the G lead frame. A memory array is arranged in the four regions divided by the cross area, and steps are provided at the four corners of the semiconductor chip.

An internal step-down voltage generation circuit is provided, which operates in response to a power supply voltage supplied from an external terminal and includes one or more output buffers for impedance conversion, which receives a reference voltage generated by a reference voltage generation circuit. The internal step-down voltage generation circuits are provided respectively corresponding to the memory array operating voltage and the peripheral circuit operating voltage.

21 The signal to be output formed by the internal circuit is the signal l corresponding to the power supply voltage supplied from the external terminal.
/ source follower type output MO in which the signal to be output is supplied to the gate through a level conversion circuit that converts it to
Drive SFET. The step-down voltage generated by the internal step-down voltage generation circuit is output from the output terminal of the data output buffer in a high-impedance state in the test mode, and the switch is controlled by the bootstrap voltage or external power supply voltage level signal. MOSF
Selectively output via ET. Selection signals for word lines and shared sense amplifiers are formed by a selection circuit whose operating voltage is a high voltage formed by boosting the internal step-down voltage. At least one pair of memory cell arrays are arranged symmetrically around a main amplifier, and the main amplifier is connected to the pair of memories via a switch circuit that is controlled in response to the selection operation of the pair of memory cell arrays. Selectively connect to the human output line of the cell array.

The shared sense amplifier has 22 operation modes in which both data lines on the selected side and the non-selected side are connected. Consists of CMOS configuration, sense amplifier, input buffer first stage circuit, output path sofa final stage circuit, main amplifier first stage circuit, input/output line pull-up MOS
Short M of FET, complementary data line and complementary input/output line
The threshold voltage of the diode-type MOSFET constituting the OSFET and charge pump circuit is set to a low threshold voltage.A pair of parallel bit lines are arranged in a bin 1 to line crossing system. The bit lines are replaced using a first metal wiring layer formed on the wiring layer constituting the hit line at the cross section. The layer is
It also constitutes a column selection line, and one column selection line is provided corresponding to two bit line pairs, and at a portion different from the bit line crossing portion, one bit line pair is connected to the other bit line pair. The wires are bent and arranged so as to overlap the wire pairs. A step buffering region made of a gummy wiring layer is provided between a stacked memory cell array portion and its peripheral circuit.

As a defect relief method, a memory array is constructed from a set of memory mats each having the same size of 23 mm including sense amplifiers, and a redundant word line and/or redundant data are connected to each memory mat. In addition to providing a redundant line, the number of redundant word lines and/or data lines made up of all the memory mats is less than the total number of redundant word lines and/or data lines that are provided in one memory mat. A decoder is provided for use in common with each of the memory mats or a block consisting of a plurality of memory mats.

At the output part of the word line or column selection circuit, a spare word line and/or a spare column selection line having wiring that intersects with a plurality of word lines and/or column selection lines is formed in advance to prevent defective word lines and column selection lines. /or When a defective data line occurs, the output line of the word line and/or column selection circuit is disconnected from the column selection line corresponding to the defective word line and/or data line by physical means, and the spare word line and /or connect to the preliminary column selection line. In the multi-pit multi-pit 24-hour test mode with multiple selection of column systems, only the defective data line or column selection line among the multiple selection data lines or column selection lines corresponds to the memory cell array divided into multiple memory blocks. The redundant data line or redundant column selection line is switched to redundant data line or redundant column selection line. Divide the data line into multiple blocks using an address signal of a specific bit of the row system and/or column system address signal, an internally formed block address, or a combination of the above address signal and block address, and specify the above block. This signal is used to switch defective data lines to redundant data lines only in blocks where defects exist.

[For production]

According to the above-mentioned means, the main timing signals extend from the center of the chip in all four directions, so the length of the Shinzuki wiring can be substantially shortened as the chip size increases.
It is possible to realize a large storage capacity and high speed of DRAM. By arranging circuits that may generate minority carriers on or near the two center lines of the cross area, the influence on the memory array can be minimized. The design and control of the memory mats can be simplified by forming a set of memory mats each having the same size and including sense amplifiers. Since the honting pad is connected to the 1-OC lead frame, the pads can be placed optimally. By providing a plurality of pads that supply the power supply voltage and ground potential of the circuit, the power supply impedance can be lowered. The stress from the resin mold can be dispersed by the steps provided at the corners. By providing an internal step-down voltage generation circuit, it is possible to reduce power consumption and prevent voltage breakdown due to element miniaturization. By forming a step-down voltage corresponding to the memory array operating voltage and the peripheral circuit operating voltage, the power supply noise margin can be increased. By converting the level and driving the output MOSFET, it is possible to secure the output level and increase the speed. The internal voltage can be monitored by placing the data output buffer in an output high-impedance state. By forming selection signals for the power input and shared sense amplifier using a boosted power supply, high speed and stability can be achieved. The circuit can be simplified by making the main amplifier compatible with multiple memory cell arrays. By connecting the share-1 sense amplifier to the screen data line, a margin test of the sense amplifier can be performed. MOSF with low threshold voltage
By using ET, it is possible to increase the speed and minimize the level drop. High integration becomes possible by replacing the bit lines using a metal wiring layer formed on the bit lines. The metal wiring layer described above can also be used as a column selection line. The step buffering area prevents the wiring from breaking at the step.

As a defect relief method, redundant decoders can be used for a large number of memory mats, making it possible to simplify redundant circuits. By directly switching from a defective data line or word line to a spare data line or word line, circuit simplification and high-speed operation can be realized. By switching only the defective circuit in the multi-viso I/simultaneous test 1 mode by multiple selection of the Y system, the spare circuit can be simplified. Easy configuration by using signals to specify blocks
7. Relief from failure becomes possible.

〔Example〕

FIG. 1 shows a dynamic type RA to which this invention is applied.
A basic layout diagram of one embodiment of M is shown.

In this embodiment, in order to prevent the operation speed from slowing down due to the lengthening of various wiring such as control signals and memory array drive signals due to the increase in chip size due to the increase in memory capacity, etc. , the following arrangement is made in the arrangement of the memory array section that constitutes the RAM and the peripheral section that performs address selection and the like.

In the figure, a cross area formed by the vertical center and the horizontal center of the chip is provided. Peripheral circuits are mainly placed in this cross area, and the cross area
A memory array is arranged in the divided areas.

The above-mentioned cross area is divided into areas ``Area Person'' to ``D'' as shown in the figure. Area A is the left side of the lateral center of the chip, and area 28B is the right side of the lateral center of the chip. Area C is the upper vertical center of the chip, and area D is the lower vertical center of the chip. Area E is the central part of the chip where the horizontal central part and vertical central part of the chip intersect.

In the memory chip of this embodiment, a memory array is formed into four areas divided by the above-mentioned cross areas consisting of areas A to E. Although not particularly limited, the above 4
Each of the two memory arrays is approximately 4M, as described below.
It is designed to have a storage capacity of 1. Accordingly, the four memory arrays as a whole have a large storage capacity of approximately 16 Mbits.

In the periphery of the cross area adjacent to each memory array, a decoder and a driver for selecting the memory array are arranged.

In other words, out of areas A and B, 2
Corresponding to each memory array, Y (column) decoder (Ydec) and Y select (column selection) driver (
YS driver) are arranged 29 respectively. Of areas C and D, X (row) decoders (X
dec) and a word line driver (WL driver) are respectively arranged. Therefore, in the memory array divided into four, the word 1 line is extended in the horizontal direction, and the data line (bit line or digital 1 line) is extended in the vertical direction.

However, as described above, one memory array has a large storage capacity of about 4 Mbits, so the number of memory cells connected to one data line etc. becomes enormous, which is impractical. Therefore, each memory array is composed of a plurality of memory mats, as will be described later.

The following main circuit blocks are arranged in the remaining portions of each of the above-mentioned cross areas. In area A and area B, an air I/res buffer, an address comparison circuit (redundant decoder), a control cross signal generation circuit, a data input buffer, etc. are arranged. In area C and area D, a common source switching circuit, a sense amplifier control signal No. 30 circuit, a mat selection control circuit, a main amplifier, etc. are arranged. In the central area E, an X decoder, a Y decoder address signal generation circuit, an internal step-down power supply circuit, etc. are arranged.

FIG. 2 shows an overall layout diagram of an embodiment of the dynamometer type RAM according to the present invention. That is,
A portion corresponding to the area A is provided with a Y-system circuit consisting of a Y-address huffer, a Y-redundancy circuit, and a Y-address driver (logic stage), a test function circuit, and a CAS-system control signal circuit. There are approximately 5
(2) An internal step-down voltage V that receives an external power supply voltage VCCB and converts it into a voltage such as approximately 3.3V that is supplied to the memory array.
A Y address driver, an X address driver, and a mat selection driver indicated by V3 are provided.

The part corresponding to area B includes an X-system circuit consisting of an X-address buffer, an X-redundant circuit, and an is provided. Near the center of this area B, there is an internal step-down voltage vCC that receives an external power supply VCCB of approximately 5 cm and converts it into a voltage of approximately 3.3 cm that is supplied to the peripheral circuits.
A limiter circuit and a Y address driver, an X address driver, and a mat selection driver indicated by DV1 to DV3 are provided, respectively.

As shown in Areas A and B above, if the address path sofa and its corresponding redundant circuits including address comparison circuits, CAS and RAS system control signal circuits that generate control clocks, etc. are placed in one place, for example, with a wiring channel in between. By distributing the cross-cross generation circuit and other circuits, in other words, by sharing the wiring channels mentioned above, it is possible to achieve high integration, and it is also possible to transmit signals to the address driver (logic stage), etc. at the shortest possible distance. Since it is possible to do this, the speed can be increased.

The part corresponding to area C has four main amplifiers corresponding to a total of eight 32 memory mats arranged symmetrically with respect to the central axis of area C, an internal boost voltage circuit VCHG, and a substrate voltage generator. Four main amplifiers are provided corresponding to the circuit VBBG and the remaining eight memory mats arranged symmetrically with respect to the center axis of the area C as described above. Therefore, in this example, 1
Eight memory mats are arranged in one memory array,
The two memory arrays arranged symmetrically with the area C as the center provide a total of 16 memory mats. By arranging the main amplifiers in this way, the number of main amplifiers can be reduced and the signal propagation distance can also be shortened, making it possible to increase the speed.

In the area corresponding to the area D, there are four main amplifiers corresponding to a total of eight memory mats arranged symmetrically with respect to the central axis of the area D, a data output buffer consisting of four, and the above-mentioned data output buffer. Similarly, the remaining 8 memory maps 1 are arranged symmetrically with respect to the central axis of area D.
・Four main amplifiers corresponding to the following are provided. Therefore, since this 33rd embodiment is composed of four memory arrays as described above, there are a total of 32 memory mats.

Although not particularly limited, in this embodiment, a bonding pad indicated by a small opening is arranged in the vertically central area. The detailed arrangement of this bonding pad is specifically shown in the layout diagram of FIG. In the figure, among the bonding pads indicated by openings, those filled in black are pads for external power supply. That is, in order to increase the input level margin, in other words, to lower the power source impedance, a total of 13 pads VSS that supply the ground potential of the circuit are arranged in a straight line. These pads VSS are r-
It is connected to a vertically extending ground potential lead formed by oc technology. Of these pads SS, one pad SS is provided in each of areas C and D, and is used as a ground potential for clearing word lines and preventing unselected word lines of the word driver from rising due to compression.

34 The two pads provided in areas C and D are
Provided for common source VSS of sense amplifier.
Achieves higher speed by lowering common source wiring resistance. In area D, in addition to the above, there are two data output paso sofas,
Area E is provided with a power supply generating circuit for supplying ground potential to the X address buffer and Y address buffer. And 1 each in areas C and D.
The two bands provided at each area correspond to other peripheral circuits. As a result, the ground potential of the circuit has a low power supply impedance with respect to the operation of the internal circuit, and the SS wiring between the internal circuits, which are divided into five types as described above, is separated from the LOG lead frame and the bonding wire. Since it is connected with a low-pass filter that minimizes noise generation,
Propagation of vSS noise between internal circuits can also be minimized.

Bands compatible with external power supply VCCE such as about 5V are
Internal step-down voltage generator 35 that performs the above voltage conversion operation. Two in the center corresponding to the raw circuit VCC limiter and VDL limiter, and one in the position corresponding to the data output buffer.
Each is provided. This also lowers the power supply impedance as described above, and also reduces the voltage between internal circuits (VCC, V D
This is to suppress noise propagation (between L and VCCE).

Address input pads AO-All are arranged together in the center. This is to minimize signal transmission distance and increase speed by providing the X address buffer and Y address buffer close to each other in accordance with the arrangement.

Pad RAS. for control signals. ．． CAS, W.E. ．． The OEs are placed close to their respective circuits. Data output pads DQI to DQ4 are provided in each data output buffer. Pasodo D is for data input in the x1 bit configuration, and Q is for data output in the x1 pinto configuration.

The above are pads for external pins.

In this embodiment, in addition to the above-mentioned external pins, the following bands 4.1 are provided for bonding master, monitor, and monitor 36 pad control.

Pasodo FPO and FPI for pounding master
is provided. FPO is for specifying the SC (static column) mode, and FPI is for specifying the NB (nibble) mode and the write mask function in the x4 bison configuration. Bad VCC, VDL, V L, VBB, VCH and VPL for monitoring.
There is. These pads are connected to the corresponding internal voltages VCC, VDLXVL, VBBXVCI-1 and V P
L. This is for monitoring. VCC is approximately 3
．． The power supply voltage for peripheral circuits is 3V, and VDL is approximately 3.3
VCH is the power supply voltage supplied to the V memory array, that is, the sense amplifier. The power supply voltage, VBB, is the substrate bias voltage such as -2.V, VPL is the play voltage of the memory cell, and VL is approximately 3.
This is the reference voltage for the 3V VCC limiter and VDL limiter. PASO 37 for monitor, PASODO VBT, VHT and VPLG for control.
There is. These functions will become clear from the discussion of monitor voltage functions below.

In this embodiment, the homing pabits are arranged in two rows. Moreover, the pitches are shifted by about half a pinch and arranged alternately. In other words, a plurality of pounding pads are arranged in a zigzag pattern. This allows the substantial distance between the pads to be increased. In other words, a large number of bonding pads can be arranged with high density in a relatively narrow area.

The bonding pad requires a relatively large area for bonding such as wire bonding, and it is necessary to provide an electrostatic breakdown prevention circuit, so it is necessary to make the pinch relatively large. . Therefore, by using the zigzag arrangement as in this embodiment, it is possible to arrange a large number of bonding pads in a relatively narrow area. Further, in a configuration in which bonding pads are arranged in the vertical center of a vertically long chip, a larger number of pads can be provided as shown in Section 38.

FIG. 4 shows a block diagram of an embodiment of address allocation for the memory array having the above configuration.

The RAM of this embodiment has a storage capacity of about 16Mbiso1, as described above. The address signal adopts an address multiplex method in which an X address signal and a Y address signal are supplied in time series in synchronization with address strobe signals RAS and CAS. Therefore, as an address signal, the X address signal is 1 of XO to Xll.
2 bits, and the Y address signal is each composed of 12 bits of YO-Yll. In the figure, the address signal XO-Xll is a true signal that means a selected state when the address signal supplied from the outside is high level,
Address signals XOB-XIIB are bar signals that indicate a selected state when an externally supplied address signal is low rail. Similarly, address signals YO to Yll are I-Lou signals that indicate a selected state when an externally supplied address signal is at a high level, and address signals YOB to YilB are This is a H signal which means a selected state when it is at a low level.

The memory array is divided into four regions as described above, with the minimum unit being two regions SL and SR with a sense amplifier in between, and the corresponding X decoder, word line driver, and column selection circuit. Eight unit memory mats are arranged. These unit memory mats are MSOL, MSOR or MS 3 L, M
It can be divided into 8 types like S 3 R. Although the memory array divided into four as described above has eight memory mats each, MSOL, MSOR or M
S3L and MS3R are each allocated to four memory mats.

The X7-coder of the above-mentioned memory mat bit contains 8 bits of address signals XO to X7, 40 SL and SR signals that specify the two areas sandwiching the sense amplifier, and the memory mat. MS to specify
OL/R-MS 3 L/R signals are supplied.

One memory mat has 512 word lines.

The memory mat of the above unit has complementary data lines (bit 1 line or digit bit line) on the left and right with the sense amplifier in the center.
A so-called shared sense amplifier method is adopted in which This left and right addressing signal SL
, SR are used with address signals X8 and X8B. Therefore, the X decoder circuit essentially has the function of decoding the 9-bit address signal of XO-X8 and selecting one word line.

The 3-bit address signals X9 to Xll form the mat selection signal MS I L/R. That is, address signals X9 and
Select adjacent memory mats as shown in L, and use address signals X11 and Assuming that the two memory mats to be used are lMi, one of the left and right memory blocks of 2'7LJA is selected. and,
Address signals XIO and Xi OB are used to select one of the memory arrays divided by areas in the vertical center of the figure. By combining the address signals consisting of 3 bits I and 1 as described above, each unit of memory mat has eight address assignment MSs as described above.
O~3L/R is specified.

When the X address signal is taken in in synchronization with the row address 1 lobe signal RAS, an X system selection operation is performed. At this time, due to the address allocation described above, among the four memory arrays, the address signals XIO and
Depending on i OB, one of the memory arrays divided into two with the vertical center area in between is selected. Then, one of the memory mats to which R or L is added is selected according to the address signals Xll and XiIB, and one of the 42 adjacent memory mats is designated by the address signals X9 and X9B.

Therefore, one word line designated by the address signal (XO to X8) consisting of the remaining 9 bits is selected in each of the four memory mats out of a total of 32 memory mats.

A Y decoder provided corresponding to each memory array (8 memory mats in total) decodes Y address signals Y2 to Y9 to select a complementary data line of the memory array. That is, by decoding the 8-bit address signal consisting of Y2 to Y9, a 1/256 address selection operation is performed. However, the column selection circuit performs a complementary data line selection operation in units of 4 bins 1. Therefore, one memory mat has a storage capacity of 512X256X4, and one memory array has 8 memory mats, so the total memory array has a storage capacity of 512X256X4.
It has a storage capacity of approximately 4 MbisoI.56X4X8=4194304. Therefore, since the entire DRAM is composed of four memory arrays, it has a large storage capacity of about 16M memory.

Here, one set consists of four memory mats consisting of memory mats MSOL to MS3L, and another set consists of four memory mats consisting of adjacent memory mats MSOR to MS3R, for a total of eight memory mats.
Two memory blocks are configured. Four main amplifiers MA are provided for this memory block.

By determining the row address as described above, the eight memory mats MSOL to MS3L and MSOR to MS3 that constitute one memory block as described above are
Of R, address signals XIO, XIOB as mentioned above
and 3 Hiso1 consisting of Xll, XIIB and X9, X9B
One memory mat is selected by the address I word, and the signal consisting of the 4 bits is outputted corresponding to the 4 main amplifiers.

Among the Y address signals, one of the four main amplifiers ASO-AS3 is selected by the address signals YO and Yl. Then, one of the four main amplifier groups NAO-NA3 is selected based on the remaining address signals YIO and Yll. In this way, the address signals YO, Yl consisting of the above 4 bits are
One of the total 16 main amplifiers is activated by YIO and Yll, and a 1-bit read signal is outputted through the data output circuit.

Note that when accessing the memory in 4-bit units, addresses YIO and Y11 are disabled and the address I/O signal YO is selected from among the four main amplifier groups, although there are no particular restrictions.
The signals of a total of four main amplifiers specified by Y1 and Y1 may be output in parallel. Furthermore, in a read operation in nibble mode, although not particularly limited, the main amplifier is connected to address signals YO and Y1 or YI.
Address increments O and Yll to serially write 4 bits 1.
can be output.

FIG. 7 shows a schematic layout diagram for specifically explaining the relationship between the power supply line, its related internal power supply circuit, and pads.

45 1 is a pad VCCE for external power supply, from which the above-mentioned power supply voltage is supplied to the internal step-down power supply circuit (VCC) 3 through a wiring layer. The internal step-down power supply circuit (CC) 3 is approximately 5.
It receives a power supply from the power supply voltage (2) CCE, and forms an internal voltage VCC for peripheral circuits of about 3.3V in accordance with the reference voltage VL mentioned above. This voltage VCC is
The wiring 5 extends horizontally and is used to supply operating voltage to address buffers, decoders, and the like. Also, wiring 5
For example, it branches into two at about the center and extends vertically. This corresponds to the power supply for the X decoder, main amplifier, etc. as described above. The wiring 5 is branched and extended in the vertical direction as described above, and is connected to a Y decoder,
It branches into multiple branches and extends horizontally at locations corresponding to redundant circuits.

2 is a pad VCCE for external power supply, from which the power supply voltage VCC is connected to the internal step-down power supply circuit (VDL) 4 in the wiring layer.
Supply E. The internal step-down power supply circuit (VDL) 4 is supplied with power from the power supply voltage CCE as shown in approximately 5. (amplifier) to form the operating voltage VDL of the amplifier. This voltage VD
L is arranged in a Japanese-shape as a whole by the wiring 6.

That is, the wiring 6 extends horizontally from the output point of the internal voltage step-down power supply circuit (VDL) 4, and is arranged in a rectangular shape so as to inwardly surround the wiring A5 extending in the vertical direction. In this way, the wiring 6 is made to form the above-mentioned Japanese character. Reference numeral 7 denotes a power supply bat for the data output buffer and the guard ring, which extends left and right from there and is arranged vertically in parallel so as to surround the pad, main amplifier, etc. in the vertical center. The upper and lower ends are formed so as to surround the entire chip. This provides a guard ring function.

FIG. 8 shows a schematic layout diagram for specifically explaining the relationship between the ground line of the circuit, its associated internal power supply circuit, and pads.

Reference numeral 11 provided at the upper and lower ends of the central part of the chip is a 47-password VSS for supplying ground potential for word clear and word line latching. and is extended vertically. Further, they extend in the horizontal direction, and extend in the vertical direction and are connected to each other at the end corresponding to the word clear section. Reference numeral 12 denotes a ground potential pad for the common source of the sense amplifier, which supplies a ground potential for activating the sense amplifier. In this embodiment, they are arranged vertically symmetrically with respect to the lateral center. On the upper side, the above-mentioned hands are provided in two places and extend laterally from each of them, and a power switch MOSFE is provided to supply the ground potential to the sense amplifier.
It extends in the vertical direction corresponding to the location where the T is provided. Reference numeral 13 supplies a ground potential to the data output buffers, and is composed of two pabits arranged corresponding to the four data output buffers and wiring connecting them.

Reference numeral 14 denotes a ground potential pad for internal step-down power supply circuits VCC and VDL and an address buffer, and is connected to wiring extending in the left and right directions. Reference numeral 15 denotes a ground potential pad for other circuits, which is used to supply ground potential to circuits other than the above, such as the decoder circuit and the main amplifier. Therefore, since there are many circuits that supply ground potential and they cover a wide area, there are as many as four pads, and the wiring connected to them is arranged horizontally and horizontally as shown in the figure. Extended vertically in a relatively complex manner. In this embodiment, as described above, the grounding wires are divided into 5 to 5 types depending on the respective circuit functions, and are commonly connected by a lead frame having a LOG configuration. This suppresses noise leakage between circuits having separate ground lines as described above, thereby increasing the noise margin. For example, an address buffer with a tight noise margin can be provided with a ground potential through an independent pad 14 and relatively short wiring, so that a sufficient input noise margin can be ensured.

This is intended to substantially separate parts such as sense amplifiers that generate relatively large noises on the ground line due to their operation from circuits that are sensitive to noise as described above.

49 FIGS. 9(A) and 9(B) show a specific layer '71 diagram and a cross-sectional view thereof of an input protection circuit provided corresponding to the above-described bonding pad.

In this example, although not particularly limited, as is clear from the layout diagram (A) and its partial sectional view (B),
A lateral type hyperpolar transistor of N"-PWE LL (substrate) - N1 is used as the protection element. In this case, both voltages VCCB and VSS are used as the emitter. High voltage (positive/negative) is used for the input. When is applied, the potential is relaxed by this lateral transistor, but in this embodiment, as shown in Layout 1 in Figure (A), the potential is further transmitted to the input gate by a high resistance element made of polysilicon. I'm trying to lower the potential.

The resistance value of this high resistance element is determined by the transmission speed of the input signal.
Although it cannot be made very high from the viewpoint of
Approximately 0Ω is appropriate from the point of view of signal transmission function and protection function.

A guard ring formed by 50 N is provided around the NWELL (N-type well region) to prevent an abnormal voltage at the input section from having an adverse effect on the peripheral circuits. This guard ring is supplied with a voltage VCCB supplied from the outside.

When the bonding butt is placed in the center of the chip as in this embodiment, the memory array and peripheral circuits are more susceptible to surge voltage than when it is placed on the periphery of the chip as in the prior art. Therefore, the bonding pad is surrounded by a guard ring as a well-equipped diffusion layer as described above, and the external power supply voltage VCCE level is supplied thereto to reduce the influence of surge voltage passing through the substrate.

Further, the purpose of using a lateral type high-bolar transistor as in this embodiment is as follows. Lateral type transistors can be made smaller in area, so collectors,
By increasing the facing length (base width) of the N-spreading layer, which becomes the emitter, and reducing the current value per resisting length to prevent current concentration, and adding a special process to form it. There's no need to.

5 1 In the figure, A L 2 is the second aluminum layer, and ALL is the first aluminum layer. Further, S i L is an opening layer of pannosification, and TC is a through hole connecting the second aluminum layer A L 2 and the first aluminum layer ALI.

FIG. 10 shows a specific layout 1 of the input protection circuit provided at the external power supply voltage VCCE pad.

When a high voltage is applied to the VCCE pad, NWELL
-PWELL (Substrate) - NW'E L J-, lateral type bipolar!・Use a transistor to release the charge to the ground potential ■SS. This protection element is provided at the top and bottom ends of the vertical center portion of the chip. As a result, a high voltage can be lowered at the entrance of a lead running vertically in the center of the chisop in the LOC structure as described below. By adopting such a configuration, instead of providing protection elements in one-to-one correspondence with multiple power supply pads provided, the protection elements 52 are provided only on a pair of butts near the lead population. In particular, it is possible to prevent high voltage from being applied to the band corresponding to the central portion of the lead.

FIG. 11 shows a layout diagram of the peripheral area of the semiconductor chip, and FIG. 12 shows a part of FIG. 11 and a cross-sectional view of a memory cell (not shown).

In this embodiment, as described above, a configuration is adopted in which the peripheral circuits and the bonding circuit 1 are arranged in the vertical and horizontal centers of the chip.

Therefore, memory arrays are arranged around the periphery and all four corners of the chip. In this case, at the four corners of the chip, there is a risk that cracks may occur in the puffiness or the like due to the stress caused by the resin of the passocage. In order to prevent this, in other words, to strengthen the mechanical strength, the memory array process is used as shown in the same figure.
G (polysilicon gate electrode of MOS+- transistor)
, WS i/Poly S i (polycide layer forming complementary data lines). Then, as shown in the schematic cross-sectional view of FIG. 12, the first aluminum layer ALi and the second aluminum layer AL2 are superimposed via the glabella insulating film.

By providing such a gentle step at a part of the corner of the chip, stress caused by the resin is prevented from being applied directly to the memory array section. In addition, some corner FC. ．． W
Stress can be dispersed by increasing the length of S i /Poly S i.

Furthermore, as shown in the layout diagram of FIG. 11 and the cross-sectional view of FIG.
The substrate high-ass voltage VBB is supplied by the second aluminum layer AL2.

Then, NWELT is placed inside it as a guard ring, and NWELT is placed in the center as a guard ring.
+ is formed, and the external power supply voltage VC is applied thereto by the first aluminum layer ALI and the second aluminum layer A L2.
CE is supplied.

The guard ring by NWELL is approximately - formed by the substrate hack high-ass voltage generation circuit V B B G.
When a voltage such as 2V suddenly changes for some reason, the substrate high-ass voltage VBB is applied.
It has the effect of absorbing carriers. As a result, the above P'
It is possible to prevent the minority carriers generated from the diffusion layer from proceeding to the memory array side and combining with the information charges accumulated in the storage capacitor of the memory cell, thereby preventing the amount of information from being reduced or destroyed.

FIG. 5 shows a block diagram focusing on control signals in the dynamic RAM according to the present invention. This figure is drawn corresponding to the layout diagram shown in FIG. 2 and the like.

The RAS system control circuit receives the signal RAS and outputs
Used to activate address buffer. The address signal taken into the X address buffer is supplied to the X system redundancy circuit. Here, a comparison is made with the stored defective address to determine whether or not to switch to a redundant circuit.

The result and the address signal are supplied to the X-system BRI decoder. Here, a predecode signal consisting of Xi and AXnl is formed, and an X address driver XiB provided corresponding to each memoria 55 ray is
, AXn 11, the signal is supplied to each X decoder provided corresponding to the memory mat as described above.

In the figure, only one dryer is exemplarily shown as a representative.

On the other hand, the RAS system internal signals are supplied to the WE system control circuit and the CAS system control circuit. For example, automatic refresh mode (CBR), test mode (WCBR), etc. are identified by determining the input order of the RAS signal, CAS signal, and WE signal.

In the test mode, the test circuit is activated and a test function is set according to a specific address signal supplied at that time.

Among the address signals taken into the X address buffer, the address signal instructing the selection of a memory mat is transmitted to the mat selection circuit MSiL/R, from which one of the plurality of memory mats provided in each memory array is selected. is selected. Here, the CS provided corresponding to the memory mat is a 56 common source switch MOSFET.

As shown in the address allocation shown in FIG. 4, the four main amplifiers MA are connected to four pairs of complementary data lines (4 bits) from a total of eight memory mats arranged symmetrically around the four main amplifiers MA. It corresponds to One of the eight memory mats is selected by the memory mat selection signal MSiL/R.
is selected.

The unit mat control circuit UM performs this selection operation.
It is C. In the figure, four pairs of main amplifiers MA are exemplarily shown as one set, and the remaining three sets of main amplifiers are shown as black box boxes by broken lines.

The mat selection circuit 11MsiL/R receives the selection signal MSOL/
Form H to MS3 L/R. For example, when MSOL is formed, four memory mats corresponding to M SO f- shown in FIG. 4 are selected. These four memory mats MSOL each have a 4-bit input/output node, which is connected to each of the four main mats M
Corresponds to A.

The CAS system control circuit is used to receive the signal CAS and form various Y system control signals. The address signal taken into the Y address path sofa in synchronization with the change of the signal CAS to low level is supplied to the Y system redundant circuit. Here, a comparison is made with the stored defective address to determine whether or not to switch to a redundant circuit. The result and the address signal are supplied to the Y-system predecoder. Here, a predecoded signal consisting of Yi and AYn 1 is formed. These predecode signals Yi and AYnl are supplied to a Y address driver (final stage) Yi provided corresponding to each of the four memory arrays.
B. ．． It is supplied to each Y decoder via AYnl. In the figure, one Y dryer YiB, A
Only Yn IB is exemplarily shown as a representative.

On the other hand, when the CAS control circuit receives the RAS signal and the WE signal as described above and determines the test mode based on the input order, it activates the adjacent test circuit.

Although not shown in the figure, bonding pads to which address signals and 58 control signals are supplied are arranged in a concentrated manner in the center of the chip. Therefore, the distance from each pad to the corresponding circuit can be made short and fairly uniform. As a result, by adopting a layout like this embodiment, address signals and control signals can be taken in at high speed, and in the case of an address signal consisting of a large number of bits, it is possible to take in address signals consisting of a large number of bits. Skew can be minimized.

Further, as shown in the figure, the power supply VDL for the sense amplifier (SA) and the power supply VCC for the peripheral circuit are also arranged in the center of the chip. As a result, various voltages can be supplied to the circuits arranged at the four corners of the chip by means of equidistant and short wiring. In addition, although not shown, capacitors with relatively large capacitance values for voltage stabilization, or in other words, for lowering power supply impedance, are distributed along each power supply wiring within the circuit for each circuit. It will be done.

FIG. 6 shows a block diagram focusing on the operation sequence 59 in the ×1 bit configuration. In the figure, each circuit block is mainly shown by a signal name, and the main circuits are shown by a circuit name. Therefore, the signal path showing the flow of write/read signals is omitted in the figure.

Referring to FIG. 6, an outline of the operation of the dynamic RAM according to the present invention will be described below.

The row-related address selection operation is performed as follows.

Address signals Ai (AO to A11) and, apart from these, address signals A9 to All and A8 are respectively taken into the address path sofa in synchronization with the row address 1 lobe signal RAS, and are used as row-related internal address signals. BX
i, MSiL, MSiR and SL, SR. The address signal BXi taken into the address buffer is input to a redundancy circuit on the one hand, and it is determined whether the memory access is to a defective address or not. The address signal BXi is supplied to the predecoder on the other hand, and a predecode signal AXNL is formed 60.
Powered by Da X-DEC. Address signal A8~All
, another set of buffers MSiL as above
, MSiR and SLXSR are provided to speed up mat selection operations. That is, the address signal AO-All is supplied to a redundant circuit and a predecode circuit, and is inputted to a large number of address comparison circuits and a large number of gate circuits in the redundant circuit, making the load relatively heavy. In this embodiment, by providing the address amplifiers MSil, . Since there is no influence on the receiving number, the speed becomes faster as described above.

The X decoder X-DEC has mat selection signals M S i L/R and SL, which control its operation timing.
X decoder precharge signal XDP formed from SR
and the X decoder extraction signal XDG are input. The X decoder
XNL is decoded to form a word line selection signal.

At this time, when accessing a defective address, the signal XRiB output from the redundant circuit is generated, and the word line selection operation by the output of the X-decoder X-DEC is prohibited, and the redundant word line selection operation is disabled. It will be done. For such a word line selection operation, the boosted voltage VCH as described above is used. As a result, the address selection MOSFET whose gate is coupled to the word line
Regardless of the threshold voltage of ET, signal charges are exchanged between the memory cell and the complementary data line without any level loss.

The mat selection signal MSiL/R forms a complementary data line precharge signal PCB. In other words, the above Maso l
- Since the memory map bit selected by the selection signal MSiL/R is determined, the precharge operation is canceled (completed) only for the complementary data line of the selected map bit. For the left region S L or 62 of the memory mat designated by the address signal 88, a selection signal S L/S R designating the right region SR is formed. This signal SL/SR and mat selection signal MSiL
/R to the region SL or S to be coupled to the sense amplifier
Selection signal SH that controls the switch MOSFET that selects R
R is formed. Here, as this selection signal SHR, the boosted voltage VCH as described above is used. As a result, signals can be exchanged between the sense amplifier and the selected complementary data line without any level loss.

The sense amplifier receives power switch MOSFET control signals PNI and PP1 generated from the RAS signal, the word line selection signal and mat selection signal M S i L /
It is activated when each condition of R is met. At this time, the sense amplifier outputs a voltage VD which is internally stepped down as described above.
Activated by L.

At this time, although not shown, a two-stage amplification operation is performed to reduce the peak current accompanying the operation of the sense amplifier. That is, in the first stage, the switch M, which conducts a relatively small current,
The MOSFET is turned on to activate the sense amplifier, and in the second stage, when the amplified output becomes comparatively large, the MOSFET switch, which allows a relatively large current to flow, is turned on to perform high-speed amplification. make the action take place.

Signal RG is a signal that determines the timing to turn on the Y switch MOSFET. That is, the signal RG is generated after a sufficient amount of signal is obtained on the complementary data line,
Controls the timing of column-related selection operations, which will be described later.

Signals RN and RF are determination signals for normal read mode and refresh mode. When the signal CAS changes from a high level to a low level before the signal RAS changes from a high level to a low level, a signal RF is generated and a refresh mode 1 (CAS before RAS refresh) is generated.

In this case, the subsequent column-related address selection operation is omitted by the signal CE.

When the signal RAS is at low level, when the signal CAS changes from high level to low level, the normal mode signal R
N is formed. In response to this, a signal CE for controlling read/write is generated.

64 Address signal BYi taken into Y address buffer
is supplied to a Y-system redundant circuit and a predecoder circuit to form a predecode signal AYNL. Signal ACIB is a signal that controls the operation of the main amplifier and Y decoder system, and is generated in response to changes in the address signal when signal CE falls and when signal CE is at high level.

In the redundant circuit, a signal YiB is generated when there is no failed address, and a signal YRiB is generated when there is a rescue address.

If there is no defect relief, the Y decoder Y-DEC decodes the pre-decode signal AYNL to form a Y (column) selection signal, and if there is defect relief, it invalidates the address selection corresponding to the pre-decode signal AYNL. A Y (column) selection signal for relief is formed.

A write signal W2 is generated from the signal WE. Signal CAS
A signal C2 is formed from the signal C2. This signal C2 is R A S
/ C.A. It is used to control S logic, read/write discrimination, each seta knob, and hold characteristics. Signal W3B is a read/modify line.
This is a one-shot pulse for performing an operation and an early write operation, and an internal write pulse is generated based on this one-shot pulse.

The signal WYP is connected from the data input buffer to the input/output line ■/○
The signal WYPB is used to control the input/output line I/O
It takes charge of control of the complementary data line from. The signal DL determines the data set bit assep/halt time when the write signal Din is taken into the data manual buffer. The write data DOi taken into the data input buffer is input/output by the signal WYP &? Conveyed to II/O.

The write signal of this input/output line I/O is transmitted to the complementary hiso line (complementary data line) selected by the Y-decoder circuit Y-DEC, and is coupled to this complementary bit line, so that the word line is in the selected state. is written to one memory cell that is

Signal YP is an operation control signal for the Y decoder system, and signal R
YP is an operation control signal for the main amplifier.

Since the signal YP controls the Y decoder Y-DEC, it is also generated during the write operation as described above.

The main amplifier activation signals MA and RM are activated by the signal RYP.
A is formed and the main amplifier is activated. The signal DS controls the data output timing of the main amplifier.

Signal RAS. ．． Based on the mutual input timing relationship between CAS and WE, test mode signals RN and RF and signals WN.
WF and signals CR and LF are respectively formed. Signal RN. RF and signals WN, WF are CBR (CAS before RAS refresh), WCBR (WE, C
AS Biower RAS) is controlled. Signal CR. LF controls the test circuit, for example, sets the seso1/reset bit of the address signal A+ during the above-mentioned WCBR. The address signal AFi taken into the test 1 related circuit is converted to FMiB which determines the test mode, and various test I signals are generated.

As a power supply circuit, a step-down voltage VCC of about 3.367 (2) for peripheral circuits is formed from a voltage VCCE of about 5V supplied from an external terminal, and word line selection 1/bell is determined from this step-down voltage. A boots I wrap voltage VCH of approximately 5.2v is created. Further, using this voltage CC, a substrate back bias voltage VBB of about -2V is formed. In addition, a step-down voltage VDL of about 3.3cm for the memory array (sense amplifier) from the externally supplied voltage VCCE as described above, and a step-down voltage V s "F" supplied especially during standby.
are formed independently.

From the above operational outline, a plurality of memory mats configured in a memory array include an X decoder that performs a word line selection operation. As shown in the block diagram of FIG. 5, this X decoder includes a mat selection signal MSiL/R formed by a mat selection circuit MSi L/R arranged in the center of the chip, and a pre-decoder formed by a BRIDGE decoder circuit. Decode outputs AXNL and XiB are fed through the final driver stage. A bonding pad 68 for address input, a control signal RAS, an address buffer, and a redundant circuit are arranged in a concentrated manner corresponding to each circuit arranged in the central part. This makes it possible to shorten the length of the wiring for transmitting address signals, thereby increasing speed. For example, in a conventional DRAM layout method in which bonding pads are placed on both short sides of a rectangular chip and address and control terminals are allocated accordingly, The signal transmission distance becomes longer. Zunawaji, there are both long and short distances from the bonding pad to the address buffer's manual terminals. Further, the distance from the address buffer to the address decoder also depends on the position of the address patch, and there are long and short distances.

In this layout method, the operating speed is limited to the one with the longest signal path due to the routing of the signal lines, and it is necessary to take a timing margin.
In a device designed to have a large storage capacity such as an M-bit device, the operating speed becomes slower in proportion to the size of the chip.

69 On the other hand, in the DRAM of this embodiment, as mentioned above, the bonding pads for address input and the pounding pad for control input are centrally arranged in the center of the chip, and This configuration adopts a configuration in which address buffers and control circuits are provided close to each other. In this configuration, since the signal lines extend approximately radially from the center of the chip, the signal propagation distance can be shortened to approximately 1/2 of the chip size. The wiring resistance increases in proportion to the wiring length, and the wiring capacitance increases in proportion to the wiring length. Therefore, in principle, the signal propagation delay time decreases in proportion to the square of the signal propagation distance. Therefore, as mentioned above, reducing the actual signal propagation distance to 1/2 of the chip size means that the signal propagation delay time can also be reduced to 1/4.

This embodiment adopts a configuration in which only the unit of memory mat selected by the Mbit selection signal MSiL/R is activated. Then, based on the mat bit selection signal MSiL/R, signals SHR, PCB, and a sense amplifier activation signal necessary for the address selection operation of the mat 70 are generated for each memory man. In this configuration, the signal S as described above is transmitted between a memory mat placed relatively close to the mat selection circuit placed in the center and a memory mat placed far away.
There is no need to take a timing margin for activation pulses of HR, PCB, sense amplifier, etc. In other words,
The memory mat to be activated starts operating from the time when the mat selection signal MSiL/R as described above is supplied,
Various signals for address selection are generated by the timing system optimized within the subsequent unit map.

In this configuration, the mat selection circuit disposed in the center of the chip has 8 mats compared to 32 mats in the above embodiment.
Since it is only necessary to supply the standard mat selection signal, the signal load can be reduced and the number of signal lines can be reduced. This reduces the delay of the selection signal transmitted to each mat.
can. The memory mats selected as described above operate at timings optimized for each mat, and there is no need to provide a timing margin between the mats, allowing high-speed memory access.

Also, as shown in the address assignment of the memory mats shown in Figure 4, two memory mats 1 and 1 in an axially symmetrical relationship are
, for example, MSO L and MSL L, MS2L and MS3L constitute one sub-block.

Four sub-blocks are provided for one memory array. In this configuration, only one of the two axially symmetrical memory mats is activated. Thereby, one control circuit can be used in common for two memory mats.

In a sub-block consisting of two memory mats as described above, memory arrays separated by a vertical center area are in an axially symmetrical relationship, such as MSOL, M
A configuration may be adopted in which the SLL, MS2L, and MS3L are used as one memory block and one control circuit is provided. In this case as well, four memory mats MSOL as described above are used.
．． ．． Among MSI72 L, MS2L and MS3L, only one is activated.
Since there are only two memory mats, one control circuit can be used in common as described above.

In this case, the entire memory array constitutes eight memory blocks.

The control circuit includes, for example, the above-mentioned complementary data line precharge operation, sense amplifier activation, shared sense amplifier control, X decoder activation, word driver activation, Y decoder activation, and common input. Output line I/
It is effective if at least one of various signals such as O selection and main amplifier selection and activation is formed, and even more effects can be obtained by forming all of them.

When a memory array is configured as a collection of unit mats as described above, it is easy to change the number of operating mats by changing the mat selection circuit, in other words, by changing the mat selection logic. Become. This results in
It is easy to develop new varieties, develop new products, etc.).

73 Furthermore, an X decoder and a Y decoder for selecting word lines and data lines may be provided adjacent to a unit memory mat, or may be common to a plurality of memory mats. In this embodiment, an X decoder is provided for each mat,
A Y decoder is provided for each memory array and is shared by eight memory mats to provide an efficient layout.

FIG. 14 shows a basic layout diagram of another embodiment of the Guinamisoku type RAM according to the present invention.

In this embodiment, as in FIG. 1, a Y decoder is provided in each of the four memory arrays divided by a cross-shaped area formed by the vertical center and the horizontal center of the chip. In this configuration, the Y decoder is placed at the center of each memory array, so the column selection line can be shortened. This makes it possible to speed up the selection operation of the Y system. Corresponding to such a configuration, the Y-system decoding signal is supplied 74 to each Y decoder circuit through the wiring channel provided in the vertical center portion. Note that an X decoder similar to the above is provided on the side adjacent to the vertical center portion.

In this configuration as well, the same speed-up as described above can be achieved by arranging input circuits such as a bonding pad and corresponding address buffers, memory mats or sub-blocks, and memory block selection circuits in the center of the chip. It is something that can be planned.

FIG. 15 shows a basic layout diagram of another embodiment of the Guinamisoku type RAM according to the present invention.

In this embodiment, an X decoder is provided at the center of each memory array in four memory arrays divided by a cross area formed from the vertical center and the horizontal center of the chip as in FIG. 1. In this configuration,
Since the length of the word line in the unit memory map 1 is shortened by half, the load on the word line is reduced and the word line selection operation can be speeded up. Corresponding to this configuration, the X-system BRI-decoded signal is supplied to the X-decoder circuit corresponding to each memory mat through 75 wiring channels provided in the X-decoder section. Note that a Y decoder similar to the above is provided on the side adjacent to the horizontal center portion.

In this configuration as well, the same speedup as described above can be achieved by arranging bonding pads, corresponding input circuits such as address path sofas, memory mats or sub-blocks, and memory block selection circuits in the center of the chip. It is something that can be done.

FIG. 16 shows a basic layout diagram of still another embodiment of the Guinamisoku type RAM according to the present invention.

In this embodiment, as in FIG. 1, four memory arrays are divided by a cross area formed by the vertical and horizontal centers of the chip. X in the direction. l! : A Y decoder is provided. With this configuration, the word line length and column selection line length can be halved, and the load correspondingly becomes lighter, so that word line selection and column selection operations can be performed at high speed. In this configuration, among each memory array, the
Out of the four memory areas divided by the
Sense amplifier activation, assured sense amplifier control,
A control circuit can be provided for forming various signals such as activation of the X decoder, activation of the word driver, activation of the Y decoder, selection of the common input/output line I/O, and selection and activation of the main amplifier.

In this configuration as well, the same speedup as described above can be achieved by arranging bonding pads, corresponding input circuits such as address buffers, memory mats or sub-blocks, and memory block selection circuits in the center of the chip. It is something. In addition, the above figures 14 to 16
In the figure, the configuration may be such that the X and Y decoders are interchanged.

Even when adopting any of the above basic layout variations, the memory array is divided into four parts by a cross area consisting of the vertical and horizontal centers of the chip, and peripheral circuits and bonding pads are placed there. It constitutes.

In particular, in a configuration in which address pads, address buffers, pre-decoders that receive them, and most-stage drivers that supply pre-decoded signals to each decoder are placed in the center, the signal propagation path for memory access is radial. Towards the four corners of the bottom left and right, move in the shortest distance to Katsuho 5.
They extend at equal distances. This makes it possible to speed up the operation as described above.

Also, as an internal power source, a step-down voltage generation circuit for forming the operating voltage VDL of the memory array (sense amplifier) and the operating voltage VCC of the peripheral circuits is also arranged at the center of the chip. With this configuration, the length of the power supply wiring can also be shortened as shown in the embodiment shown in FIG.

As a result, the power source impedance can be kept low, making it possible to increase the speed of the circuit and reduce noise.

FIG. 17 shows the basic structure of another embodiment of the memory mat and a layout diagram of another embodiment of the memory block constructed by combining the basic structure.

FIG. 17(A) shows a basic configuration diagram of a memory mat. In the figure, S is a sense amplifier, M is a memory cell array, W is a word 1/' line drive circuit (including an X decoder), and C is a control circuit.

In the example shown in FIG. 2A, the sense amplifier S is provided on the left side of the memory cell array M. Therefore, the memory mat of this embodiment does not employ the shared sense amplifier method as in the previous embodiments.

In FIG. 2B, a sub-block is formed by symmetrically arranging memory cell arrays M with the sense amplifier S of the memory mat at the center. in this case,
A shared sense amplifier method may be used in which the sense amplifier S is selectively used for the left and right memory cell arrays M, or a shared sense amplifier method may be used in which two 79 sense amplifiers S are arranged adjacently corresponding to each memory cell array M. You can also use it as A plurality of such sub-blocks are combined to form the above-mentioned memory array. In this configuration, if the left and right memory cell arrays are selectively operated, the control circuit C can be shared.

In the same figure (C), for the sub-block of (B) above, Mn
J? One memory block is formed by combining the memory mats shown in FIG. 3A so that the word line drive circuit W, memory cell array M, and sense amplifier S are vertically symmetrically arranged so that the ffl1 circuit C is in the center. It consists of In this case, each of the pair of vertically symmetrical sub-blocks may be configured into two memory arrays. By assigning addresses so that one of the four divided memory cell arrays M (unit memory mat) is selected, the sense amplifier S is connected to the left and right channels through the switch MOSFET. The shared sense amplifier system 80 may be used in common in that it is selectively coupled to the memory cell array, and the word line drive circuit W may also be made common to the upper and lower memory cell arrays. With this configuration, the control circuit can be shared by four memory mats. However, in this case, since no Y-system decoder circuit exists in the mat or block, the Y-system signal circuit is excluded.

FIG. 18 shows the basic structure of another embodiment of the memory mat and a layout diagram of another embodiment of the memory block constructed by combining the basic structure.

FIG. 18(A) shows a basic configuration diagram of another embodiment of the memory mat. In the example shown in the figure, a control circuit C is provided adjacent to a sense amplifier S. Furthermore, word line drive circuits W are provided on both upper and lower sides of the memory cell array M. This word line drive circuit W selects/unselects one word line from both ends for high-speed word line selection operation. Instead of this configuration, memory cell array M
The word line may be divided into upper and lower parts at the midpoint, and each of the divided word lines may be selected by the two word line driving circuits 81W. In this case, by shortening the length of the word line, high-speed word line selection operation becomes possible. Alternatively, every other word line may be selected by two upper and lower word line drive circuits. With this configuration, the pinch of the selected word line can be doubled compared to the word line drive circuit divided into upper and lower parts. That is, by dividing the word line drive circuit, which requires a relatively large occupied area, into upper and lower parts, word lines arranged at a smaller pitch can be driven. The memory mat of this embodiment does not employ the shared sense amplifier method as described above.

In FIG. 3B, a sub-block is formed by symmetrically distributing a memory cell array M and a sense amplifier S provided therein with the control circuit C of the memory mat at the center. In this case, the control circuit C is shared. A shared sense amplifier system may be adopted in which the control circuits C are arranged vertically and the sense amplifier S is also shared and used selectively for both memory cell arrays.

The same figure (C) shows the word line drive circuit W of the sub-block.
One memory block is constructed by arranging a memory cell array M, a sense amplifier, and a control circuit C vertically symmetrically with respect to the portion . In this case, of the memory cell array M (unit memory mat) which is divided into four parts, the sub-blocks may be constructed into two memory arrays.

By assigning addresses so that one memory cell array M is selected from among the memory blocks,
The control circuit can be shared by a memory block consisting of four memory mats. However, in this case, since no Y-system decoder circuit exists in the mat or block, the Y-system signal circuit is excluded.

FIG. 19 shows the basic configuration of another embodiment of the memory mat and a layout 1 of another embodiment of the memory block constructed by combining the basic configurations (FIG. 83).

FIG. IIQ (A) shows a basic configuration diagram of another embodiment of the memory mat. In the example shown in the figure, sense amplifiers S are provided on the left and right sides of a memory cell array M. Therefore, complementary data of memory cell array M! vl (bit line) is split in the middle. As a result, the number of memory cells on the complementary data line connected to the input of the sense amplifier can be reduced by half, reducing the parasitic capacitance, lightening the load, and increasing the amount of signals read from the memory cells. The speed of the sense amplifier S can be increased. Instead of this configuration, sense amplifiers S may be connected to both ends of the complementary data line to amplify the read signal from both ends of the complementary data line. With this configuration, the current of the sense amplifier is distributed, so high-speed operation and low noise are possible.

Alternatively, sense amplifiers may be arranged on the left and right sides for every other pair of complementary data lines. In this case, the pinch of the sense amplifier can be alleviated. In other words, by distributing the sense amplifiers as described above, one sense amplifier can be formed in an area corresponding to two pairs of complementary data lines, making it possible to further increase the density of the complementary data lines. . A word line drive circuit W is provided below the memory cell array M, and a control circuit C is arranged to surround it.

In FIG. 3B, two memory mats are arranged symmetrically so that the sense amplifier S on the - side of the memory mats is in the center to form a sub-block. In this case, the control circuit C is shared. When the word lines of the left and right memory cell arrays are only selected alternatively, a modified shared sense amplifier method is adopted in which the central sense amplifier S is shared and used selectively for both memory cell arrays. Good too. In this case, if the sense amplifier provided in the center is used for auxiliary amplification, the input/output of the sense amplifier is directly connected to one end of the complementary data line of one memory cell array, and the switch MOSFET is connected to the other end. There is no problem even if the input and output of the sense amplifier are coupled through 85.

FIG. 2C shows a memory block consisting of four memory mats arranged vertically symmetrically around the control circuit C portion of the sub-block. In this case, of the memory cell array M (unit memory mat) which is divided into four parts, the sub-blocks may be constructed into two memory arrays.

One memory cell array M of the above memory block
By allocating addresses so that 1 is selected, the control circuit 1 can be shared by a memory block consisting of four memory mats. However, in this case, since no Y-system decoder circuit exists in the mat or block, the Y-system signal circuit is excluded.

FIG. 20 shows the basic structure of another embodiment of the memory mat and a layout diagram of another embodiment of the memory block "C" constructed by combining the basic structure.

FIG. 20(A) shows a basic configuration diagram of another embodiment of the memory mat. In the example shown in the figure, sense amplifiers S are provided on the left and right sides of a memory cell array M,
Word line drive circuits W are provided above and below the memory cell array M. Therefore, the complementary data line (
bibit line) is split in the middle. As a result, the number of memory cells on the complementary data line connected to the input of the sense amplifier can be reduced by half, reducing the parasitic capacitance, lightening the load, and increasing the amount of signals read from the memory cells. The speed of the sense amplifier S can be increased. Instead of this configuration, sense amplifiers S may be connected to both ends of the complementary data line to amplify the read signal from both ends of the complementary data line. With this configuration, the current of the sense amplifier is distributed, so high-speed operation and low noise are possible.

Furthermore, similarly to the above, sense amplifiers may be arranged alternately at both ends of the complementary data line in order to achieve high integration.

The word line drive circuit W selects/unselects one word line from both ends for high-speed word line selection operation. Instead of this configuration, the word line of the memory cell array M may be divided into upper and lower parts at the midpoint, and each of the divided word lines may be selected by the two word line drive circuits W. In this case, by shortening the length of the word line, high-speed word line selection operation becomes possible.

Further, word line driving circuits may be arranged alternately at both ends of the word lines in the same manner as described above, thereby achieving high density arrangement of the word lines.

A control circuit C is arranged to surround the word line drive circuit W on the lower side of the memory cell array M and the sense amplifier on the left side.

In FIG. 3B, two memory mats are arranged symmetrically with the control circuit C on the left side of the memory mat in the center to form a sub-block. In this case, the control circuit C is shared. If the word lines of the left and right memory cell arrays are only selected alternatively, a modified shared sense amplifier method 2 may be adopted in which the central sense amplifier S is shared and used selectively for both memory cell arrays. good. In this case, if the sense amplifier provided in the center is used for auxiliary amplification, the input/output of the sense amplifier is directly connected to one end of the complementary theta line of one memory cell array, and the switch MOSFET is connected to the other end. There is no problem even if the input and output of the sense amplifier are connected via the .

FIG. 2C shows a memory block consisting of four memory mats arranged symmetrically with respect to the lower control circuit C of the sub-block.

In this case, of the memory cell array M (unit memory mat) which is divided into four parts, the sub-blocks may be constructed into two memory arrays. By assigning addresses so that one memory cell array M is selected from among the memory blocks, the control circuit can be shared by the memory blocks consisting of four memory mats. However, in this case, since no Y-system decoder circuit exists in the mat or block, the Y-system signal 89 circuit is excluded.

FIG. 21 shows the basic configuration of another embodiment of the sub-block and a layout diagram of another embodiment of the memory block constructed by combining the basic configuration.

FIG. 21(A) shows memory cell arrays M arranged on the left and right sides with a sense amplifier S in the center, word line drive circuits W arranged below each memory cell array M, and word line drive circuits arranged below the memory cell arrays M. The control circuit C shown in FIG. 17 (
Sub-blocks as shown in B) are arranged symmetrically or in parallel, and a Y decoder commonly used for the plurality of memory cell arrays M is provided on the right side.

In FIG. 18(B), a common X decoder is provided in the memory block shown in FIG. 18(C). In this embodiment, W is simply a word line driving circuit and has no decoding function. In this embodiment, if only one word line is selected from among the four memory cell arrays M, the word line driving circuit may be shared by the two memory cell arrays.

Even when adopting the configurations of memory mats, sub-blocks, and memory processors as shown in FIGS. 17 to 21,
A configuration can be adopted in which only a unit memory mat is activated by an appropriate mat selection signal. In this way, based on the mat selection signal, the signal SHRXPC and the sense amplifier activation signal necessary for the address selection operation of the mat are generated for each memory mat. In this configuration, the above-mentioned signals SHR,
There is no need to provide a timing margin for the activation signals of the PC and sense amplifier.

In other words, the memory mat to be activated starts operating from the moment the mat selection signal as described above is supplied, and from then on, the timing system optimized within the unit mat activates the unit mat. Various signals are generated. Therefore, the mat selection circuit placed in the center of the chip only needs to supply a selection signal for activating one of the plurality of mats such as 9 1 described above, so that the signal load can be reduced.
The number of signals transmitted to each mat and their delay can be reduced. The memory mats selected in the same manner as described above operate at timings optimized for each mat, and there is no need to take a timing margin between the mats, thereby enabling high-speed memory access.

FIG. 22 shows the S used in the DRAM according to the present invention.
A top view of an OJ (Small Outline J-Bend Pathocage) lead frame is shown.

In the same figure, the DRA indicated by the dashed-double line is the installed DRA.
It is an M chip. A pair of leads formed to extend horizontally from the top, bottom, right and left of the center of the chip are used as leads for supplying the ground potential VSS and the power supply voltage VCCB.

Since the leads are arranged across the center of the chip in this way, they are bonded at a plurality of 92 locations with the power supply baths VSS and VCCE shown in FIG. 3. In addition, as a power terminal,
As mentioned above, both VCCB and VSS consist of two terminals,
Since the ground potential VSS and power supply voltage VCCB are applied to the chip at multiple locations using wiring materials with low resistance values such as lead frames, the power supply impedance of the circuits to which these potentials are applied can be kept small. . Thereby, noise generated in the power supply line due to the operating current of the circuit can be suppressed to a small level.

Further, in the figure, the connecting ends of the leads for transmitting and receiving signals extend from the top and bottom of the chip toward the center. This allows efficient connection to the address signal terminals and control terminals gathered in the center of the chip.

FIGS. 23(A) to 23(C) show examples of connection between the lead frame and the semiconductor chip as described above.

In the example in the same figure (A>), the lead frame 22 and the chisop 23
are connected to the surfaces 93 by adhesive A 26 and adhesive B 27 with a film 24 interposed therebetween. And the terminal of the lead frame is a gold wire 25
It is connected to the boarding pad of Chiseop 23 by.

In the example shown in FIG. 2B, the lead frame 22 is made of adhesive C
29 is connected to the insulator 8 formed on the surface of the chisop 23. Then, the terminal of the lead frame is connected to the real estate terminal 7 of the chip 23 by a gold wire 25.

In the example shown in FIG. 2C, the lead frame 22 is covered with mold resin 21 except for the lead surface where bonding connections are made, and is connected to the surface of the chisop 23 with adhesive D30. be. Then, the terminal of the lead frame is connected to the chimp 2 by the gold wire 25.
Connected to No. 3 Hondingpaso.

When such a lead frame is used, the lead frame can be placed on the surface of the semiconductor chip so as to form part of the wiring. As a result, even if the bonding pad is placed in the center of the chip as shown in FIG. 3, connection to the lead 94 can be made without any problem.

FIG. 24(A) shows a DRAM with a LOG (lead-on-chip) structure using the lead frame as described above.
The external view is shown, and the same figure (B) is the internal perspective view.

In the figure, 31 is a molding resin, 32 is an external terminal (lead frame), and 33 is a chip. The chisop 33 is bonded to the lower side of the lead via an insulating film 34 using the adhesive as described above. Inside, the tip of each lead is connected to a chisop 33 by a gold wire 35.
It is connected to the bonding node 38 of the. 36 is a bus hard, and the voltage VCCE and ■SS as mentioned above are applied.
Used for supply leads. 37 is a hanging lead;
9 is Indy Sox.

FIG. 25(A) shows a pin layout diagram of external terminals. Although not particularly limited, the 16M bin dynamic RAM can be accommodated in a 28 bin PC cage. 95(B) shows a side view as seen from the side where the pins are arranged, and FIG. 95(C) shows a sectional view as seen from the side where the pins are not arranged.

FIG. 26 shows pin layout diagrams of a ×1-bit configuration and a ×4-bit configuration when using a ZIP (zigzag inline package) type dynamic RAM according to the present invention. has been done. In the same figure, NC indicates a vacant pin, which is a DRAM with ×4 bit configuration.
The locations marked with arrows indicate the same signal pins as those in the ×1 bit configuration.

FIG. 27 shows pin layout diagrams of a ×1-bit configuration and a ×4-bit configuration in the Guinamisoku type RAM according to the present invention when using an SOJ type PCB. In the same figure, NC indicates a vacant pin,
The location marked with an arrow in a DRAM with a ×4 bit configuration is ×1
This means that the signal bin is the same as the bit configuration.

When using a lead frame with the LOG structure as described above, the Hasper I No. 1
is used as the ground potential VSS of the circuit, and on the 96 DRAM chip side, pads for supplying the ground potential are provided corresponding to the units of operation, and the ground potential is supplied from a plurality of locations. In this configuration, since the ground potential is directly applied to the circuit of each operation unit from the low-impedance lead frame, a large level margin on the ground potential side can be secured. Also, connect the other Hasbar lead that extends the vertical direction of the chip to the external voltage VCCE.
Power supply pads are provided corresponding to circuits used and required, such as data output buffers and internal step-down voltage generation circuits VCC and VDL. This makes it possible to lower power source impedance and reduce power source noise due to internal operations. In particular, the output buffer that forms the output signal is adapted to carry a large drive current to drive a relatively large load. Therefore, by providing dedicated power supplies VCCE and VSS for the output buffer and arranging them in close proximity, noise generation can be reduced.
It is possible to prevent the generated noise from adversely affecting other circuits.

97 Hereinafter, the dynamometer type RAM according to the present invention will be explained in detail with reference to a specific circuit diagram and its operation waveform diagram.

In the specific circuit diagrams below, signals with the letter B added at the end, such as the signal WKB, are HA signals in which LOWERHEL is set to the active level.

FIG. 28 shows a partial circuit diagram of an embodiment of the RAS system control circuit. Moreover, in FIG. 70, R
A timing diagram of one embodiment of each AS system signal is shown.

RAS (row address strobe) signal is CMOS
It is supplied to the input circuit of the in-harter configuration.

The CMOS inherter circuit for this input buffer is not particularly limited, but may include a P-channel MOSFET and an N-channel MOS whose absolute value of threshold voltage is about 0.5V.
It is composed of FET. By setting the conductance ratios to be equal, a rosin threshold voltage of approximately 1.6V is obtained. The power supply voltage VCC for the peripheral circuits in the DRAM of this embodiment is:
The threshold voltage of the Kushino 98 mentioned above is 3.3■, which is about twice the 1.6■
is set to This means that the other control signals CAS, WE
The same applies to each input buffer that receives address signals and write data.

The logic threshold voltage as above is “r”′
It corresponds to rL level signals.

In addition, in a DRAM designed to increase the capacity like this embodiment, the elements are miniaturized. Therefore, in a circuit such as a MOSFET that constitutes an internal inverter circuit where variation in element constants is a concern, a flat portion of the channel length Lg-L threshold voltage vth characteristic is used. Therefore, the channel length Lg becomes relatively long, and the threshold voltage v. th becomes relatively high, and when operating at a relatively low voltage VCC as described above, the operating speed becomes slow.

Therefore, MOSFETs constituting the first-stage inverter circuit of the input buffer, which is required to be high-speed as described above, are not particularly limited, but the MOSFETs constituting the inverter circuit used in the internal circuit can reduce the channel impurity concentration. The threshold voltage is set to have a low threshold voltage as described above, such as by making the threshold voltage smaller than the threshold voltage. MOSFET with such low threshold voltage
is similarly used in the first stage circuit for inputting other control signals and address signals. In addition, as above, from the viewpoint of operating speed and level reduction, MOSFETs with low threshold voltages are also available.
are the output stage MOSFET of the output huffer in the CMOS configuration like this example, the output stage MOSFET of the output huffer in the RAM, the first stage MOSFET of the main amplifier, and the blue associative MOSFET of the human output line I/O.
SFET, Complementary Deke Line Show 1- MOSFET
ET, also used in diode-type MOSFETs used in charge pump circuits. Note that the method for obtaining the above-mentioned low threshold voltage can include various embodiments other than the method in which the impurity concentration of the channel is changed by the above-mentioned ion implantation technique.

When the signal RAS is set to low level, the DRAM is activated, and when it is set to high level, the DRAM is activated.
is made inactive.

1 0 0 RA through the inverter circuit as the above input buffer
The S signal is a NAND (
N.A. ND) Through the gate circuit, the human power and the output are taken into a latch circuit consisting of two cross-connected NAND gate circuits.

The signal WKB is set to a high level when the level of the substrate bias voltage VBB is low. Therefore, the output of the inverter circuit becomes low level and the output of the NAND gate circuit is fixed at high level, thereby prohibiting reception of the signal RAS. In other words, if the substrate bank high ass voltage is not sufficient, the operation of the internal circuit cannot be guaranteed, so R
AM access is prohibited. Further, the output of the NAND gate circuit is positively fed back to the gate of a P-channel MOSFET provided at its input section. Between the P-channel MOSFET and the operating voltage VCC, there is a P-channel MOSFET that acts as a resistance element by constantly applying a ground potential to its gate.
T are provided in series. As a result, once the signal RAS is taken into the gate circuit, the logic threshold voltage is shifted to the low level side to invert the signal.

When the level of substrate back bias voltage VBB is at a desired deep level, signal WKB becomes low level. As a result, the NAND gate circuit opens gate 1-, so that the RAS signal passed through the human buffer is taken into the latch circuit. Signal RE is a rewrite guarantee signal, and the internal RAS signal is held by the high level of this signal.

The signal R1 passed through the latch circuit is used to control individual buffers such as the X address buffer, map bit selection, CAS, WE, and Din. That is, each circuit is activated by the high level of the signal R1. R.I.B.
This is the inverted signal.

A delay signal RI is generated from the signal R1 by impark circuits arranged in series (hereinafter simply referred to as inheritor circuit array).
A signal R2 is formed by D, the inhark circuit, and the Frisopfrosov circuit. The signals R1 and RID determine the control of the X address 1 0 2 buffer, that is, the set-up/hold of the X address signal as will be described later.

Signal R2 is used to control word line set 1/reset. Furthermore, to compensate for the write level, the word line reset timing is delayed.

From the signal R2, a signal FtJS is formed using a Frisopflosob circuit, an inharter circuit, and a NAND gate circuit. This signal FUS is used to set the initial value of a redundant circuit as described later. This signal FUS is made into one pulse with a constant pulse width from the signal R2, and current is caused to flow through the fuse that stores the defective address for a certain period of time, and the level is held in the latch circuit depending on whether the fuse is disconnected or not. . This initializes the defective address storage circuit. By using such a one-shot pulse, a steady DC current does not flow through a fuse that is not blown, thereby reducing power consumption.

A signal R3 is generated from the signal R2 using an inheritor circuit array and a Frisopflo 103 subcircuit. This signal R3
is used to control the complementary data line system (sense amplifier SA, precharge PC1 shared sense SHR, etc., and redundant decoder precharge RDP. Take enough delay from the word line reset (R2) and reset the complementary data line reset bit. To do this, the reset timing is delayed.

A signal RDP is formed from the signals R1 and R3, the Nantgate circuit, and the inverter circuit.

FIG. 29 shows another partial circuit diagram of one embodiment of the RAS system control circuit.

Signal WM is used to monitor the set 1 timing of the word line and control the operation of the complementary data line (sense amplifier). Therefore, the signal WM is XE,XREO
It is formed from B to XRE3B. XE. ．． XRBO
B to XRE3B are formed by a redundant circuit as described later, and when the address is not a relief address, the signal
When REOB to XRE3B are at high level, the signal WM is formed by the signal XE, and when it is a relief address, the signal 104 is at low level and one of XREOB to XRE3B is set to low level, so that the signal WM is set to low level. It is formed.

A signal po is formed from the signal WM and the signal R3. Signals PN1 and PPI are formed by delaying the signal PO, and determine the amplification timing of the first stage of the sense amplifier. Further, the signals PNI and PPI are used to form relatively large delay signals formed by a Frisopflosop circuit by a multiplexer circuit, or signals PN2 and PP2 having a relatively small delay time formed by the multiplexer and three inverter circuits. used for. These signals PN2 and PP2 are the second signal of the sense amplifier.
This determines the amplification timing of each step. The multiplexer is switched during the test mode and is used to vary the peak current of the sense amplifier.

FIG. 30 shows another partial circuit diagram of one embodiment of the RAS system control/roll circuit.

The signal PN2 is delayed by a delay circuit consisting of a Frisopfromp circuit and a series of inverter circuits to form a signal RG. This signal RG determines the timing for turning on the Y (column) switch. When a sufficient amount of signal is obtained on the complementary data line by the amplification operation of the sense amplifier, the Y (column) switch is opened to output the signal to the input/output line I/O.

Signal RG is delayed by a Frisopflosop circuit to form signal RE. This signal RG is a rewrite guarantee signal and is used when the RAS times out. Of course, in a dynamic memory cell in which a memory cell is selected by a row-related address selection operation, the information charge in the information storage capacitor is temporarily destroyed by the selection operation, but there is no resetting in which the amplified output of the sense amplifier is received as is. The information holding charge is recovered by 1. Therefore, even if the RAS signal is set to high level before the write is performed as described above, the signal RE
The operation time for the above-mentioned rewrite operation is secured by the high level of rewrite operation.

106 FIG. 31 shows a circuit diagram of an embodiment of a unit circuit constituting the X address buffer.

Address signal AI supplied from external terminal and signal R1
The NAND gate circuit receiving the signal constitutes a large buffer. That is, when the signal R1 becomes high level, the NAND gate circuit opens the gate and takes in the address signal supplied from the external terminal AI. Game 1 like this
Even in a functional input buffer, its logic threshold voltage is set to about 1.6 mm as described above, and its operating voltage VCC is set to about 2 mm as described above.
It is set to 3.3■ times. As a result, the operating voltage VC
Since the Rosinx threshold voltage is set at the midpoint of C, the operating voltage can be used efficiently and the input level margin can be increased.

The three-state output circuit whose output high impedance state is controlled by the signal XLB is an input gate circuit that takes in the address signal AI.

A three-state output circuit similar to the above, which is controlled by the signal RLB, is an input gate circuit that takes in 1 0 7 refresh address signals API. The A1 and ARES signals selectively taken in through the above two input gate circuits are
It is transmitted to the input of the CMOS interconnection circuit. This commercial
An address latch circuit is constructed by providing a feedback loop of a similar three-state output circuit controlled by the signal XRLB between the input and output of the OS.

From the output of this address latch circuit, an internal address signal BXI is sent through an inharter circuit or a NAND gate circuit.
, BXIB are formed.

Control signals XRLB, XLB, and RLB for controlling the triangular output circuit are formed from the signal RID and the signal CI.

Here, ■ indicates a numerical value from O to 11. In other words, the circuits in the figure are unit circuits corresponding to address signals AO to All, respectively.

Unit circuits corresponding to address signals AO to All are:
Each output is supplied to an X-system redundant circuit and used as an address signal for comparison with the stored defective address. Furthermore, the following address buffer circuit for forming memory mat selection signals and the like is also provided for the address signals A8, 1 0 8 to All.

FIG. 32 shows a circuit diagram of an embodiment of an address path sofa circuit corresponding to address signals A9 and AIO.

The address input circuit that receives the address signal supplied from the external terminal, the refresh address signal input circuit, and the latch circuit provided in common to each are the same as those shown in FIG. 31, so their explanation will be omitted. From the address signal taken into the above-mentioned Lasochi circuit, the mat selection signal MSOB or M is generated by an invert circuit or a NAND gate circuit.
S3B is formed. In addition, row system signals R3, RDI
Control signals XRLB, XLB and RLB for the input gates constituting the latch circuit are formed from C1 and C1.

FIG. 33 shows a circuit diagram of an embodiment of the address buffer circuit corresponding to the address signal All.

1 0 9 The address input circuit that receives the address signal supplied from the external terminal, the refresh address signal input circuit, and the latch circuit provided in common to each are the same as those shown in FIG. 31, so their explanation will be omitted. From the address signal taken into the latch circuit, the signal BXI I LB. ．． BX
I IRB is formed. These signals BXI ILB
．． ．． The BXI IRB selects the left and right sides of the operating mat. These signals BXIILB and BXIIRB are outputted via a CMOS transmission gate circuit consisting of an N-channel MOSFET and a P-channel MOSFF,T.

The CMOS transmission game 1 circuit is switch-controlled by a signal RC. A reset MOSFET receiving the signal RC is provided on the output side of the transmission gate circuit.

The above signals BXI ILB, BXI IRB and signal MSI
B, the Mabit selection signal MSLIL. ．． MSIR is formed. Here, since ■ does not indicate O to 3 as shown in the figure, eight types of mat 1 1 0 selection signals as described above are formed. In addition, row signals R3 and RD
Control signals XRLB, XLB and RLB for the input gates constituting the latch circuit are formed from I and C1.

Note that in the normal mode, the signal RC is set to low level. Therefore, the left and right mat selection signals BXI ILB. corresponding to the address signals ALL and ARl1 are transmitted through the transmission gate circuit. ．． BXIIRB is formed. On the other hand, in the test mode, the signal RC is set to a high level. Therefore, the transmission gate circuit is turned off, and the reset bit MOSFET outputs the signals BXI ILB,
BXI IRB both go to low level. This means that
This means that the left and right mats MSIL and MSI R are simultaneously in the selected state. As a result, the number of cycles in the test mode is 2084 cycles, which is half of the 4096 cycles in the normal mode in which the signal RC is set to low level. Thus, in this embodiment, refresh cycle switching is enabled.

FIG. 34 shows a circuit diagram of an embodiment of an address buffer circuit corresponding to address signal 88.

An address input circuit that receives an address signal supplied from an external terminal, an input circuit for a refresh address signal, and a latch circuit provided in common to each of the above-mentioned 31st
Since it is similar to the figure, its explanation will be omitted. From the address signal taken into the latch circuit, the signal SLB. ．． An SRB is formed. These signals SLB and SRB are for generating left and right selection signals SL and SR within the selected mat. Furthermore, control signals XRLBXXLB and RLB for the input gates constituting the latch circuit are formed from the row-related signals R3, RD1, and C1 similar to those described above.

The above address signals AO to All are transmitted to the gates 112 of a large number of MOSFETs, such as the address comparison circuit in the bridge decoder and the redundant circuit, as described above. This causes the address buffer to drive a large capacitive load, which causes the internal address signal to change relatively slowly. Therefore, by providing an address buffer circuit for mat selection for address signals A8 to All as described above, the mat selection that needs to be performed prior to word line selection can be performed at high speed, and the access time can be increased. It is.

FIG. 35 shows a circuit diagram of a part of the embodiment of the row predecoder.

Signals AXNLD and AXNLU are for controlling the X decoder, and address signals BXIO and BXIOB
This is for selecting the upper and lower Masots.

Signals AXIH and AXIHB control the Y-system redundant decoder [corresponding to relief of sense amplifier and Y (column) selection line defects]. Here, I8 to Il are shown. The signals AXIH and AXIHB are formed by setting a latch circuit consisting of a pair of NAND gate circuits 1 1 3 to set bit/reset using the signals BXIB and BXI.

A X 1 0 H also controls the upper and lower mats of the Y decoder, and controls the signal AYNL and signal YIB. Signal AX
IH is Y Decoder City II? Latch one cycle period of RAS for wholesale.

FIG. 36 shows a circuit diagram of an embodiment of the X-system redundant circuit. FIG. 72 shows a corresponding operation timing diagram.

The basic idea of the redundant circuit in this embodiment is as follows.

Four redundant word lines are provided in the left and right memory areas of each memory map bit.

One conventional DRAM defect relief method is to provide redundant decoders in one-to-one correspondence with each redundant word line.

This results in an enormous number of redundant decoders in a device having a large storage capacity consisting of a large number of memory mats as in this embodiment.

In another conventional DRAM defect relief method, fuses are provided corresponding to the redundant decoder defect and the address 1 1 4 signals XO to X7. If this continues, redundant word lines will be selected at the same time in 24-16 blocks that can be specified by address signals X8 to Xll, which will reduce the efficiency of the redundant word lines and increase the probability that the redundant word lines will have defects. As a result, defect relief efficiency decreases.

Therefore, fuses are added corresponding to the address signals x8 to Xll so that only one of the 16 blocks selects a redundant word line. That is, switching to a redundant word line is performed only in a block (mabit) in which a defective word line exists. This operation is
Signal XRODB-XR provided commonly to each block
3DB (BXIO) or XROUB-XR3UB (
BXIOB) and mat selection signals (MSiL/R, SL
/ S R ).

In this way, if the X address direction is divided into 16 by 4 bits of address x8 to Xll, each block has 4 redundant word lines, so the number of redundant decoders is 4 at maximum.
X 1 6 = 6 4 pieces can be installed.

115 This increases the number of redundant decoders from a minimum of 4 to a maximum of 6.
It can be set to any number up to 4 (preferably a multiple of 4). Here, the relief efficiency is the maximum value among 4 to 64 (
In this example, 12 pieces were selected so as to have the highest yield. The relief efficiency of this defect relief method can be equal to that of other conventional defect relief methods in which the number of redundant word lines is 12 (the number of redundant decoders is also 12). That is, the number of redundant word lines can be reduced to 1/3 with the same number of redundant decoders.

In FIG. 36, the fuse FUSE is formed from a polysilicon layer, although it is not particularly limited, and is selectively cut by laser beam irradiation in response to a defective address to be stored.

The fuse FUSE is a signal FUS of 1 pulse.
Initialization is performed through the MOSFET which is turned on by the inverter circuit, and when the fuse FUSE is cut off, the MOSFET is turned on by the output high level of the inverter circuit and is fixed to the ground potential. If the fuse FUSE is not disconnected 1 16 , the input of the inverter circuit is thereby fixed at a high level.

If the fuse FUSE on the upper side of the figure is not blown by the signal RDP, it means that the defect relief will not be performed.
At this time, the signal XRDJB becomes low level. here,
J indicates a number from 0 to 11, corresponding to the number of redundant decoders, which is 12. When the defect is repaired, the fuse FUSE is cut, and the signal RDP causes the signal XRDJB to become high level.

In the figure, the upper fuse is for enable,
The lower fuse is for storing defective addresses. The enable fuse is blown when the defect is resolved. Signal XR
When the address programmed in the redundant decoder J matches the input address XO to Xll, the DJ becomes high-level. In the figure, the signal X N D 0 . 1~XN
The MOSFET to which D2J is input as a source is an N-channel MOSFET. The signal XRDJB becomes high level when it is activated, and when it is active, it is sent to the redundant decoder J among the input address signals XO-Xll.
7. If there is an address that differs by even one bit from the programmed address, that is, if the defect relief address is not selected, it will cause an outrage. The signal XRDBJ remains at a high level when all of the above bits match. Signal XRDJ
becomes low level during precharge, and remains low level when no relief address is selected.

When not being rescued, the enable fuse is not cut. As a result, the signal XRDJB is fixed at a low level, and the signal XRDJ is fixed at a low level. Signal A
, B6 and B7 are used for testing redundant word lines. In the test mode, the signal STB is set to low level. As a result, the redundant decoder of J=0.3, 6.9 is set to the rescue state, and the combination of X6 and X7 (0.0) (10
) (0 1) (1 1), the address fuses are equivalently blown and made to correspond to the four redundant word lines of XRO-XR3, respectively, so that the redundant word lines can be selected. At this time, the address comparison circuit for I=8 to 11 selects a redundant word line with all 16 floats as described above by setting the match state regardless of the input address. . By doing this, 1 out of 16 blocks
This makes it possible to avoid the block from being unable to test redundant word lines.

In this embodiment, the redundant word lines are not necessarily all used, and more often than not, all of them are not used. Taking this into consideration, in this embodiment, the redundant decoder is commonly used to select redundant word lines provided in a plurality of memory mats, as described above.

In this embodiment, two address comparison circuits are provided. The reason for this is as follows. In the conventional redundant decoder, only a match is determined using one atrus comparison circuit, and when a match is found, the normal word line selection pass is stopped. This method requires one-stage logic to inhibit the normal word line selection pass and a timing margin to prevent racing. Therefore, in this example,
1 19 Two address comparison circuits are provided, one for match detection and one for mismatch detection. When a match is detected, a redundant word line is selected, and when a mismatch is detected, a normal word line is selected. As a result, it is possible to reduce the number of logic stages by one stage, eliminate the timing relationship that causes racing as in the prior art, and speed up the word line selection operation.

37 and 38 show circuit diagrams of decoder circuits that select word lines and redundant word lines.

In the circuit of FIG. 37, signal XE is a word line selection timing signal in normal mode. When the enable fuse is cut, all of the signals XRDOB to XRDIIB become low level when a word line other than the defective word line is accessed.

Accordingly, none of the redundant decoders of J = 0 to 11 has cut off the enable fuse FUSE.In other words, in non-relief mode, the signal BXO or BXOB becomes low level, and the signal XE becomes high level. . From this and the signal BXO120BXl2, the bridecode signal XKDB. XKU
B (divided into upper and lower parts by BXIO and BXIOB) is created. Signals WCKDB and WCKUB are corresponding word line clear (far end of word line) signals.

In the circuit of FIG. 38, the signal X R E L B is
This is a signal for selecting four redundant word lines created by dividing 12 redundant decoders into three each. This signal and signal B
XIO, BXIOB generate a redundant word line selection signal XRLDBXRLUB and redundant word line clear signals WCRI, DB. WCRLUB is created.

FIG. 39 shows a circuit diagram of an embodiment of a timing generation circuit for activating a sense amplifier.

The N-channel MOSF is turned on in response to a signal formed by the mat selection signal MSI and the timing signal PNI for performing the first stage amplification operation from the signal R3.
The ground potential is applied by ET, and N is turned on in response to a signal formed by the timing signal P121 and N2 that performs the second stage amplification operation.
A ground potential is provided by the channel MOSFET.

A P-channel MOSFET that is turned on in response to a signal formed by the Mabit selection signal MSI and the timing signal PPI that performs the first stage amplification operation from the signal R3.
The P-channel MOSFET is supplied with an operating voltage VDL and turns on in response to a signal formed by a timing signal P P 2 that performs the second stage amplification operation.
The operating voltage VDL is given by

Although not shown, the ground potential or operating voltage VDL
N-channel MOSFET, P-channel MOSFET that gives
The ground potential (N-channel side) and operating voltage (
The ground potential or operating voltage VDL applied to the sense amplifier is applied to the P-channel side), and the N-channel MOSFET or P-channel MOSFET is connected to the sense amplifier.
When T is turned off, the power supply line is shared to prevent it from being accidentally turned on due to power supply noise.

122 The N-channel MOSFET and P-channel MOSFET that are turned on in the first stage are made to have relatively small conductances, thereby supplying a relatively small current. The N-channel MOSFET and P-channel MOSFET that are turned on in the second stage are made to have a relatively large conductance, thereby supplying a relatively large current.

The above mat selection signal MSI (I is OL/OR~3 L/
3R) activates the sense amplifiers of four memory mats among the 32 Mbits.

FIGS. 40 and 41 show circuit diagrams of one embodiment of a control circuit provided in a memory mat.

The circuit shown in FIG. 40 forms the following signals from the mat selection signal MSIL/R, signals SL and SR, and row-related timing signals R1 and R2. Here, 32
This will be explained as a closed signal within one mat in the Mabit. Therefore, the suffix I is omitted for signals other than MS I L/R.

From the above 1 2 3 signals, the X decoder precharge signal XDPL/
An R,X decoder extraction signal XDGLB/RB and a complementary data line precharge signal PCB are formed. Further, the word line drive signal WPHL/R and the signal MSH are subjected to signal level conversion by a latch-type NOR gate circuit whose operating voltage is the bootstrap voltage VCH. These level-converted high-level signals are outputted via an inverter circuit whose operating voltage is the Boo 1 strump voltage VCH. Therefore, in the memory mat of this embodiment, the selected word line changes from the low level, unselected level, to the boosted selected level. This makes it possible to speed up the word line selection operation compared to the conventional configuration in which a word line selection signal is used and a bootstrap voltage is obtained by combining it with a delayed signal.

The circuit shown in FIG. 41 includes a decoder and a drive circuit that form word lines WL and redundant word lines RWL selected from the pre-decode signal, the X-decoder precharge signal XDPL/R, and the X-decoder extraction signal XDGLB/RB. It is.

Since the word line drive circuit uses the boosted voltage VCH as described above for its operating voltage, the selected word line is changed from the low level ground potential VSS to the boosted voltage VC as described above.
It is designed to rise linearly up to H.

The shared line drive signal SHL/R formed by the selection signal MS} {and SL and SR is also boosted voltage VC similar to the above.
H is the operating voltage. Therefore, between the sense amplifier and the selected complementary data line, a switch MOS
Signals can be exchanged without level loss due to the threshold voltage of the FET.

FIG. 42 shows a circuit diagram of one embodiment of the memory cell array.

The memory cell is composed of a capacitor for storing information and a MOSFET for address selection. MO for address selection
The drain of the SFET is connected to one of a pair of parallel complementary data lines.

1 2 5 The gate of the address selection MOSFET is connected to the word line. The plate voltage is supplied to the other end (plate) of the information storage capacitor.

The figure shows a pair of complementary data lines and four word lines WLO.
to WL3 and redundant word lines RWLO to RWL3
is shown illustratively.

Since the cathode pulling caused by O'Harasop between the word line and the pair of complementary data lines appears on the complementary data lines in common mode, it can be canceled out by the differential sense amplifier described later. Note that the complementary data lines are crossed at regular intervals and replaced. By doing so, it becomes possible to eliminate the influence of coupling between complementary data lines.

A switch MOSFET for clearing the word line is provided on the far end side of the word line, and the clear signal WCLO
~WCL3 and RWCLO~RWCL3 are supplied.

Switch MOSF receiving shared line drive signal SHL
The complementary data line is coupled to the input/output node of the sense amplifier 1 2 6 via ET. The sense amplifier is a P-channel MOSFET and an N-channel MOSFET, one of which is exemplified as a representative.
It is constructed by cross-connecting the input and output of a CMOS impedance circuit consisting of FETs.

It should be noted that in this embodiment, the sense amplifier may refer to a unit circuit as described above, or may refer to a memory unit in which the source of such a unit circuit is shared.

The common source PP of the P-channel MOSFET in the sense amplifier has the P-channel MOSFET as described above.
The operating voltage VDL is supplied through a power switch consisting of an OSFET, and an N-channel MOSFE
To the common source PH of T, add N channel M as described above.
Ground potential V via a power switch consisting of an OSFET
The amplification operation of the sense amplifier is started by supplying SS.

In this embodiment, a column switch MOS connects four pairs of complementary data lines to input/output lines 100, IOOB, 1 2 7 to 103, and IO3B.
A FET is provided. Therefore, the four pairs of collars J and switches MOSFETOKI have a common Y.
(Column) Selection line YS is connected. In response to this,
The redundant data lines are also composed of four pairs, and although not shown, four pairs are provided and selection signals YSRO to YSR3 are provided.

FIG. 43 shows a circuit diagram of an embodiment of the reflex valve 1 to the counter concave path.

In the refresh mode, this CBR counter circuit performs a counting operation using the signal RFDB corresponding to the RAS signal as a cross clock, and forms a refresh address signal ARJ. Signal CAI is a carry human input signal, and signal CAJ is a carry-out signal. Twelve such unit circuits are connected in series, and address signals AO to Δ11 are
corresponding to Fressocie address signal ARO or AR
Generate l1. In this embodiment, a 4096-bit scan paste is used. An action is taken.

Figure 44 shows 1 2 of the CAS system control/roll circuit.
8 A partial circuit diagram of one embodiment is shown. Further, FIG. 75 shows a timing diagram of one embodiment of the CAS system address selection operation.

The CAS (column address strobe) signal is
It is supplied to an input circuit consisting of an S inverter circuit. CMOS inverter for this input buffer. The circuit is made to have a rosin resistor voltage of about 1.6 µ as before. Its operating voltage CC is 3.3V, which is about twice the zinc threshold voltage 1.6V mentioned above.
It is set to correspond to TTL level signals. When the signal CAS is set to a low level, the operation of the Y-system circuit is started.

CA through the inverter circuit as the above input buffer
For the S signal, a circuit similar to that for the RAS signal is used.

However, the signal corresponding to the signal WKB of the RAS circuit is omitted, and the power supply voltage VCC of the circuit is constantly supplied.

Signals C1 and C2 are formed from the signal CAS.

The signal C1 is a Nifl counter, signal 1 2 as described later.
No. 9 DOEXW3B. ．． The signal C2B is used to control the signal W5B and the signal CE, the signal C2B is used to control the signal WYP, and the signal C2 is used to control the signals W3B, YL, DL, etc. Signal ACIB is formed from signal CE, which in turn forms signals YP and RYP.

Signal ACIB is a signal that controls the operation of the main amplifier and Y decoder system, and is generated by signal CB. This signal ACIB internally generates one shobit pulse (RYP).
, YP) and read it.

Signal YP is an operation control signal for the Y decoder system, and is also generated during a write operation. Signal RYP is an operation control signal for the main amplifier.

FIG. 45 shows a circuit diagram of an embodiment of a unit circuit constituting a Y address buffer.

Address signal AI supplied from external terminal and signal R1
The receiving NANDKATE circuit constitutes an input buffer. That is, when the signal R1 becomes high level, the NAND gate circuit opens the gate and takes in the address signal supplied from the external terminal AI into the internal circuit 130. This signal R1 is for reducing the current in the stand-up state. That is, in the standby state where the signal R1 is set to low level, the address terminal A
The input circuit is made unresponsive to the I signal. Even in an input buffer with such a gate function, its logic threshold voltage is set to approximately 1.6■ as mentioned above, and its operating voltage CC is approximately twice that as described above. It is set to 3.3■. As a result, the threshold voltage is set at the midpoint of the operating voltage CC, so the operating voltage can be used efficiently and the input level margin can be increased.

The three-state output circuit whose output high impedance state is controlled by the signal YL is the input game 1 circuit which takes in the address signal AI. A three-state output circuit similar to the above, which is controlled by the address signal capture signal YL, constitutes a positive feedback loop between the input and output of the CMOS inverter circuit that receives the address signal through the input circuit 1. Performs address latch operation. Internal address signals BYI and BYIB are formed from the output of this address 1 3 1 latch circuit through an inharter circuit.

A signal ACjB is formed from the internal address signals BYI, BYIB and the signal CB.

A circuit for generating signal YL is shown in FIG. 54, and the Y address buffer has four operation modes depending on the generation mode of signal YL. The first mode is a normal mode in which the signal YL changes in response to the CAS signal to enable static column operation. The second mode is a nibble mode, in which a signal YL is formed by the first CAS signal to hold the fetched address signal. The third mode is the CBR mode, and in this case, when the CAS signal is set to υ and later set to low level, a signal YL is generated and an address signal is taken in. The fourth mode is WCBR, in which an address signal valid between signal R1 and signal YLO is taken in as a signal specifying the test mode.

1 3 2 FIGS. 46 to 49 show circuit diagrams of one embodiment of the y redundancy circuit and the bridecode circuit, in which data lines, column selection lines (hereinafter sometimes simply referred to as Ys lines)
It is used to repair defective sense amplifiers and sense amplifiers. The basic concept of the Y-system redundant circuit in this embodiment is the
It is similar to a redundant circuit.

That is, the block consists of 16 blocks divided by X8 to Xll. Among these, the defective data line of the I block is relieved by the redundant data line. Therefore, the address comparison circuit uses the address signals AX8H and AX8HB.
-AXI L AXIIB is input.

Since there are four pairs of input/output lines I/O, one column selection line selects four bare complementary data lines. Therefore, relief is performed in units of four pairs of complementary data lines. Therefore, since addresses YO and Y1 are degenerated, address YO
A fuse corresponding to Y1 is not provided. Also, ×4
Address YI that is degenerated in Viso 1 configuration and nibble mode
A fuse corresponding to O Yl1 3 3 1 is also not provided. Therefore, 1
Four redundant YS lines are output simultaneously within the block.

In the actual layout, one block consists of four blocks in the word line direction.
It is divided (YIO, Yll) and distributed within the chip in the longitudinal direction. This will be clear from the block address allocation shown in FIG. 4 above.

In the 64-bit simultaneous test mode as described later, addresses ¥2 and y3 are also degenerated. However, address Y
If the fuses corresponding to Y2 and Y3 are also eliminated, 16 redundant ys lines will be issued at the same time within the l block. That is, 16x4 (number of I/O) - 64 pairs of redundant data lines are to be relieved at the same time, and a large number of redundant data lines must be prepared, resulting in poor efficiency. Therefore, for addresses Y2 and Y3, only the YS line corresponding to the complementary data line with the actual complementary data line defect is switched to the redundant YS line during the 64-bit simultaneous test, and the rest are normal YS lines.
Select lines (multi-selection of 4YS lines by degenerating addresses Y2 and Y3). This 1 3 4 eliminates the need to prepare four times the number of redundant data lines even though the 64-bit test mode of the YS multi-selection method is provided.

Since the YS line spans multiple blocks as described above, if a YS line failure occurs, data line failure will occur in multiple blocks belonging to the same YS line. If redundant decoders are allocated to each block in order to relieve this problem, the number of redundant decoders becomes large and the relief efficiency decreases. To prevent this, block address x8~X
Two fuses are provided in each of the lower fuses F'USE, and when the lower fuse F'USE is blown, comparison of the corresponding X addresses is no longer performed. In this way, for example, if the lower fuses FUSE of x8, X9, and x11 are cut, eight blocks belonging to one ys line are degenerated,
Relief can be performed with one redundant decoder, improving efficiency. Similarly, for a defective sense amplifier,
If only the lower fuse FUSE 8 is cut off, the left and right data lines of the sense amplifier can be relieved by one redundant decoder.

In FIG. 46, the upper circuit corresponds to enable,
The lower circuit corresponds to addresses Y4 to Y9. In FIG. 47, the upper circuit corresponds to addresses Y2 and Y3, and the lower circuit corresponds to addresses x8 to Xll.

The fuse FUSE is a pulse signal F t
M.J.S. is turned on by J.S. O S F E
Initialization is performed through T, and fuse F U
When SE is disconnected, the MOSFET is turned on due to the high level output of the inharter circuit, and is fixed to the ground potential. If the fuse FUSB is not disconnected, the input of the inverter circuit is thereby fixed at a high level.

At the time of completion, if the address programmed in the redundant decoder and the input address match, the signal RDJ becomes high level, and if they do not match, the signal R DJ becomes low level. At the time of non-relief, the signal RDJ is fixed to the low level.

During 64-bit simultaneous test, signal YMB1 3
6 is at a low level, and signals YFIJ and YFIJB output the states of the fuses corresponding to addresses Y2 and Y3. Addresses Y2 and Y3 are not compared (degenerated)
. When redundant data line test 1, addresses X8 to Xl
l is degenerate. The state of addresses Y2 and Y3 is (0, O
)(L O)(0.1)(i l), J
=0. 3, 6. 9 redundant decoders are in a relief state and correspond to four redundant YS lines. This configuration is similar to the X redundancy circuit described above.

In FIG. 48, signals RDO to RD2, R D3 to R
Redundant YS line selection signals YRDOB to YRD3B correspond to D5, RD6 to RD8, and RD9 to RDI1, respectively.
is formed.

Signal YRD, when set to high level, inhibits normal selection of the YS line during redundancy selection. However, during the 64-bit simultaneous test, the signal YRD is fixed at a low level due to the low level of the signal YMB, and the normal YS line is also selected at the same time.

Signals RAOJB-RA3JB are at address Y21 3
7 Monitor the status of the fuse FUSE corresponding to Y3. In the normal mode, it is fixed at a high level by the high level of the signal YMB. 64 Biso 1 - During simultaneous testing, when a repair address is selected, the state of the fuses at addresses Y2 and Y3 is decoded by the high level of signal RDJ, and one of the outputs is set to low level (defective address Y2, (corresponds to the Glidecort signal of Y3)
.

Signals RY2OB-RY23B are the signals RY2OB-RY23B when the addresses excluding Y2 and Y3 among the 12 redundant decoders of J=0-l1 coincide, and only Y2 and Y3 are different addresses or are repaired. J=O so that two or more of them can be set to low level]
1's OR (OR) logic is adopted. That is, for example, four YSWAs are degenerated by areas Y2 and Y3.
If two of them have been saved, those two will be redundant YS.
line, and the remaining two lines are used to distribute to the normal YS line.

Also, for redundant YS line chenok, paraphrase 1 3
8, in order to select the redundant YS line in the test mode and perform a write/read test on the memory cell provided there, the redundant YS line is selected for any address specification of address signals X8 to Xll. YS line (Y
SRO to YSR3) must be selected. Further, two bits of address signals Y2 and Y3 are used to designate the redundant YS line. That is, }word Bl (1=
2.3) and A (corresponding to the redundant decoder of L=8.9.10.11) are supplied with STB (redundancy test signal) or VCC. As a result, without cutting the fuse at the defective address, it is equivalent to blowing the fuse using the address signal in the above test mode, and it is possible to perform the selection operation of the redundant YS line specified by the above address. Become what you can. This circuit is basically the same as the X-system redundant circuit, so a detailed explanation of each signal will be omitted.

To explain the defect relief method related to this invention from another perspective,
It is as follows.

FIG. 91(A) shows 1 3 due to the multiple selection of the Y system.
9 shows a conceptual diagram for explaining an example of defect teaching in the multi-bit simultaneous test mode from another perspective.

In the figure, the horizontal axis shows the X address, and the vertical axis shows the Y address. When configuring a RAM having a storage capacity of about 16 Mbits as in this embodiment, X consists of 4096 addresses and Y also consists of 4096 addresses. Conventional defect, 1'! In the i-processed technology, a redundant circuit is switched to a redundant circuit for one defective address of X and Y. Therefore, for example, if a defect exists in one address of the Y system, access to the bit line to which 4096 memory cells provided therein are connected is prohibited, and the redundant bit line to which 4096 memory cells are connected in the same way is disabled. The configuration is such that the switch can be switched to a line. This increases the scale of the redundant circuit, so
In the embodiment shown in the figure, the X and Y addresses are divided into 16 memory blocks by using the upper 2 bits of the X-system address and the upper 2 bits of the Y-system address, and the data is stored in each block. 1 40 that allows you to specify a line.

Further, in the case of a multi-bibit simultaneous test as described above, or when the upper two bits of the Y-system address are degenerated to form a x4-bit configuration, the Y-system is multiple selected. therefore,
If even one of them is defective, the conventional defect relief method is to switch all of them to redundant circuits. Then, it becomes necessary to switch the bit lines with no defects to redundant bit lines only for the Y-system multiple selection test or the x4 biso 1 configuration. Therefore, when selecting four addresses of the Y system at the same time, as shown by the dotted line in the figure,
Only blocks in which defective bit lines and YS selection lines exist are switched to redundant bit lines RBL, and bit lines corresponding to the remaining three simultaneously selected addresses are shifted to select normal bit lines NBL. Note that with the above block configuration, the bit lines of other memory blocks divided by the X address are unselected. With this configuration, only those with defects are switched to redundant focus lines, so the number of redundant 1 4 1 bit lines to be prepared can be significantly reduced.

FIG. 91(B) shows a conceptual diagram illustrating another embodiment of repairing defects in the biso hm in the normal mode.

In the example of the same ID (B), among the focus lines belonging to the same Y address, among the four blocks divided by the X address, only the defective block is switched to the redundant bit line RBL, and the other blocks are Normal bit line NBL is selected.

By repairing defects in units of blocks, the number of redundant bit lines or YS selection lines to be prepared can be reduced.

FIG. 91(C) shows a conceptual diagram for explaining another embodiment in which word line defects are counted in the normal mode.

In the example of the same figure (C), among the word lines belonging to the same X address, of the four blocks divided by the Y address, only the defective pro-nok is connected to the redundant word line R.
WL, and normal word line NWL is selected for other blocks.

1 4 2 By performing defect relief on a block-by-block basis, the number of redundant word lines to be prepared can be reduced. However, in a DRAM like this embodiment where the X address signal is multiplexed and input before the Y address signal,
The above Y address signal cannot be used as is. Therefore, the same defect relief method as described above can be realized by internally programming an address, which can be called a block address, which is equivalent to the Y address, by using the same fuse means as described above.

FIG. 49 shows a circuit diagram of an embodiment of a Y-system partial decoder circuit including a circuit for forming a main amplifier selection signal.

Signal ASK (ASO to AS3) selects one group of main amplifiers (selects one pair of four bare I/O lines).

The signal AY20U/D-AY23U/D is
Predecode addresses Y2 and Y3.

It is divided into upper and lower mats by Atres X10.

During a 64-bit simultaneous test, the pre-decoding of Y2 and Y3 is ignored in the signal YMB, and the signals RY2 0B to RY2 3B shown in FIG. 41438 are output with their original logic.

Signals YOUB-Y3UB and YODB-Y3DB are pre-decoded signals that pre-decode addresses Y4 and Y5 and are output in accordance with signal YP, and are used as data line selection timing. Signal CB defines the reset bit timing.

Signal YOUB-Y3UB. ．． YODB-Y3DB becomes high level when the signal YRD is high level, and prohibits selection of the normal YS line.

64-bit simultaneous test 1 Sometimes addresses Y2 and Y3
If the AYS line degenerated in is not relieved, the signal AY20U/
D ~ AY23U/D 4 or high level 4 Y
The S line is selected, but if it is relieved, the corresponding AY20
1 to 4 of U/I) to AY23U/D are not output, and 1 to 4 redundant YS lines are selected instead, and the redundant Y
The S line and the normal YS line are selected at the same time. AY60U/
D to AY83U/D are Buri decode signals of addresses Y6 to Y9. Signal YR O U/DB-YR 3
U1 4 4 /DB selects the redundant YS line. This is the signal You
/DB~Y 3 Corresponds to U/DB.

FIG. 50 shows a unit circuit of a Y decoder and a redundant YS line selection circuit.

The above-mentioned BRI decoded signal is decoded by a three-man NAND gate circuit. This decode output and the Y selection timing signal YKUB (K=0 to 3) are supplied to the NOR gate circuits, and column selection signals YSO to YS3 are formed from the respective NOR gate circuits. A redundant column selection signal YSRO-YSR3 is formed from the signal formed by the redundant decoder circuit.

FIG. 51 shows a circuit diagram of one embodiment of the nibble count circuit.

In normal mode, address signal NAK corresponding to internal address signal BY■ is output. In the nibble mode, the internal address signal BYI of the first cycle is first counted and amplified. When memory access is performed in the ×4 pin configuration, the signal NA1 4 5 K is fixed at a high level (VCC) by a master slice shown in the form of a switch.

FIG. 52 shows a circuit diagram of an embodiment of a control circuit that forms Y-system control signals.

Signal MA is a main amplifier operation control signal.

The signal DS is a signal that controls the data output of the main amplifier. Signal MA is generated in conjunction with the generation of signal ACIB (RYP). The signal R1 determines the reset bit timing of the main amplifier.

Signal DS is generated by signal MA. Signals C1 and R1
is what performs the reset bit.

In other words, the data output of the main amplifier is controlled by RAS.
This is a reset bit for both high-level health and CAS.

The signal WR is a read/write 1 discrimination signal.

The first stage is controlled by signal R1 to reduce current consumption in stand-high state.

Signal DOE controls the data output buffer and is generated in read mode. In the case of the ×1 bit configuration, the signal is generated by ANDing the signal C1 and WR. ×
In the case of the 4 Hiso 1 configuration, the 1 4 6 output enable signal is generated by ANDing the output enable signals OE-Cl and WR. tOEH (signal OE from signal WE
In order to prevent hold time, the control signal OE is latched by the WE system signal DL.

FIG. 53 shows a circuit diagram of an embodiment of the operation mode determination circuit.

Signals RN, RF and signals -qWN, wF are in normal operation,
Controls CBR operation and WCBR operation.

Signals RN and RF control signals CE and YE, and signals CRB and LFB control test circuits, specifically, control the address set bit/reset during WCBR.

FIG. 54 shows a part of an embodiment of the Y-system control circuit.

The signal YL causes the Y address buffer shown in FIG. 45 to latch an address.

As mentioned above, the timing of occurrence etc. differs depending on each operation mode. An example of the operating waveform is shown in FIG. 77.

1 4 7 CAS corresponding to high speed page mode (normal mode)
The Y address is latched in synchronization with . For nibble mode, the Y address is searched during the RAS cycle. The reason for this is that in nibble mode, the address signal is generated with a nibble counter. In static column mode, the first Y address at the time of writing is searched.

When in counter test I-mode during CBR, Y address is latched. In the WCBR mode, the Y address is searched during the RAS cycle period.

The signal DL controls the setup/holding of data in the data buffer. In high-speed page mode or nibble mode, CAS is reset to low level and WE is reset to low level, and reset is performed by CAS high level. In static column mode, CA. It is set by the low level of S or the low level of WE, and is reset to 1 when the write operation is completed.

Signal OLB outputs the written data to DO1 4
8 This is a signal that is latched to prevent this from occurring. This corresponds to read-modify-write operations. In the static column mode, it corresponds to tWol+ (output hold time from signal WE).

FIG. 55 and FIG. 56 show some embodiments of the WE system control circuit.

In FIG. 55, a WE (write enable) signal is supplied to an input circuit consisting of a CMOS inverter circuit. The CMOS inverter circuit for this input buffer is designed to have a logic threshold voltage of about 1.6 .ANG., as described above.

Power supply voltage V for peripheral circuits in the DRAM of this embodiment
CC is set to 3.3 .quadrature., which is approximately twice the above-mentioned zinc threshold voltage of 1.6 V, and corresponds to a TTL level signal.

Signals W1 and W2 control the Lie 1 operation. In the standby state, W1 and W2 are set to low level. During operation, it changes in synchronization with changes in signal WE. Signal W1 performs RAS/WE logic control (WN/WF), and signal W2 performs CA1 4 9 S/WE logic control. tAsc (column address seso 1・up time) f! The light se bit is delayed for security reasons. Signal W3B is a one-shobit pulse formed by signal W2, from which signal W4B is formed.

In FIG. 56, the signal WYP controls the write signal until it is transmitted from the data input buffer to the input/output line I/O, and the signal WYPB controls the process until the write signal is transmitted from the data input buffer to the input/output line I/O.
Control is performed from the time the signal is transmitted to the bit line.

The signal IOU precharges the input/output lines ■/○ after the write operation. This is to accommodate the next read cycle. Signal WL is used to latch address and data in the state/knock column mode. 76th
The figure shows a timing diagram of an example of a write operation.

FIG. 57 shows a circuit diagram of one embodiment of the data manual buffer.

The input circuit is composed of a NAND gate circuit and has the same resistance voltage as the other input circuits. In the x1 bit configuration, this gate control signal A is substantially invalidated by one of the four input buffers serving as the signal Rl and the remaining three input buffers being supplied with the circuit ground potential ■SS. When used as a ×4 bit configuration, the signal A corresponds to all four input buffers and becomes the signal R1. The reason why a Nant gate circuit is used in the human power section of the human cover that is put into operation and the signal R1 is supplied thereto is to reduce current consumption in the standby state, as described above. Setup/hold of write data is controlled by signal DL.

Signal MKI is used to control the write mask mode in the ×4 bit configuration. Signal D when signal RAS is set
Write 1/non-write control is performed by QI-DQ4 data. Signal DI (0 to 3) is further divided into nibble address NAI units.

FIG. 58 shows a circuit diagram of an embodiment of the main amplifier control circuit, and FIG. 59 shows a circuit diagram of an embodiment of the main amplifier control circuit.

Signal RMA is a timing signal that controls the operation of the main amplifier. Signal WMA controls signal transmission (write operation) from the data buffer to the human output line I/O.

Signals ILAi3 to ILCi3 are for pulling up the input/output line I/O, and signal IOIJ is for pulling up the input/output line I/O.
This is a signal that shorts /O.

In normal mode, one main amplifier is operated by signal HMA. In one test mode, the signal TB
As a result, 16 main amplifiers become operational all at once.1
A batch comparison operation of 6 binoto is performed. Furthermore, in another test mode, a 64-bit batch comparison operation is performed by multiple-selecting YS&1 using signals TE and YMB. FIG. 89(A) shows a circuit diagram illustrating the principle of a multi-bit test using a 4-bit parallel test using a pair of main amplifiers as an example.

That is, according to the example in the same figure, the 16 main amplifiers are divided into 8 pairs, and each of the 215 2 I/O line pairs corresponding to each pair is connected to a 4-bit string multi-selected by 4 YS lines. Total of 8 with two I/01 pairs of
A total of 64 bits of multi-test is performed each time the read data consisting of bits is sent in parallel to the eight pairs of main amplifiers.

Taking FIG. 89(A) as an example, one input of a pair of main amplifiers MA has complementary bit lines BL1 and BLBI or BL4 and BLB4 corresponding to a read signal consisting of 4 bits connected to a Y switch MOSFET. They are commonly connected via input/output lines I/O and I/OB, respectively. A reference voltage (R) is supplied to the other input of the pair of main amplifiers MA. This reference voltage VR is set to an intermediate level between the high level read signal and the signal when there is a 1-bit mismatch, as shown in the waveform diagram of FIG. In other words, as shown in the same figure, the complementary bit BLI
When BLB1 and BLB1 are logic "0" as shown in the figure (BLI is low level "I4" and BLBI is high level "H"), the input/output line I/O (7)153 level is pulled up. Since the Y-switch MOSFET (M2) and the MOSFET (M3) of the sense amplifier are connected to the MOSFET (Ml), the level is lowered as shown by the dotted line in the figure according to the conductance ratio thereof. Therefore, the reference voltage VR is applied to the Y-sunsonar M for the pull-up MOSFET (M1).
Two OSFETs (M2), sense amplifier MOSF
Two ETs (M3) are connected in series to provide an intermediate level between the high level and the low level when 1 bit mismatches. Therefore, in the embodiment shown in FIG. 89, if all bits are written with logic "1" and even one bit is logic "0",
Out of the pair of main amplifiers, the output signal of the main amplifier corresponding to the input/output line I/O changes from high level to low level, and becomes the same low level as the output of the main amplifier corresponding to the input/output line /OB, and an error is detected. ,,Contrary to the above case, if you write logic "'0'" to all 4 hits and read it, if all bits logic "0" is read, the input/output % will be reversed to the above case. ? il/OB side is high 1
5 4 level, and if there is a mismatch in even one bit as described above, the level of the input/output line ■/○B will be lowered as above, so the main amplifier of the pair of main amplifiers corresponding to the input/output line I/OB The output signal changes from high level to low level and becomes the same low level as the output of the main amplifier corresponding to the input/output line I/O, and an error is detected. Note that when all the bits are defeated, the outputs of the pair of main amplifiers are divided into a high level and a low level.

In such a multi-bit test, for example, the 89th
In the state shown in the figure, the input/output line ■/OB has 3
By supplying the low level output of two sense amplifiers, the output level tends to be relatively low. As a result, the bit line BLBI with the defective read is
There is a possibility that the low level of the input/output I/OB will be transmitted and the sense amplifier will be reversed and normal data will be written to the defective read bin I/line.

As a countermeasure for this, in the multi-pit Tetos mode, the conductance of the pull-ahead MOSFET (Ml) 1 5 5 is increased. Specifically, in the multi-bint test mode, a pull-up MOSFET is provided that is turned on by the signal. This makes it possible to reduce the drop in the low level of the input/output lines ■/○ and ■/OB, thereby preventing the above-mentioned erroneous writing.

Alternatively, in the case of a multi-bit test as described above, the switch MO is turned on by the control signal.
The SFET switches the operating voltage from VCC to VCCE or a boosted voltage VCH, such as about 5V.

With this configuration, the level of the input/output line can be made relatively high by the amount corresponding to the voltage switching, so that erroneous writing due to the low level as described above can be prevented.

Alternatively, the threshold voltage of the pull-up MOSFET may be set to a low threshold voltage, and the pull-up level (bias level) of the input/output line may be increased accordingly. That is,
When operating at a low voltage VCC of about 3.3cm as in this embodiment, if the threshold voltage of the pull-up MOSFET is large, the pull-up level described above will be low, causing an error. This is because the low level margin for preventing writing becomes smaller.

In the embodiment shown in FIG. 54, the two I/O line pairs connected to the two main amplifiers mentioned above are connected true to true and bar to bar to connect the two main amplifiers. The amplifier is shared by the above-mentioned configuration. This prevents the number of main amplifiers from doubling. A total of 8 bits, 4 bits for each I/O 11i'i pair, are compared using the 8 pairs of main amplifiers mentioned above, achieving a 64-bit simultaneous test.

By adopting the multi-bit test described above, approximately 1
RA with a large storage capacity like 6M bint. This makes it possible to shorten the test time for M.

In the write mode, a signal from the data input buffer is supplied to the input/output line /0 by signal WMA, and data is also written to the main amplifier by signal RMA. This corresponds to the nibble mode 157 and high speed page mode.

FIG. 60 shows a circuit diagram of an embodiment of the main amplifier data output control circuit.

Main amplifier output group MAiO to MA+3, MAiOB
-MAi3B is selected by the main amplifier selection address ASO-AS3, and the output group selected by the nibble address NAi is sent to the outputs WAMOiB, MO+ by the signal DS. In this way, one main amplifier out of 16 main amplifiers is selected.

When outputting in units of ×4 bits, nibble address NAi
is fixed at a high level.

{When the S DS is in high-speed page mode, RAS/CAS
It is reset bit by reset. In nibble mode, the first
It is sufficient to input data into four main amplifiers in a cycle and output the acquired data from the main amplifiers from the second cycle, so the signal DS remains at a high level.

In the test mode in which the signal TE is generated, the data of the four main amplifiers are combined into one output signal MOi through a comparison circuit (NAND gate 158).

FIG. 61 shows a circuit diagram of an embodiment of the main amplifier output control circuit.

Signal OLB controls data output to the data output buffer. Perform data rasoching using read/modify/write 1. The signal TE activates all 16 main amplifiers in the test mode, and the output signal MOO~
Data is output to MO3 or MOOB to MO3B. This comparison output method includes two values and three values.

In the binary system, high level/low level is output to the output DO/DOB when all logic is "1'°" or logic "0", and low level/high level is output when there is a failure.In ternary system, all logic u1' is output. When , a high level/0u level is output to the output D O/D O B, a low level/high level is output when all logic is "0", and a low level/low level is output when there is a failure.

When the signal TW is high level, the above binary output 1 5
9 system, and when the signal TW is low level, the above three-value output system is used.

FIG. 62 shows a circuit diagram of an embodiment of the data output path sofa.

The data output buffer is provided with a level conversion circuit at its input section. As mentioned above, the internal circuit operates with the stepped down voltage VCC. Therefore, the read data transmitted through the main amplifier is formed by the operating voltage CC. The data passed through the NAND gate circuit by the signal DOE is connected to the externally supplied power supply voltage VCCB.
The level is converted into a latch-type NOR gate circuit operated by. By providing such a level conversion circuit and driving the push-pull output section consisting of an N-channel MOSFET, the output level on the high-level side can be increased, and the amplitude of the drive signal is increased, making it possible to increase the speed.

The output section is provided with a MOSFET that controls the gate of the output section MOSFET and a resistance element.

The threshold voltage of the MOSFET, which is provided between the gate 160 and the source of the output MOSFET on the side of the power supply voltage VCCE and whose gate is constantly supplied with the ground potential ■SS, is defined as the threshold voltage of the output MOSFET. lower than the value voltage. As a result, when the output terminal DOUT becomes a negative potential, the MOSFET with the above-mentioned low threshold voltage
T turns on and shorts the gate and source of the output MOSFET. This prevents the output MOSFET from being turned on due to the above-mentioned negative voltage.

Further, an output circuit that operates at a relatively early timing through the output gate circuit is separately provided, thereby making the rising and falling timings of the output signal earlier. Then, it is changed to a specified level by an output circuit that receives data passed through a level conversion circuit. By adopting such a configuration, the output level can be changed linearly over a relatively long time while increasing the speed, and the noise generated in the power supply line and ground line due to changes in the output signal level can be reduced. The level can be reduced.

1 6 1 FIGS. 63 and 64 show circuit diagrams of one embodiment of the test circuit.

Test functions are set according to the timing of WCBR. This WCBR outputs a test signal corresponding to the fetched address. Above WCBR
As a result, a signal LFB is formed and an external address signal can be taken in.

Signal FR resets everything to logic "0" at power-on.

The reset bit of the test function is signal F by the RAS only refresh and CBR refresh cycles.
This is done by setting R to high level during the precharge period of the RAS signal and resetting all addresses to logic "0".

The following test modes are prepared according to the signal FMNB formed from a combination of 4 bits of API to AFL corresponding to address signals YO to Y3. (11x16 vivid test, (2) x 6
4-bit test (3) Switch internal voltage VCC to external voltage VCCB. (4) Internal voltage ■1 6 2 CC monitor, (5) Internal voltage VDL monitor (61 2
0 4 8 refresher (8 1 9 2 bit operation)
, (7) redundant area test, and (8) high-speed test I.

FIG. 65 shows a circuit diagram of an embodiment of a control circuit for specifying an operating mode.

By selecting the high level/mouth level and high impedance for the bonding path FPO and FPI, from the combination, depending on the x1 bis 1 configuration and x 4 bis l configuration specified by the aluminum master slice. The following modes are set for each.

In the ×1 focus configuration, when both the bathode FPO and F P 1 are at high impedance, the signals sC and NB both become low level, and the high-speed page mode is designated. When PASODO FI) O is set to low level and PASODO FPI is set to high impedance, signal SC becomes high level and static column mode is designated. pasodo FP
When O is set to high impedance and the path mode F P1 is set to a high level (VCCB'), the signal NB becomes high level and the nibble mode 163 is designated.

In the ×4 bit 1 configuration, when both the pabits FPO and FPI are at high impedance, the signals SC and NB are both low level and the high speed page mode is designated. When the path FPO is set to low level and the path FPI is set to high impedance, the signal SC becomes high level and the static column mode is designated. Pasodo FPO is high-impedance, Pabit FPI is high-reher (VC
CE), the signal WB is formed, the high-speed page mode becomes the write mask mode, the pad FPO is set to the low level, and the pad FPI is set to the high level (VCCB), the signal WB is formed in the same way as above, and the write mask is set in the static column. This is the mode. In the write mask mode, by keeping the WE signal at a low level when the RAS signal falls, it is possible to set the bin to be written from the output terminal I/O.

Figure 66 shows other systems? A circuit diagram of one embodiment of a ffn circuit is shown.

164 Signal WKB monitors the level of substrate bias voltage VBB. When the substrate bias voltage VBB becomes approximately 0.7V or less, the signal W K r3 becomes low level. When the substrate bias voltage VBB is shallow, the threshold voltage of the MOSFET becomes low, so a relatively large through current flows due to circuit operation, and latch amplifier is likely to occur. Therefore, access to the RAM is prohibited by the high level of the signal WKB. be.

Signal ■NT monitors the level of power supply voltage VCCB. When the voltage VCCB>3V, the signal INT is set to low level. In other words, when the external power supply voltage is low, the internal initial state is set by the signal INT.

In this embodiment, a specific configuration of the delay circuit indicated by blank boxes is shown. This circuit delays the signal from low level to high level. By setting the terminal SET to a high level (V CC), the amount of delay can be shortened. These are widely used for timing adjustment in RAS systems, pulse generation in CAS and WE systems, and the like.

1 6 5 Output terminal Q/DQ4 is used as an internal voltage monitor terminal. The data output buffer coupled to this terminal is kept in an output high impedance state, and the signal VM
The operating voltage VCC for the peripheral circuit is output through the MOSFET which is switch-controlled by CH, and the signal V
An operating voltage V D L for the sense amplifier is outputted through a MOSFET whose switch is controlled by M D H.

Further, the output terminal Q/DQ4 is also used as a signature terminal for determining whether or not a defect has been completed. In Chisop where defect relief has been performed, SIGB becomes low level and Q/DQ4
When a voltage that is approximately three times or more higher than the threshold voltage vth than VCCE is applied to the terminal, a current flows into the ground potential of the circuit, thereby determining that the chip has undergone defect repair.

FIG. 67 shows a circuit diagram of an embodiment of the substrate back bias voltage generating circuit.

In this example, the operating voltage is a low voltage for peripheral circuits.
CC is used. The reason why the substrate high-ass voltage is formed using the internal voltage 1 6 6 vCC in this way is because the internal voltage Vcc is stabilized as described later, so that the substrate high-ass voltage can be stabilized.

The substrate bias voltage VBB is generated by the bias voltage generation circuit VB.
It is formed by BA and VBBS. The substrate bias voltage generating circuit VBBA is the main generating circuit, and when the substrate level is shallow, the substrate bias voltage generating circuit VBBA generates a substrate current Inl1 caused by the circuit during operation.
Works to compensate for.

The substrate high-ass voltage generating circuit VBBS is a sub-generating circuit, and operates steadily to compensate for fluctuations in VBB caused by leakage current or minute direct current.

Signal VBSB is a monitor output of the level of substrate voltage VBB. This controls the operation of the oscillation circuit,
When the above board level is shallow, VBB is set by circuit VBBA.
It is operated until it becomes about -2■.

Terminal VBT is connected to circuit VBBA. , V B
167 is used to stop the operation of the BS, set the substrate voltage from the outside through the VBB pad, and evaluate the operating margin.

FIG. 68 shows a circuit diagram of an embodiment of the internal boosted voltage generating circuit.

The circuit VCHA is the main boosted voltage generation circuit, and when the boosted voltage VCH monitor signal VHSB indicates that the voltage is low, or the signal RIB indicates that the RA
Internal operating voltage V for peripheral circuits when M is accessed
Oscillation signal O S formed by C C and the oscillation circuit
A boosted voltage VCH of about 5.3 .mu. as described above is formed by a charge pump circuit receiving C.sub.H. The circuit VCHS is a sub-boosted voltage generation circuit, and operates steadily to form the boosted voltage VCH. This circuit VC
The HS has only a small current supply capacity that compensates for the leakage current of the word line.

Note that the internal voltage V
CC is increased accordingly when the power supply voltage \lCCE is increased above a certain level. Correspondingly, the boosted voltage VCH is also raised by a constant 1/1, in response to the rise in VCC. A diode-type MO S FE 'r provided in the output section 1 6 8
Well, it's for Les \Reclambes.

The terminal VHT is used to stop the operation of the circuits V C HΔ and VCHS, set a boosted voltage from the outside through the VCH pad, and evaluate the operating margin.

Although not shown, the power supply impedance of the boosted voltage VCH
- Capacitors for lowering the dance are distributed and provided for each operating circuit unit, for example, each memory mat.

FIG. 69 shows a circuit diagram of an embodiment of the internal voltage step-down circuit.

The reference voltage VREF is a highly accurate reference voltage formed using the difference between the MOSFET and the threshold voltage vth. A constant voltage L is formed from this voltage, and is DC amplified by an operational amplifier circuit to generate the voltages VDL and VCC of approximately 3.3V. In order to reduce the operating current, the above voltage ■CC and VDL. The circuits that respectively generate LD and LC operate only when the DRAM is activated by the signals LD and LC. Separately from this, a circuit is provided which is in a steady state of operation in response to a signal LS when the power supply voltage VCCB is below a certain level, and forms a step-down voltage during high-level operation. Immediately after the power is turned on, the signal SB is generated by the signal INT until the external voltage VCCE reaches a certain voltage, and the signals LD and LC are forcibly activated accordingly.
and LS are formed, all the circuits become operational at the same time, and the internal circuit operating voltage is raised at high speed.

In the figure, the circuit shown by a resistor and a gapacitor is for increasing the phase margin for preventing oscillation.

By selectively cutting the fuses F1 to D4 with a laser beam, the reference voltage V L is set.
allows for adjustment.

In test 1/funksha 1, signal VB causes signal L.
D, LC, and LS are set to low level to stop the operation of the operational amplifier circuit, and the MOSFET turned on by the signal VH sets the low level to the case of the P-channel output MOSFET of the operational amplifier circuit. Supply and turn on. As a result, the external voltage VCCB changes the internal voltages DL and vCC to V through the P-channel MOSFET which is turned on.
It is possible to switch to CCE.

Further, when the external power supply voltage VCCB becomes higher than a certain level (for example, about 6.6V), the reference voltage VL increases accordingly, and the internal voltages VCC and VDL are also increased. This corresponds to accelerated tests such as aging.

FIG. 70 shows a timing diagram of an example of the operation of the RAS system.

This figure shows a schematic waveform diagram of the main timing signals from the start of memory access by the RAS signal to the selection of the word line WL and the reset bit of the word line.

FIG. 71 shows a timing diagram of an example of the operation of the RAS system.

The figure shows a word line selection timing diagram. Also, redundant system timing is shown in the second cycle.

FIG. 72 shows a timing diagram of an example of the operation of the RAS system.

The figure shows a timing signal for activating the sense amplifier and a waveform diagram of a common source line driven by the timing signal.

FIG. 73 shows a timing diagram showing an example of the operation of the X address buffer.

The diagram shows the mutual timing between the RAS and CAS signals.

FIG. 74 shows a timing diagram of an example of the operation of the CAS system.

In the same figure, read mode (READ), early write mode (FW), read/modify mode,
Waveform diagrams of main signals are shown in the order of write mode (RMW), RAS only refresh mode, CBR refresh mode, counter test mode, and test mode (WCBR).

FIG. 75 shows 1 7 of the CAS system address selection operation.
2. A timing diagram of one embodiment is shown.

The figure shows main timing signals for selecting Y-system addresses.

FIG. 76 shows a timing diagram showing an example of the lie 1 operation.

The figure shows main timing signals of the WE system.

FIG. 77 shows a timing diagram showing an example of the operation of the Y address buffer.

The diagram mainly depicts the timing signal YI-, which controls the address latch in fast page mode (FP), nibble mode (N), and static column mode (SC).

FIG. 78 shows a timing diagram illustrating one embodiment of the operation in the test mode.

The diagram mainly depicts address capture and latch operations.

FIG. 79 shows a timing diagram showing an example of the operation of the CAS system.

In the figure, test mode signals are targeted 1 7
3, read mode (READ), early write mode (EW), read modify write mode (RMW), RAS only refresh mode, CBR refresh mode, counter test mode,
The waveform diagrams of each signal are exemplarily shown in the order of and test mode set (WCBR).

FIG. 80 shows a timing diagram showing an example of the operation of the CAS system.

In the same figure, read mode (READ), early write mode (E
W), read-modify-write mode (RMW)
), RAS only refresh mode, CBR refresh mode, counter test mode, and test mode set bit (WCBR).

FIG. 81 shows a timing diagram showing an example of the operation of the CAS system.

In the same figure, the light mask mode is targeted at 1 7.
4 Read mode (READ), early write mode (EW), read modify write mode (RMW), RAS only refresh mode, C
Waveform diagrams of each signal are exemplarily shown in the order of BR refresh mode, counter test mode, and test mode set (WCBR).

FIG. 82 shows a block diagram showing another embodiment of the defect relief method according to the present invention.

One redundant word line is provided for a plurality of word lines selected by an X decoder (including a word line drive circuit). This redundant word line is arranged so as to intersect the plurality of word lines at a location corresponding to the X decoder, or in other words, to be parallel to the row of output terminals of the X decoder. Although not particularly limited, the redundant word line intersects with a plurality of word lines to be relieved by two parallel wiring lines. ” - One end of the two parallel wires is given a ground potential.

1 7 5 In this configuration, when there is no defect in the word line, the redundant word line is supplied with a ground potential and is therefore constantly in a non-selected state.

One of the word lines has a defect (
For example, if there is a break in the word line, the word line is cut at the location marked with a triangle in the figure. Similarly, in order to separate the redundant word line from the ground potential, the redundant word line is cut on the right side (redundant word line side) of the defective word line as indicated by a triangle. Then, the decode output forming the selection signal for the defective word line is connected to the redundant word line at the intersection marked with a circle. Similarly, in order to bring the defective word line into a non-selected state, it is connected to the wiring to which the ground potential is applied at the intersection marked with the circle. The above-mentioned wiring cutting and connection are not particularly limited, but are both performed using a wiring processing technique using laser beam irradiation.

In this configuration, the defective word line is separated from the output terminal of the word line selection circuit and a redundant word line is connected in its place, so a memory circuit for storing defective addresses and an address comparison circuit are not required. becomes. This enables higher integration and lower power consumption of semiconductor memory devices. Furthermore, since the address comparison operation as described above is no longer necessary, memory access can be speeded up.

In addition, when a redundant word line as described above is provided for each of multiple word lines, when the redundant word line is not used, a ground potential is constantly applied to the redundant word line, thereby suppressing cathode pull between the word lines. It can have an effect.

FIG. 83 shows a block diagram showing another embodiment of the defect teaching method according to the present invention.

One redundant column selection line is provided for a plurality of column selection lines formed by the Y decoder circuit.

Each of these column selection lines is transmitted to the gate of a column switch MOSFET included in the sense amplifier in the same figure, and substantially selects the bit line (data line) shown in the figure and becomes a common input/output line. Connect to. In other words, this redundant column selection line intersects with the plurality of 1 7 7 column selection lines at a location corresponding to the Y decoder.
It is arranged parallel to the row of output terminals of the Y decoder. Although not particularly limited, the redundant column selection line intersects with a plurality of column selection lines to be repaired by two parallel wiring lines. One end of the two wirings arranged in parallel is supplied with a ground potential.

In this configuration, when there is no defect in the bit line and the sense amplifier, the redundant column selection line is supplied with a ground potential and is therefore constantly in a non-selected state.

If one of the bit 1 lines has a defect (for example, a disconnection) at a location indicated by an x in the same figure, the column selection line is cut at a location indicated by a triangle in the same figure. Similarly, the redundant column selection line is cut off above the column selection line corresponding to the defective focus line (on the redundant column selection line side), as indicated by a triangle, in order to separate it from the ground potential. Then, the decode output forming the selection signal for the defective bit line is connected to the redundant column selection line at the intersection marked with a circle.

1 7 8 Similarly, in order to make the column selection line corresponding to the defective VISOL into a non-selected state, it is connected to the wiring to which the ground potential is applied at the intersection marked with the circle. The above-mentioned wiring cutting and connection are not particularly limited, but both are performed by laser beam irradiation.

In this configuration, the column selection line corresponding to the defective bit line is separated from the output terminal of the Y decoder and connected to the column selection line corresponding to the redundant bit line instead, so the memory circuit that stores the defective address This eliminates the need for an address comparison circuit.

This enables higher integration and lower power consumption of semiconductor memory devices. Furthermore, since the address comparison operation as described above is no longer necessary, memory access can be speeded up.

In addition, when a redundant column selection line as described above is provided for each of multiple column selection lines, when the redundant column selection line is not used, ground potential is constantly applied to it, thereby reducing coupling between the column selection lines. It is possible to provide a shielding effect by suppressing the ring.

FIGS. 84(A) to 84(C) show waveform diagrams and corresponding circuit diagrams of one embodiment for explaining a word line testing method.

In this embodiment, a control signal EM is newly provided. This signal EM is newly added as one test mode consisting of a combination of address signals in the test mode as described above, in addition to the one supplied from the external terminal. In the same figure (A>), there is shown a timing diagram of the general word line 111 & selection operation in the normal mode. In this way, in the normal mode, according to the selection operation of the RAS system, the input address designation A.O. to A3, the corresponding word lines are sequentially selected.

On the other hand, in the aging mode (set as one of the test 1 modes) in which the signal EM is set to high level, R
A. Even when the S signal is reset from low level to high level, the selected word line WLI is maintained at high level. Therefore, when the addresses AO to A31 8 0 incremented by the RAS signal are input, the word lines W selected sequentially as described above are input.
LI to WL3 are no longer reset when the RAS signal is at a high level. Although not particularly limited, each time the signal EM is brought to a low level, the word lines WLI to WI-3 set to the selected state are reset.

FIG. 2C shows a circuit diagram of one embodiment of the word line selection circuit. The signal EM is level-converted by a level conversion circuit consisting of a latch-type NOR gate circuit that uses the boosted voltage VCH as an operating voltage, and becomes a low level in the aging mode I. As a result, the P-channel MOSFET is turned on, and the high level of the word line WL is changed to the P-channel MOSFET receiving the signal WPHL.
The P-channel MOSFET connected in series with O S FE'F is turned off, and the word line
P channel receiving signal WPHL
Disable T's output. Once the word line WL is brought to a high level due to dirt, it remains in that state.

1 8 1 When resetting the word line WL or in the normal mode, the level conversion output becomes high level (VCH) in accordance with the low level of the signal E11/I. As a result, the P channel MOSFET is turned off, and the P channel MOSFET receiving the signal WPHL is turned off.
P-channel MOSFET connected in series with FET
C is both turned on and drives the word line WL.
With a high level of human power in the MOS inherta circuit,
The word line WL is reset from high level to low level.

Note that a switch MOSFET controlled by the inharter circuit receiving its output signal is provided at the input of the CMOS inharter circuit that drives the word line. This prevents the high level of the unselected signal XOUB from being transmitted to the CMOS inherter circuit that should not maintain the selection rail during multiple selection as described above.

During acing, if the signal EM is kept at a high level and the word lines are selected one by one, 182 word lines can be maintained in the selected state during that time. As a result, the high level time of the selected word line can be lengthened, so that the duty of the signal becomes high, making it possible to carry out efficient aging in a relatively short period of time.

85(A) to (D>) show an embodiment of the signal amount margin test method. In this embodiment, a control signal SM is newly provided. In addition to what is supplied, a new test mode consisting of a combination of address signals is added in the test mode as described above. In the same figure (A), sense amplifiers and preamps associated with a pair of complementary bit lines are added. A charge circuit, a column switch, and a senior switch circuit are shown as representative circuits.

FIG. 2B shows an operational waveform diagram in the normal mode. In the normal mode, the signal SM is set to low level. Accordingly, the selected word line (L
) side shared selection signal SHL The shared selection signal SHL on the word line (R) side is set to low level and unselected. Therefore, complementary bibit IB
h storage information from the selected memory cell is read out to L.

FIG. 2C shows an operational waveform diagram of the signal amount test I mode. When in signal amount test mode, signal S
M is made into a high-level hell. Accordingly, together with the shared selection signal SHL on the selected word line (L) side,
The shared selection signal S H R on the non-selected word vA(R) side is also set to high level. Therefore, since the left and right bit lines BL are coupled to the input of the sense amplifier, the bit line capacitance is approximately doubled. Therefore, the read level of stored information from the selected memory cell is reduced to about 1/2 of that in the normal mode. Accept this
It becomes possible to perform a signal amount margin test to determine whether the sense amplifier performs an accurate amplification operation.

FIG. 2D shows a circuit diagram of an embodiment of the shared selection signal generating circuit. In the figure, the control signal S
M is added and passed through a NOR gate circuit to control the validity/invalidity of the selection signals SL and SR. That is, when the signal SM is at a high level, the signal S L/
Both S R are forced to the selection level, shifting the signals S H L and SHR to the selection level of the high level. Note that this selection level is the boosted voltage VCH as described above.
This is the result.

FIG. 86 shows another embodiment of the function mode.

Binary numerical data is input directly from address terminals AO to A3 using a function signal formed by WCBR or the like. This numerical data is changed into analog voltages SO2 to S102 by, for example, a voltage decoder (digital/analog conversion circuit). This analog voltage SiV is supplied to an internal voltage generation circuit consisting of an operational amplifier circuit having a voltage follower configuration, etc., to form the internal voltages CC and VDL as described above. With this configuration, the internal operating voltage can be set arbitrarily.

This simplifies voltage margin tests, acceleration tests during aging, etc.

1 8 5 Further, the pinary numerical data directly from the address terminals AO to A3 is input to the time decoder and decoded signals SOD to S]. OD is formed and its signal is input to the SiD delay circuit. This delay circuit is connected to the signal SO
Delay time is O or L depending on D or SIOD Qns
It becomes variable as in This causes the signal S
An arbitrary delay time can be obtained using the iD. This delay circuit is used, for example, as a delay circuit when forming time-series timing signals of RAS system and CAS system. By using this, it becomes possible to test the time margin, for example.

FIG. 87 shows another embodiment of the refresh address counter. In this example, the control signal CS
will be newly established. In addition to being supplied from an external terminal, this signal CS is newly applied as a test mode consisting of a combination of address signals in the test mode as described above, or is formed by a power-on detection signal or the like.

1 8 6 In the same figure (A), an operation waveform diagram of the normal mode is shown. In the normal mode, the signal CS is set to low level. Accordingly, at the time of CBR refresh, the counter circuit performs a counting operation using the RAS signal 2 as a cross signal to form a refresh address signal ARi.

FIG. 2B shows an operational waveform diagram of the counter set. When the counter is set, the signal CS is set to high level. At this time, when CBR is performed, the address signal input in synchronization with the low level of the RAS signal is input as the counter initial value. When the signal CS becomes low level, the counter circuit increments its initial value by 1 and holds it.

A circuit diagram thereof is shown in FIG.

To enable external input as described above, an external set input circuit controlled by signal CS is added.

FIG. 88 shows another embodiment of the internal power supply monitor type.

The block is shown in FIG.

1 8 7 The voltage CC or VDL formed by the internal step-down power supply circuit VCC or VDL is supplied to one input of the level comparison circuit. The other power of the level comparator circuit is supplied with a reference voltage supplied via an external pin. The level comparison circuit outputs the magnitude relationship between both voltages to the external terminal DOUT as a binary signal.

FIG. 2B shows a waveform diagram for explaining the operation. By changing the voltage supplied to the external pin as shown by the dotted line in the figure, the voltage value of the voltage VDL can be indirectly determined from the point of change between the high level and low level of the output signal DOUT. The input voltage supplied from the external bin may be supplied as is to the level comparison circuit in a one-to-one correspondence, or may be supplied with the level attenuated or increased. Similarly, the voltages CC and VDL may also be attenuated in level at a constant rate. When the level is attenuated in this way, it becomes possible to monitor the level of the boosted voltage VCH as described above.

As in this embodiment, a level comparison circuit is provided internally.
In this configuration, the level can be monitored with high accuracy because it is not affected by level fluctuations in the output voltage path in a method that outputs the analog voltage as it is to the outside.

FIG. 90 shows a memory cell section, an N-channel type column switch MOSFET for Y selection, and other CMOS
A schematic cross-sectional view of the element structure of one embodiment of a P-channel MOSFET used in the circuit is shown. In the figure, a schematic cross-sectional view of the element structure in the bit line direction is shown.

N-channel M that constitutes memory cells and column switches
OSFET is a P-type W formed on a P-type substrate 41.
EL. Formed into L.

In the figure, a pair of memory cells are provided for a bit line 50 made of polycide. That is, a pad contact 47 made of conductive polysilicon is provided in a contact hole formed by a self-alignment technique for the shared source and drain 44 of the address selection MOSFETs constituting a pair of memory cells. The source and drain 44 on the capacitor side are provided on the left and right sides of the shared source and drain 44, respectively, and a gate electrode 46 is provided between the two regions with a thin gate insulating film 53 interposed therebetween.
is formed. This gate electrode 46 is made of conductive polysilicon and constitutes a word line. This word line is word shunted by an aluminum layer 52 formed thereon. The same figure also shows an address selection MOSF of another memory cell whose pinch is shifted perpendicularly to the same figure.
A word line 46 is exemplarily shown connected to the gate of ET. This word line 46 is formed on a relatively thick field insulating film.

The source and drain of the address selection MOSFET on the capacitor side are connected to a conductive polysilicon 48 constituting a store node of the information storage capacitor,
This polysilicon 48 is connected to a polysilicon 49 forming the plate electrode of the capacitor through a thin insulating film 54.
is provided.

Above the bit line 50, there is a column selection line of the shape 19.
A tungsten layer 51 is provided as a first metal layer consisting of 0. Although not particularly limited, the polycide 50 constituting the bit line is connected to the tungsten layer 51 via a shared selection switch MOSFET, which is omitted in the figure, and is one of the MOSFETs constituting the column switch in the figure. It is connected to the source and drain 44 of.

The source and drain 44 on the I/O side of this MOSFET are connected to the address selection MOS of the memory cell as described above.
Like the FET, it is connected to the input/output line I/O made of the second layer of aluminum 52 via the first metal layer 5l via the pad contact 47. Note that an example in which a P-channel MOSFET is provided is shown on the right side of the figure. This P-channel MOSFET is used in sense amplifiers and other CMOS circuits. In this way, the P-channel MOSFET is formed into an N-type well 43 and is composed of a source, a drain 45, and a gate 46.

In this embodiment, N channel M constitutes a column switch connected to input/output II/0191 as described above.
As an OSFET, a MOSF for selecting the address of the memory cell is connected to the input/output line I/O at the source and drain.
A pad contact 47 similar to ET is used. In this configuration, self-alignment technology can be used to make holes for contacts to be formed in the oxide film on the surface of the source and drain. As a result, the source and drain under the pad contact 47 do not need to be formed large in consideration of the mask shift for forming the contact hole, so that they can be formed as small as necessary as shown in the figure. This allows for higher integration and lower parasitic capacitance values. In particular, many column switches MOSFE. When the source and drain of T are connected, the parasitic capacitance value can be significantly reduced as the parasitic capacitance of the source drain of the column switch MOSFET is reduced. As a result, the wiring capacitance of the input/output line I/O can be significantly reduced, so that the signal transmission speed can be increased, making it possible to increase the speed of write/read operations.

In addition to the column switch MOSFET described above, MOSFETs that use pad contacts as described above include MOSFETs that configure sense amplifiers, bit line precharge MOSFETs, and bit line short MOSFETs.
It can be used in various circuits that require miniaturization and reduction of parasitic capacitance, such as ET, shared sense amplifier selection MOSFET, and word line driver MOSFET.

FIG. 92 shows a schematic circuit diagram showing another embodiment of the main amplifier selection circuit.

In the embodiment shown in the figure, the main amplifier MA is commonly used for memory mats arranged vertically with respect to the main amplifier MA. That is, a main amplifier MA is arranged at the center of a pair of memory mats consisting of a memory cell array M and a sense amplifier S. The human output lines I/O and T/OB of the memory mat are selectively connected to the input of the main amplifier MA via a switch 1 9 3 MOSFET whose switch is controlled by mat selection signals MSU and MSD. The layout relationship between the memory mat and the sense amplifiers is basically the same as that of the embodiment shown in FIG. 2, and the number of main amplifiers can be reduced.

If the number of main amplifiers is not simply reduced, the main amplifier MA can be placed above the upper memory mat 1 or below the lower memory mat. However, in this case, among the human output lines connected to the input terminal of the main amplifier MA, the wiring corresponding to the memory mat on the opposite side becomes long.

On the other hand, in the configuration in which the main amplifier is arranged in the center of the divided memory mats, as in the embodiment shown in FIG. 2 and the above-mentioned FIG. Since the lengths of O and ■/○B are equally short, memory access can be speeded up.

FIG. 93 shows a schematic circuit diagram showing still another embodiment of the main amplifier selection circuit.

In the embodiment shown in the figure, the main amplifier MA is May 1 9
4 It is commonly used in memory mats arranged vertically with respect to the amplifier MA. The memory mat of this embodiment uses a shared sense amplifier in which the memory cell array is divided into left and right halves by passing the sense amplifier S into the middle tc,-1. In this configuration, the divided memory cell arrays are regarded as memory mats, input/output lines I/O and 1/OB are arranged for each, and a switch MOSFET is connected to the switch itll J by the mat selection signal -qMso to MS3. Through the main amplifier M
selectively connected to the input of A. The layout relationship between the memory mat and the sense amplifier is basically the same as that of the embodiment shown in FIG. can. Furthermore, in the configuration in which input/output lines I/O and I/OB are arranged for a pair of memory cell arrays M, respectively, as in this embodiment, the column switch MOSFET connected to the human output lines I/O and I/OB is can be divided in half. This allows the length of the input/output lines to be substantially shortened (195), and in combination with this, the wiring capacitance can be reduced, making it possible to achieve high-speed operation.

FIG. 94 shows a layout 1 diagram of another embodiment of the DRAM according to the present invention.

In this embodiment, the layout shown in FIG. 2 is used as the basis,
A semiconductor chip is divided into two along a vertical center line, and the layout 1 shown in FIG. 2 is arranged axially symmetrically about the center line. In this configuration, each half of the memory chip is provided with a cross area consisting of the vertical center area and the horizontal center area. As shown in the figure, when the memory chip is divided along the vertical center line, the horizontal center portions are arranged on a straight line. The memory array is divided into eight parts by the two cross areas as described above. Peripheral circuits and bonding pads are placed in the above two cross areas as in the embodiment described above, and bonding is performed on each of them using the LOG REET.

When such layout 1 is applied to a dynamic RAM having a storage capacity of 16 Mbits, the word line length is shortened by half in the example shown in the figure, and even higher-speed access becomes possible. Additionally, since the memory mat is segmented into smaller pieces, it is possible to reduce power consumption accordingly. Further, by using the above-mentioned cross area and the four areas divided by it as the basic configuration, and providing two sets of them as above, it is possible to further increase the storage capacity of the RAM.

In addition to the configuration in which the memory chip is divided into two parts along the vertical center line of the memory chip and each area is provided with a cross area as described above, the memory chip is divided into two parts along the horizontal center line of the memory chip as in the previous embodiment. A cross-shaped area formed by a similar method may also be provided. Furthermore, these may be combined into other divisions.

FIG. 95 shows a pattern diagram of an embodiment of a memory cell array according to the present invention.

The Hiso1 lines are crossed at regular intervals to reduce mutual coupling noise between adjacent bit line pairs. When such a bit line crossing method 1 9 7 formula is adopted, a problem arises in that the area at the bit line crossing portion increases. Therefore, in this embodiment, a wiring layer used as a column selection line is used as a cross wiring. In other words, when the first metal layer is used as the column selection line as shown in the same figure, the first metal wiring formed in the upper layer is is used.

By adopting a configuration in which such a first metal layer is used, a dedicated wiring layer can be made unnecessary for the bit line cross section.

In order to equalize the parasitic capacitance between the bit line and the column selection line extending parallel to the bit line, the column selection line is bent at the bit line crossing portion so as to be shifted by one pitch of the bit line pair.

As a result, it is possible to make one column selection line in two pairs of bit lines have the same parasitic capacitance with respect to both bit line pairs, and by providing the above-mentioned bent portion, it is possible to create a bit line cross section. It can be used as This eliminates the need for a special area for the Viso I-line cross 198 portion, and it is possible to prevent the continuity of various wiring patterns from being impaired.

Further, when the bit line crossing portion is formed using the upper wiring layer, there is no adverse effect on the uniformity of the capacitors forming the underlying memory cells and the address selection MOSFETs. From the above, the continuity and uniformity of the devices (capacitors and MOSFETs) constituting the memory cell can be maintained, and variations in the characteristic margins of individual bison lines can be reduced. Furthermore, since the continuity of the pattern and the cross contact 1 are made by separating the vivid line contacts, no particular problems are caused in terms of manufacturing and processing conditions.

This is true in the cross-sectional view shown in FIG. 96(A) and in the same figure (
This can be easily understood from the schematic diagram shown in B). Same figure (
As shown in the cross-sectional view of A), at the intersection of the focus lines,
The bit line pairs made of polycide in the lower layer are separated from each other, one of the bit lines remains polycide and replaces the position of the other focus line, and the other piso 1 line is formed in the upper layer. 9. The first metal layer intersects with one of the bit lines and replaces the bit line with the first bit line.

97 to 99 show layout diagrams of an embodiment of a shared sense amplifier column and a corresponding memory cell array section.

In FIG. 97, Kumi layers 69 and 70 forming a step buffer region are provided between the memory cell array section located on the right side and the shared MOSFET, and are formed to extend vertically in the figure. There is. When a stacked memory cell is used as in this embodiment, this step buffer region is approximately
It becomes about μm high. For this reason, the difference in level between the memory cell array section and the peripheral circuit section becomes steep, making it difficult to process wiring layers and the like and to open holes in the vicinity of the step.

Therefore, as shown in the figure, the IN-th polysilicon 69, which is formed at the same time as the gate 1 electrode of the MOSFET, and the word line 70 for step buffering are joined together to form a 200 layer. In this configuration, as is clear from the cross-sectional view of FIG. 100, by providing the above-described dummy layer, the difference in level between the memory cell array section and the peripheral circuit section can be made gentler.

In addition, in this embodiment, using this step buffer area,
By forming an N diffusion layer in that portion and supplying voltage VDL, a guard ring function of the memory cell array section is provided. This can prevent minority carriers generated by, for example, operations on the peripheral circuit side from reaching the memory cell array section and combining with storage charges, thereby shortening the retention time.

FIG. 98 shows a pattern diagram of the Y gate (column switch MOSFET) section arranged on the left side of FIG. 97 and the P channel MOSFET 1' constituting the sense amplifier. Further, FIG. 99 shows a pattern diagram of the HISO line precharge MOSFET arranged on the left side, the N-channel MOSFET and shared MOSFET constituting the sense amplifier, and the memory cell array section on the left side. 1. In this way, a similar step buffer region is provided between the left memory cell array section and the shared MOSFET.

In FIGS. 97 to 99, reference numeral 61 indicates a bit line made of polyzide, which is arranged to extend in the horizontal direction as shown in the figure. 62 is a column selection line, which is composed of the first metal layer as in the above embodiment;
In the same figure, it is arranged so as to extend in the horizontal direction. 63
is a word line made of a polysilicon layer, and is word shunted by a second metal layer 68 provided above the word line. These word lines are arranged so as to extend in the vertical direction in the figure. 64 is an address selection MOSFET that constitutes a memory cell. In the figure, the storage capacitor is omitted because the pattern is complicated. 65 is a bit line contact, and a panned contact as in the previous embodiment is provided here.

66 is a diffusion layer. Reference numeral 67 denotes an input/output line (■/○), which is constructed of the second metal layer 202 in the same way as the word shan, and is arranged so as to extend vertically in the figure.

In addition, using the step buffer area to create a shared MOSFET
A second metal layer is formed to shunt the polysilicon constituting the gate to lower the actual resistance value and increase the speed.

101 to 108 show pattern diagrams of an embodiment of a memory cell array section in the word line direction and a peripheral circuit corresponding thereto.

In FIG. 101, the above-described step buffering region is provided on the left side of the memory cell array.

To buffer this level difference, dummy polysilicon wiring 78
is provided. Further, on the substrate surface under this step buffer region, a diffusion layer for a guard ring of the memory cell array and a wiring layer for applying a bias voltage V D L are provided.

In the memory cell array section, 71 indicates a diffusion layer;
Reference numeral 72 indicates a word line made of a polysilicon layer. In the figure, the capacitor pattern is omitted. 7
3 is a bit line made of polysilicon 2 0 3 as described above, and 74 is a second metal layer for word shunting. Reference numeral 75 denotes a column selection line, which is composed of the first metal layer.

76 is a bit line contact, which uses the pad contact described above.

A word driver is formed on the left side of the memory cell array portion, sandwiching a step buffering region. In this word driver, 79 is the gate of the word driver MOSFET, and 80 is the first metal layer on the output side connected to the word line of the driver MOSFET. 81 is M
This is a contact that connects to the source and drain diffusion layers of the OSFET. The entire word driver is the tenth word driver.
They are arranged to extend leftward in the order of FIGS. 102 to 105 with respect to the left side of FIG.

Further to the left end of the word driver shown in FIG. 105, X decoders are arranged in a line extending leftward as shown in FIGS. 106 and 107.

Figure 108 shows the memo 20 shown in Figure 101 above.
4 shows a pattern diagram of an embodiment of a word clear circuit provided on the right end side of the recell array section, in other words, on the other end side of the word line to which the output of the word driver is connected.

In the same figure, a similar step buffering region is provided between the right end of the memory cell array section and the word clear circuit. There, a step buffer wiring (polysilicon) and guard ring shunt 99 is provided.

In the figure, reference numeral 91 is a word clear signal line, which is formed of the second metal layer. 92 is the ground wire and 1
It is formed by two metal layers.

Reference numeral 93 denotes a word clear gate I, which is composed of a polysilicon layer. 94 is a diffusion layer. 95 is a dummy polysilicon layer for buffering the step difference. Reference numeral 96 denotes a word line signal layer 1, which is formed of a second metal layer. 97 is a word line made of polysilicon. 10
0 is a bit line made of polycrystalline silicon. Furthermore, the black opening indicates the contact portion.

2 0 5 The effects obtained from the above examples are as follows.

(1) Peripheral circuits are placed in a cross area consisting of the vertical center and the horizontal center of the semiconductor chip, and memory arrays are placed in the four areas divided by the cross area.

With this configuration, the maximum signal transmission path can be shortened to about half the chip size due to the peripheral circuits being placed in the center of the chip, making it possible to use DRAM with a large storage capacity.
This has the effect of increasing the speed of the process. In addition, by providing the above-mentioned cross area in both areas divided by the vertical center line of the semiconductor chip and adopting the same layout as above, it is possible to achieve an even larger storage capacity or faster speed. is obtained.

(2) By placing the X decoder and Y decoder on the edge of the above-mentioned cross area that is in contact with the memory array,
The signal transmission path with the address buffer and predecoder provided in the cross area can be shortened.

This has the effect of enabling a rational 2 0 6 layout and increased speed.

(3) In the above-mentioned cross area, at least one of the main amplifier, common source switch circuit, sense amplifier control signal generation circuit, and mat selection control circuit is placed in the area sandwiched between the X decoders in the vertical center or horizontal center. Place one. As a result, among the peripheral circuits arranged in the Jumonji area, the circuits corresponding to the X decoder, sense amplifier, and input/output line I/O are installed in the vicinity, so that the memory cell selection circuit and the transmission path of stored information are Since the layout can be streamlined, the effects of higher integration and higher speed can be obtained.

(4) Of the above-mentioned cross area, the area sandwiched between the Y decoders in the vertical center or horizontal center is provided with an address buffer,
At least one of a control logic circuit and a defect relief circuit corresponding to the control signal is arranged. With this configuration, a rational layout can be realized according to the signal propagation path, and the speed can be increased accordingly.

2 0 7 (5) At least one final driver circuit of the decoder input address signal generation circuit and at least one of the internally used power supply generation circuits are located in the center part of the above-mentioned cross area where the vertical center part and the horizontal center part overlap. Place one. As a result, the input signals for the X and Y decoders that select word lines and column selection lines are transmitted from the center of the chip to all four directions correspondingly, so the signal transmission path is divided. Since the load is divided and lightened, the speed can be increased.

(6) Among the peripheral circuits mentioned above, by placing the circuits that have the possibility of injecting minority carriers into the substrate in principle on or near the two center lines of the above-mentioned cross area, the peripheral circuits can be placed in the center of the chip. This arrangement provides the effect of minimizing the influence of minority carriers on the memory cell array portion while increasing the speed described above.

(7) 20 in the area divided into four by the cross area
8. The formed memory array is configured as an aggregate of a plurality of unit memory mats of the same size including sense amplifiers. With this configuration, the memory cell selection operation can be divided into two stages by adding the mat selection operation using the upper address to the memory cell selection operation within the mat, and the decoder can be divided accordingly, so that the decoding signal can be The effect is that the load is lightened and high-speed operation is achieved.

(8) At least one of an X decoder or a Y decoder is arranged in the memory array divided into four by the above-mentioned cross area so as to divide each memory array. As a result, the length of the word line or column selection line can be shortened as the word line or column selection line is substantially divided by the decoder, resulting in the effect that memory cells can be selected at high speed.

(9) The above unit memory map bit is provided with a control circuit that generates various evening and timing signals for memory cell selection operations based on the map bit selection signal. In addition, since a time-series operation sequence can be executed at an optimized timing within the memory mat, different memory blocks can communicate with each other in a large-capacity DRAM that is composed of many memory blocks. Since it is not necessary to take a timing margin of In addition, it becomes easy to change the number of memory map bits that operate, and it is possible to easily expand product types (lower power).

(10) In the unit memory mat, a pair of adjacent memory mats is treated as one subblock, and a control circuit for controlling the memory mat is provided for each subblock. With this configuration, since one memory mat can be selected in a sub-block, the control circuit can be used in common for a plurality of memory mats, resulting in the effect that higher integration and higher speed can be achieved.

(11) By constructing the above-mentioned unit memory mat by a pair of sub-blocks that are axially symmetrical, the control circuit can be used in common for more memory mats, resulting in higher integration and higher speed. This has the effect of making it possible.

(12) By activating the control circuit with the mat selection signal, subblock selection signal, or block selection signal, wasteful current consumption in unselected maso I/subblocks can be suppressed, resulting in low power consumption. This has the effect of increasing the number of people.

(13) The above control circuit precharges the complementary data line, activates the sense amplifier, and controls the shared sense amplifier! , activation of an X decoder, activation of a Y decoder circuit, activation of a word driver, selection of a common input/output line, selection of a main amplifier, or activation of a main amplifier. This provides the effect of optimizing the motion sequence control within the mat.

(14) The selection 21 1 signal for selecting the word line and complementary data line belonging to the memory mat is supplied to the memory mat. In the configuration 1-, the selection signal is generated by the BRIDGE decoding circuit, and the effect that the decoder circuit can be rationally divided can be obtained.

(15) A circuit for forming a selection signal for selecting a word line or complementary data line belonging to the memory mat of the above unit is installed for multiple memory mats or sub-blocks.
By providing them in common, there is no need to route the masoso 1 and control signals redundantly, so that it is possible to achieve lower power and higher speed.

(16) A dedicated address huffer is used to input the address signal for selecting the memory mat or memory block. With this configuration, the address signal that forms the Massot selection signal can be separated from relatively large load capacitances such as a large number of address comparison circuits provided in the redundant circuit, making it possible to increase the speed and precede the selection operation of the memory cell array. The effect is that it becomes possible to perform a mat selection operation by selecting the mat.

21 2 (17) Part or all of the bonding pads are placed within the cross area. This allows signals to be sent and received from the center of the chip, so that the signal transmission path is transmitted from the center of the chip to the periphery without spreading in all directions. Since the signal transmission path, which is involved in increasing the size of the chip, can be shortened, it is possible to achieve the effect of increasing the speed.

(18) All the bonding baths are arranged in two rows in a zigzag pattern at the vertical center of the cross area. This allows for efficient placement of a large number of bonding pads.
The effect is that high integration becomes possible.

(19) The bonding pads arranged in the vertical center of the above-mentioned cross area are bonded to the LOC lead frame, so that the lead frame is not connected to the power supply pad. Since the bonding bath can be regarded as a part of the wiring or can be provided close to the human-powered circuit, the effect of improving and speeding up level marking can be obtained.

(20) Among the bonding pad bits mentioned above, a plurality of pad bits that provide the circuit power supply voltage and ground potential are provided at appropriate intervals depending on the circuit block that requires them, and the circuit power supply voltage and ground potential are By connecting them to a common LOG REIT frame that respectively applies a potential, it is possible to suppress the noise level accompanying circuit operation to a low level, thereby achieving the effect that the operating margin can be improved.

(21) Among the bond pad bits, a plurality of panodes for applying a ground potential are provided according to the chip distribution of the sense amplifier array to be activated. As a result, a relatively large current due to the amplification operation of the sense amplifier is supplied from the corresponding band, and the noise level generated at the ground potential of other circuits can be suppressed to a low level, thereby expanding the operating margin. This has the effect of being able to.

(22) Peripheral circuits and Honda inverters are placed in the cross area consisting of the vertical center and the horizontal center of the semiconductor chip, and the memory array is placed in the four areas divided by the cross area, and the semiconductor Provide steps at the four corners of the chip. This has the effect of preventing the stress from the mortar thinner from being applied directly to the memory cell portion at the corner of the chip.

(23) The steps provided at the four corners of the semiconductor chip are:
By stacking wiring layers formed in the same process as the memory array manufacturing process, it is possible to disperse the stress applied to the chip from the mold resin without adding an additional manufacturing process. .

(24) A peripheral circuit is arranged in a cross area consisting of a vertical center part and a horizontal center part of the semiconductor chip, and a memory array is arranged in the four areas divided by the above-mentioned cross area,
A highly concentrated diffusion layer of the same conductivity type as the substrate is placed on the outermost periphery of the semiconductor chip to supply a substrate hack bias voltage, and a guard ring consisting of a diffusion layer of the opposite conductivity type to the substrate is placed inside the layer. Place it and supply the power voltage there.

This 2 1 5 configuration provides the effect of preventing undesired noise from entering the memory array section.

(25) Built-in is an internal step-down voltage generation circuit that operates with a power supply voltage supplied from an external terminal and generates an operating voltage for an internal circuit consisting of an output buffer for impedance conversion that receives a reference voltage. With this configuration, the operating voltage can be lowered in response to the reduction in breakdown voltage due to element miniaturization.
Moreover, the effect of reducing power consumption by lowering the operating voltage can be obtained. Furthermore, since the step-down voltage is formed using a reference constant voltage, it is not affected by fluctuations in the external power supply voltage, so that the operation of the internal circuit can be stabilized.

(26) By dividing the internal step-down voltage generating circuit into a memory array voltage and a peripheral circuit voltage, it is possible to prevent noise from occurring due to circuit operation.

(27) The step-down voltage generated by the internal step-down voltage generation circuit is set to a voltage approximately twice the rosin threshold voltage of the input buffer 21 6 circuit to which it is supplied. This provides the effect that the operating voltage can be used effectively and the input power margin can be expanded.

(28) The output circuit of the output buffer that performs the above impedance conversion operation has a CMOS configuration, and has a function of selectively outputting the power supply voltage through the P-channel MOSFET on the power supply voltage side. . This provides the effect of providing a function of switching the internal operating voltage to the power supply voltage supplied from the outside without adding a special circuit. This voltage switching function can be used, for example, for aging.

(29) Converting the signal to be output, which is generated by the internal circuit that operates with the step-down voltage generated by the internal step-down voltage generation circuit, into a level according to the power supply voltage supplied from the outside through the I/bell conversion circuit. Source follower output M
Drive OSFET. With this configuration, the level amplitude of the output signal can be increased and the amplitude of the drive signal can be increased, so that the effect of speeding up the operation 2 1 7 can be obtained.

(30) The output MOSFET is provided in parallel with an output MOSFET driven by a signal with a relatively small signal amplitude formed by the internal circuit. This allows the output signal to start changing at a relatively early timing, allowing the signal to change linearly over a relatively long period of time, without sacrificing the output operating speed. The effect is that the noise level generated in the power supply line and the ground line when the output signal changes can be reduced.

(31) The internal voltage generated by the internal step-down voltage generation circuit is output from the data output buffer in a high impedance state in the test mode, and is transmitted from its output terminal by a signal of the boolean/strump voltage or external power supply voltage level. It is selectively outputted via a switch MOSFET controlled by a switch. This has the effect that it is possible to monitor whether the internal power supply circuit is operating normally and to improve reliability.

2 1 8 (32) A selection signal for a word line or a shared sense amplifier is formed by a selection circuit whose operating voltage is a high voltage formed by boosting the internal step-down voltage. As a result, the boosted voltage can be made stable without being influenced by an external power supply, and the selection operation of word lines and the like can be made faster.

(33) A memory cell array is arranged symmetrically around the main amplifier, and input/output lines of the memory cell array are selectively connected to the main amplifier via switch MOSFETs that are switch-controlled in response to a memory cell array selection signal. . With this configuration, the number of main amplifiers can be reduced, and the actual wiring length of the input/output lines can be shortened, so that higher speeds can be achieved.

(34) A shared sense amplifier is adopted as the memory cell array, and input/output lines corresponding to the left and right memory mats are provided respectively, and a switch MO is controlled according to the mat selection signal.
Connect to common 2 1 9 main amplifiers via SFET. With this configuration, the length of the data line can be shortened due to the shared sense amplifier system, and since the human output line is correspondingly divided, the wiring capacitance of the input/output line can also be halved, resulting in the effect of increasing speed.

(35) By using the above unit memory mat as the memory cell array, the number of main amplifiers can be reduced and the wiring length of the input/output lines connected to them can be shortened, thereby realizing high-speed operation. can get.

(36) A latch circuit is provided which receives and holds a word line selection signal in response to a control signal, and a word line drive signal is formed by the output signal of the latch circuit. This allows multiple word lines to be selected in sequence.
The effect that aging etc. can be performed efficiently can be obtained.

(37) A mode is provided in which both left and right complementary data lines are connected to the shared sense amplifier in the test mode. As a result, since the capacitance of the complementary data line 2 2 0 is approximately doubled, the signal amount from the memory cell is relatively reduced by half, making it easy to carry out signal amount margin tests. Effects can be obtained.

(38) As a function setting mode, provide a function to input a corresponding multi-bit digital signal from the multi-bit address terminal and set the state of the internal circuit to the voltage or delay time corresponding to the digital signal. . This makes it easy to change internal operating voltages and signal delays, resulting in the effect that internal tests can be performed efficiently.

(39) A reset bit or initial value setting function can be added from the outside using a predetermined control signal, or a french address counter circuit can be provided. This provides the advantage that the refresh operation can be used for multiple selection of the word lines and selection of addresses for various read/write tests.

(40) Equipped with an internal power supply voltage generation circuit that forms the operating voltage of the internal circuit, and compares the voltage based on the internal voltage with the voltage applied from the outside, and generates a binary signal as a result of the comparison. Output. This configuration provides the effect that the internal operating voltage can be monitored with high accuracy.

(41) Sense amplifier in CMOS-configured DRAM, input buffer first stage circuit, output buffer final stage circuit, main amplifier first stage circuit, input/output line pull-up MO
S FET, complementary data line, and complementary input/output line} Among the MOSFET and diode-type MOSFET that constitutes the charge pump circuit, the threshold voltage of the MOSFET used in at least one circuit is set to the threshold voltage of the MOSFET used in the other circuit. It is assumed that the threshold voltage is lower than that of the MOSFET. This has the effect of making it possible to speed up the operation.

(42) Column switch MOSFET, MOSFET forming sense amplifier, precharge MOSFET
T, short MOSFET, word line drive MOSFET
MOSF for cutting T and shared sense amplifier
At least one type of M2 2 2 OSFET among the ETs has source and drain contacts as the source and drain contacts of the address selection MOSFET of the memory cell.
A band contact similar to the drain contact is used. As a result, self-alignment technology can be used for the source and drain contacts in the same manner as in memory cells, and the source and drain regions can be formed to the minimum necessary size. This has the effect of increasing integration and reducing parasitic capacitance, thereby increasing speed.

(43) By using the first metal layer used to configure the column selection line formed above the cross section in the bit line cross method, the wiring constituting the cross section is no longer necessary. At the same time, it is possible to obtain the effect that the uniformity of the underlying capacitor and MOSFET is not adversely affected.

(44) By making the column selection line correspond to two pairs of bit lines and arranging it by bending it so that it overlaps from one bit line pair to the other bit line pair in front of the bit line crossing part, a special This eliminates the need for a 2 3 cross wiring area, and has the effect that the parasitic capacitance between the column selection line and the bit line can be made uniform.

(45) By providing a step buffering region made of a dummy wiring layer between the stacked memory cell array part and its peripheral circuit part, the effect of facilitating wiring processing can be obtained.

(46) By arranging the guard ring under the step buffering region, it is possible to obtain the effect that the characteristics can be stabilized.

(47) It has a memory array consisting of a collection of memory mats of the same size each including a sense amplifier, and a redundant word line and/or a redundant data line is provided for each memory mat. In addition, a redundancy circuit consisting of a number less than the total number of redundant word lines and/or data lines configured from all of the above memory mats and more than the number of redundant word lines and/or data lines provided in one memory mat is provided. A memory mat is provided and used in common for each of the above memory mats. As a result, it is possible to reduce the scale of the circuit necessary for repairing defects, resulting in higher integration and lower power consumption.

(48) The redundant circuit includes a defective address storage circuit and an address comparison circuit, and is provided adjacent to the corresponding X and Y address buffers. As a result, the signal transmission path can be made as short as possible, resulting in the effects of faster operation and higher integration.

(49) At the output part of the word line or column selection circuit, a spare word line or a spare column selection line having wiring that intersects each of a plurality of word lines or column selection lines is formed, and a defective word line or a defective data line is formed. When this occurs, the output line of the word line or column selection circuit is disconnected from the column selection line corresponding to the defective word line or data line by laser beam irradiation, and connected to the spare word line or spare column selection line. In particular, we provide defect relief. This configuration eliminates the need for a storage circuit for defective addresses and a comparison circuit, so that it is possible to achieve high integration, high 225 speed, and low power consumption.

(50) In the multi-bibit simultaneous test mode by multiple selection of Y system, the memory block or Y
Only the S line is switched to the redundant data line or the redundant YS line. As a result, it is possible to reduce the number of redundant data lines or redundant ys lines to be prepared while shortening the test time by the multi-bit simultaneous test function.

(51) Divide the data line into multiple blocks using X, Y, an internally formed block address, or a combination of these, and use these signals to make only the defective block into a redundant data line or redundant YS line. By switching, it is possible to reduce the number of redundant data lines or redundant YS lines to be prepared.

(52) Divide the word line into multiple blocks using X, an internally generated block address, or a combination of these, and use these signals to switch only the defective block to a redundant word line. By doing so, it is possible to reduce the number of redundant word lines to be prepared.

(53) By using the same programming means as the means for programming the defective address as the block address, it is possible to simplify the program.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it is possible to make various changes without departing from the gist thereof. Not even. For example, the storage capacity of the Guinamisoku type RAM may be in addition to 16 Mbits as described above, a smaller one such as 4 Mbits, or a larger one such as 64 Mbits. In addition, a non-multiple method is used in which the X address and Y address are supplied from independent terminals as address inputs, and the storage capacity is accordingly increased to approximately 8 Mpis.
・or 24M bits may be used.

2 2 7 The present invention can be widely used in semiconductor memory devices having a large storage capacity as described above.

[Effects of the Invention] A brief explanation of the effects obtained by typical inventions disclosed in this section is as follows. That is, in each area divided by the semiconductor chip or its vertical center line, peripheral circuits are placed in a cross area consisting of the vertical center and horizontal center, and the four areas divided by the cross area are Place the memory array. With this configuration, the maximum signal transmission path can be shortened to about half the Chisop size as the peripheral circuits are placed in the center of the chip or area, making it possible to increase the speed of DRAMs with large storage capacities. It will be done. The memory array formed in the area divided into four by the above-mentioned cross area is constructed as an aggregate of a plurality of unit memory mats of the same size including sense amplifiers. With this configuration, the memory cell selection operation can be divided into two stages by adding the mat selection operation based on the upper address to the memory 2 2 8 cell selection operation in the mat, and the decoder can Since it can be divided, the load on the decoded signal is reduced and high-speed operation can be achieved. The memory mat is provided with a control circuit that generates various timing signals for memory cell selection operations based on the mat selection signal. This makes it possible to control the time-series operation sequence within the memory mat with optimized timing, achieving high-speed memory access and improving operating margins, as well as changing the number of operating memory mats. This makes it easier to develop new varieties.

All the bonding pads are arranged in two rows in a zigzag pattern in the vertical center of the cross area. This makes it possible to efficiently arrange a large number of bonding bands, as well as perform bonding to the LOG lead frame.
By doing so, it is possible to consider the REIT frame as part of the wiring for the power supply bathode and the Q terminal, and to provide a bonding pad close to the input circuit, improving the level margin. The speed will be increased. Peripheral circuits and boarding baths are placed in the cross area consisting of the center and horizontal center of the semiconductor chip, and memory arrays are placed in the four areas divided by the cross area, and the memory array section is placed in the four corners. By stacking wiring layers formed by the same process as the manufacturing process, stress on the chip from the mold resin can be dispersed.

It operates with a power supply voltage supplied from an external terminal, and includes an internal step-down voltage generation circuit that generates an operating voltage for an internal circuit consisting of an output buffer for impedance conversion that receives a reference voltage. With this configuration, the operating voltage can be lowered in accordance with the reduction in breakdown voltage due to element miniaturization, and the lowering of the operating voltage can reduce power consumption. Since the step-down voltage is formed using a reference constant voltage, it is not affected by fluctuations in the external power supply voltage, so that the operation of the internal circuit can be stabilized. By dividing the internal step-down voltage generating circuit into a memory array voltage and a peripheral circuit voltage, it is possible to prevent noise 230 from occurring due to circuit operation. The internal voltage generated by the above-mentioned internal step-down voltage generation circuit is set to the output high impedance state of the data output buffer in the test mode, and the switch is controlled by a signal at the boot 1 strap voltage or external power supply voltage level from its output terminal. It is selectively outputted via a switch MOSFET. Thereby, it is possible to monitor whether or not the internal power supply circuit is operating normally, and high reliability can be achieved.

As a word line or shared sense amplifier selection signal,
It is formed by a selection circuit whose operating voltage is a high voltage formed by boosting the internal step-down voltage.

This allows the boosted voltage to be stabilized without being affected by an external power supply, and also allows for faster selection of word lines and the like. CMOS configuration sense amplifier, input capacitor first stage circuit, output buffer final stage circuit, main amplifier first stage circuit, input/output line pull-assignment MOSFET
, Complementary Deak Line and Complementary Input/Output Line Show 1- M O
A MOS used in at least one circuit among the diode type MOSF2 3 1 ET that constitutes S F E 'f' and the charge pump circuit.
M used in other circuits as the threshold voltage of the FET
By having a threshold voltage lower than that of an OSFET, it is possible to increase the speed.

Column switch MOSFET, MOSFET that constitutes the sense amplifier, precharge MOSFET,
Short MOSFET, '7 single line drive MOSFET
and M OSFE for Kavit of Seat Sense Amplifier
At least one type of MOSFET among the MOSFETs is connected to its source and drain by using pad contacts 1 to 1 similar to the source and drain contacts of the address selection MOSFET of the memory cell as its source and drain contacts. 1. Ruin contact 1. Separate alignment technology can be used in the same way as memory cells, and the source. Since the drain region can be formed to the minimum required size, higher integration and higher speed can be achieved by reducing the parasitic capacitance of each wiring. By using the first layer of metal layer used for forming the column selection line formed on the cross section in the cross section of the bisolar line cross direction 2 3 2, the wiring constituting the cross section is It becomes unnecessary and does not adversely affect the uniformity of the underlying capacitor and MOSFET. In addition, by making the column selection line correspond to two pairs of bit lines and arranging it by bending it so that it is overlapping from one bit line pair to the other bit line pair in front of the bit line cross section, a special This eliminates the need for a large cross-wiring area and makes it possible to equalize the parasitic capacitance between the column selection line and the bit line. By providing a step-buffering area made of a dummy wiring layer between the stacked memory cell array part and its peripheral circuit part, processing of the wiring becomes easy.

It has a memory array consisting of a collection of memory mats of the same size each including a sense amplifier, and a redundant word line and/or redundant data line is provided for each memory mat. , less than the total number of redundant word lines and/or data lines configured from all of the above memory mats, and greater than the number of redundant word lines and/or data lines provided in one memory mat, or from 2 3 3 A redundant circuit is provided and used commonly for each of the L memory mats. This makes it possible to reduce the circuit scale required for defect relief, resulting in higher integration and lower power consumption. Defects occur when performing multi-bibit simultaneous testing l/mote by multiple selection of the Y system, or when dividing data lines or word lines into multiple blocks using address signals, internally formed block addresses, or a combination of these. The number of redundant data lines or redundant word lines to be prepared can be reduced by switching only redundant data lines and redundant word lines to blocks in which redundant data lines and redundant word lines exist.

[Brief explanation of drawings]

Figure 1 shows a Tainami Noku type RA to which this invention is applied.
FIG. 2 is a basic layout diagram of an embodiment of the DRA.M according to the present invention. Overall layout 1 and Figure 3 showing one embodiment of M are as follows. Layout 1 and Figure 4 show the detailed layout of the Bontinckpanoto, and Figure 4 shows an example of the address allocation.
4. A block diagram shown in FIG. 5 is a block diagram focusing on the control signal in the Dynamisoku-type RAM according to the present invention. FIG. 6 is a block diagram focusing on the operation sequence of the Dynamisoku-type RAM according to the present invention. is a layout diagram specifically explaining the relationship between the power supply line and the related power supply circuit and the pad, and Figure 8 is the relationship between the grounding line of the circuit and the related internal power supply circuit and the pad. 9(A) and (B) are specific layout diagrams showing one embodiment of the input protection circuit according to the present invention, and a cross-sectional view thereof; FIG. 10 is a layout diagram for specifically explaining the , a specific layout diagram 1 showing an example of an input protection circuit provided on an external power supply voltage pad; FIG. 11 is a layout diagram showing an example of the peripheral area of a semiconductor chip; FIG. 13 is a schematic sectional view of the outermost periphery thereof; FIG. 14 is a basic layout diagram showing another embodiment of the Guinamisoku type RAM according to the present invention; FIG. 15 is a basic layout diagram showing another embodiment of the Guinamisoku type RAM, FIG. 16 is a basic layout diagram showing still another embodiment of the Guinamisoku RAM, and FIG. 17 (A ) to (C) are layout diagrams of the basic configuration of another embodiment of the memory mat and another embodiment of the memory block constructed by combining the basic configuration, and FIGS. 18(A) to (C) 19 is a layout diagram of another embodiment of the memory block constructed by combining the basic configuration of another embodiment of the above memory mat, and FIGS. The basic configuration of another embodiment of the memory mat and the layout diagram of another embodiment of the memory block constructed by combining the same are shown in FIGS. 20(A) to 20(C).
21 (A) and 21 (B) show the basic configuration of yet another embodiment of the 6-bit block and the layout diagram of another embodiment of the memory block constructed by combining the above sub-blocks. A basic configuration of another embodiment and a layout diagram of another embodiment of a memory block constructed by combining the same, FIG. 22 shows a lead frame used in a dynamic RAM according to the present invention. 23(A) to 23(C) are schematic side views showing an example of connection between the lead frame and the semiconductor chip, and FIGS. 24(A) and 24(B) are plan views showing one embodiment. 25(A) to (C) are external terminal bin layout diagrams showing an embodiment of the Guinami-soku type RAM according to the present invention. , Figure 26 shows the case where a ZIP type pancage is used.
FIG. 27 is a pin layout diagram of external terminals showing one embodiment of 7.
FIG. 28 is a pin layout diagram of external terminals showing an example of the case where an SOJ type path cage is used; FIG. FIG. 29 is another partial circuit diagram showing one embodiment of the above control circuit, FIG. 30 is another partial circuit diagram showing one embodiment of the above control circuit, and FIG. 31 is a partial circuit diagram showing one embodiment of the above control circuit. FIG. 32 is a circuit diagram showing an embodiment of the X address buffer circuit in a dynamic RAM; FIG. 32 is a circuit diagram showing an embodiment of the address buffer circuit corresponding to the X address signals A9 and AIO; FIG. 34 is a circuit diagram showing an embodiment of the address buffer corresponding to the address signal All. 2 3 8 FIG. 35 is a circuit diagram showing an embodiment of the address buffer corresponding to the X address signal A8. FIG. 36 is a circuit diagram showing an example of an X-system redundant circuit; FIG. 37 is an implementation of a decoder circuit for word line selection. A partial circuit diagram showing an example; FIG. 38 is a partial circuit diagram showing an example of a decoder circuit that selects a redundant word line; FIG. 39 is a partial circuit diagram showing an example of a timing generation circuit for activating a sense amplifier. A circuit diagram showing an example, FIG. 40 is a partial circuit diagram showing an embodiment of the control circuit provided in the memory mat, and FIG. 41 is an embodiment of the X decoder, word line drive circuit, and shared fresh fish line drive circuit. A circuit diagram showing an example. FIG. 42 is a circuit diagram showing an example of a memory cell array. FIG. 43 is a circuit diagram showing an example of a refresh address counter circuit. FIG. 44 is a circuit diagram showing an example of a refresh address counter circuit. Control circuit 1 2 3
9. Partial circuit diagram showing an embodiment. FIG. 45 is a circuit diagram showing an embodiment of a Y address buffer. FIG. 46 is a partial circuit diagram showing an embodiment of a Y-system redundant circuit. Figure 48 is a partial circuit diagram showing an example of the Y-system redundant circuit; Figure 49 is a partial circuit diagram showing an example of the Y-system redundant circuit; FIG. 50 is a circuit diagram showing an embodiment of a pre-decoder circuit for address signals. FIG. 50 is a circuit diagram showing an embodiment of a Y-system decoder forming a column selection signal. FIG. 51 is an embodiment of a nibble counter circuit. 52 is a partial circuit diagram illustrating an embodiment of a control circuit that forms a Y-system control signal; FIG. 53 is a circuit diagram illustrating an embodiment of an operation mode determination circuit; Figure 54 shows an implementation of the Y system control circuit 2 4
0 Partial circuit diagram showing an example. Figure 55 is a partial circuit diagram showing an example of a WE system control/roll circuit. Figure 56 is a partial circuit diagram showing an example of a WE system control circuit. FIG. 57 is a circuit diagram showing an embodiment of the data driver buffer, FIG. 58 is a circuit diagram showing an embodiment of the main amplifier control circuit, and FIG. 59 is a circuit diagram of an embodiment of the main amplifier control circuit. 60 is a circuit diagram showing an example of a main amplifier data output control circuit; FIG. 61 is a circuit diagram showing an example of a main amplifier output control circuit; 62 is a circuit diagram showing one embodiment of the data output buffer, FIG. 63 is a partial circuit diagram showing one embodiment of the test circuit, and FIG. 64 is a circuit diagram showing one embodiment of the test circuit. 4
1 Partial circuit diagram. FIG. 65 is a circuit diagram showing an embodiment of a control circuit that specifies an operation mode. FIG. 66 is a circuit diagram showing an embodiment of another control circuit. FIG. 68 is a circuit diagram showing one embodiment of the substrate back bias voltage generation circuit; FIG. 68 is a circuit diagram showing one embodiment of the internal field voltage generation circuit; FIG. 69 is a circuit diagram showing one embodiment of the internal step-down voltage generation circuit. FIG. 70 is a timing diagram showing an example of the operation of the RAS system; FIG. 71 is a timing diagram showing an example of the operation of the RAS system; FIG. 72 is a timing diagram showing an example of the operation of the RAS system. Figure 73 is a timing diagram showing an example of the operation of the X address buffer. Figure 74 is a timing diagram showing an example of the operation of the CAS system.
2. Figure 75 is a timing diagram showing an example of a CAS system address selection operation. Figure 76 is a timing diagram showing an example of a write operation. Figure 77 is an example of Y address buffer operation. Timing diagram: Figure 78 is a timing diagram showing an example of the operation of the test l/mote; Figure 79 is a timing diagram showing an example of the operation of the CAS system; Figure 80 is a timing diagram showing an example of the operation of the CAS system. FIG. 81 is a timing diagram showing an example of the operation of the CAS system. FIG. 82 is a block diagram showing another embodiment of the defect relief method according to the present invention. FIG. 83 is a timing diagram showing an example of the operation of the CAS system. A block diagram illustrating another embodiment of such defect teaching method. Figures 84 (8) to (C) are waveform diagrams and waveform diagrams of an embodiment for explaining the word line testing method. Circuit diagrams, Figures 85 (A) to (D) are circuit diagrams and their waveform diagrams showing one embodiment for explaining the signal amount margin test method, and Figure 86 is a circuit diagram showing an example of the signal amount margin test method, and its waveform diagram. 87 (A) to (C) are a block diagram showing one embodiment, and FIGS. 88 (A) and (B) are waveform diagrams and circuit diagrams showing another embodiment of the refresh address counter. , a bronc diagram showing another embodiment of the internal power supply monitoring method and a waveform diagram explaining the same,
Figure 89 (A.) and (B.
) is a circuit diagram and its waveform diagram for explaining the principle of the multi-bit test method, FIG. 90 is a sectional view of the element structure in the bit line direction showing an embodiment of the present invention, and FIGS. FIG. 92 is a block diagram showing an example of the layout of the main amplifier and memory cell array according to the present invention. , FIG. 93 is a block diagram showing layouts 1 to other embodiments of the main amplifier and memory cell array according to the present invention, and FIG. 94 shows another embodiment of the semiconductor chip according to the present invention. Figure 95 is a pattern diagram showing one embodiment of the memory cell array according to the invention, and Figures 96 (A) and (B) are diagrams showing the cross section of the Viso I-line. Cross-sectional view and schematic diagram of the tank to be explained, Figures 97 to 99
100 is a pattern diagram of an embodiment of a shared sense amplifier row section in the bit line direction and a memory cell array section corresponding thereto. FIG.
1 is a pattern diagram showing a memory cell array section in the word line direction and an example of a word driver corresponding thereto; 102nd to 105th are pattern diagrams showing an example of word driver 8 corresponding thereto; 2 4 5 FIGS. 106 and 107 are pattern diagrams showing one embodiment of the corresponding X decoder, and FIG. 108 is a pattern diagram showing one embodiment of the memory cell array section and word clear circuit extending in the word line direction. It is a diagram. DVI... Y address driver, DV2... X address try 8, l) V 3... Mat selection driver, 1...
・Paso F' V C C B for external power supply, 2... Pad for external power supply VCCB, 3... Internal step-down power supply circuit (VCC
), 4...internal step-down power supply circuit (VDL), 5...v'
c c wiring, 6...VDL wiring, 7...power supply pad VCCE for data output buffer, 11...word clear, ground t supply band for word cotton pad, 12...
・Ground potential path for common source of sense amplifier, 13
・・Panodo for data output buffer, 14・・Internal step-down power supply circuit, ground potential path for address buffer・, 15・
・Ground potential band for other circuits, 21...Mold resin, 22...Lead frame, 23...Chisop, 24
・・Film, 25・・Gold wire, 262 4 6 ・・Adhesive A, 27・・Adhesive B, 28・・Insulator, 2
9...Adhesive C, 30...Adhesive D, 31...Mold resin, 32...Lead frame, 33...Chisob, 34
・・Film, 35・・Gold wire, 36・・Busbar lead, 37・・Hanging wire, 38・・Bondy 4 ring pavit, 39・・Index, 41・・P board, 42・・P type WE1 , I5, 43...N type W E L
L, 44...N゛diffusion layer, 45...P+diffusion layer, 46
...Polysilicon (gate, word line), 47...Polysilicon (pad contact I-), 48...Polysilicon (capacitor 1 to anode), 49...Polysilicon (capacitor plate) , 50... polycyte (
bit I line), 51...1st layer metal (tungsten), 52...2nd layer methanol (anoleminium),
53...first gate insulating film (MOSFET), 54...
2nd gate insulating film (capacitor), 61...Bit line (polycide), 62...Column selection line (first layer metal), 63...Word line (polysilicon), 64...M
O S F E T, 2 47 65... Viso I-line contact, 66... Diffusion layer, 67
・・Input/output line, 68 ・・Word shift, Yant, 69, 70
...Dummy wiring layer, 71...Diffusion layer, 72...Word line (polysilicon) 73...Bit line (polycide),
74...Word line shunt (second metal layer), 7
5... Column selection line (first metal layer) 76... Bit line contact (uses Pabit' polysilicon) 77...
・Diffusion layer for guard ring of memory cell array, 78...
Step buffer wiring (polysilicon), 79... word driver gate, 80... word line (driver MOSFE)
T output side wiring), 81...diffusion layer contact, 91...
- Word clear signal line (second metal layer) 92... Ground line (IJi metal layer) 93... Word clear gate (polysilicon) 94... Diffusion layer, 95... Step buffer wiring (polysilicon) )96...Word line shunt layer (
2nd metal layer) 97...Word line (polysilicon) 9
8... Diffusion layer for guard ring of memory cell array, 99
・・Wiring for level difference reduction (polysilicon and guard ring shear 2 4 8 2 4 9 N r→ Law Σri≧Q and one i → Law −532− 2 Rimi Q 2≧o X> − to 11 1ΣRimiQ JP-A-3 214669 (79) JP-A-3 - 214669 (81) JP-A-3 -
214669 (83)-1540- Ward Unexamined Publication Hei 3 - 214669 (90) r~ ■ Law〉 Husakae Shi Kyo Eishi Expenses Kidney Takashi Some Unexamined Patent Publication Hei 3 214669 (92) Concave Unexamined Patent Publication Heisei 3 214669 (93) Unexamined Patent Publication Hei 3 3 214669 (97) JP-A-3 214669 (98) -555- JP-A-3 - 214669 (104) Ward JP-A-3 - 214669 (108) JP-A-3 -
214669 (109) Choichiichi JP-A-3-214669 (110) OO QO JP-A-3-214669 (115) OO OO JP-A-3 214669 (117) Ku Takumi■ (Fu Hoku) Mon JP-A-3 214669 ( 122) 〇2nd Industrial Patent Publication No. 3 214669 (126) ≦ ≦ ≦ 214669 (130) 214669 214669 (131) Manabu Kakuzaki @ Inventor Tetsuro Matsumoto 2326 Imai, Ome City, Tokyo Inside the Device Development Center, Hitachi, Ltd. 5-20-1 Josui Honmachi, Kodaira, Tokyo Inside the Musashi Factory, Hitachi, Ltd. Josui, Kodaira, Tokyo 5-20-1 Honmachi Hitachi Super L.
SI Engineering Co., Ltd. 5-20-1 Kamizu Honmachi, Kodaira-shi, Tokyo
SI Engineering Co., Ltd. 5-20-1 Kamizu Honmachi, Kodaira-shi, Tokyo
SI Engineering Co., Ltd. 5-20-1 Kamizu Honmachi, Kodaira-shi, Tokyo
SI Engineering Co., Ltd. 5-20-1 Kamizu Honmachi, Kodaira-shi, Tokyo
SI Engineering Co., Ltd. 5-20-1 Kamizu Honmachi, Kodaira-shi, Tokyo
606 Hitachi, Ltd. Device Development Center, 2326 Imai, Ome-shi, Tokyo, SI Engineering Co., Ltd. - 13, Juho Tadashi'': (Method) Amendment of the name of the invention on October 1, 1990 Address Name Address Name Semiconductor Storage Device and Defect Remedy Method Patent 1-Kawa 119jA 4-6 Kanda Surugadai, Chiyo III-ku, Tokyo (510)
Representative of RZTLEW Isho 5K Katsushige Mita Tokyo pIX 5-20-1-Kamimizuki-cho, Taira-shi Hitachi Super LSI Engineering Co., Ltd. Target of amendment Drawing of the detailed statement of amendment 1111 Vehicle description column Correct as shown in the attached sheet. Attachment■. Specification, page 245, lines 10 to 11 r, Figure 96 (
A) and (B) are cross-sectional views and schematic diagrams for explaining the line cross portion of the memory cell array according to the present invention. 1999 Patent Application No. 65840 Address (510) Nippon St Bowa Co., Ltd. Representative Katsushige Mita @ 187 5-chome Moe, D-layer, TJ Tsubo-shi, Tokyo No. 20 No. 1 Hitachi Super Enore SI Engineering Co., Ltd. Representative Minoru Ohno

Claims (1)

[Scope of Claims] 1. Peripheral circuits are arranged in a cross area consisting of a vertical center part and a horizontal center part in both areas divided into halves by a semiconductor chip or its vertical center line, and divided by the above-mentioned cross area. A semiconductor memory device characterized in that a memory array is arranged in four areas. 2. The semiconductor memory device according to claim 1, wherein an X decoder and a Y decoder are arranged at an edge of the cross area that is in contact with the memory array. 3. Of the above-mentioned cross area, at least one of the main amplifier, common source switch circuit, sense amplifier control signal generation circuit, and mat selection control circuit is located in the area sandwiched between the X decoders in the vertical center or the horizontal center. 3. The semiconductor memory device according to claim 2, wherein: a. 4. Of the above-mentioned cross areas, at least one of an address buffer, a control logic circuit corresponding to a control signal, and a defect relief circuit is arranged in the area sandwiched between the Y decoders at the vertical center or the horizontal center. A semiconductor memory device according to claim 2, characterized in that: 5. At least one of the final driver circuit of the decoder input address signal generation circuit and the internally used power supply generation circuit is arranged in the center part of the cross area where the vertical center part and the horizontal center part overlap. A semiconductor memory device according to any one of claims 1, 2, 3, or 4, characterized in that: 6. A semiconductor memory device characterized in that, among the peripheral circuits, a circuit that has the possibility of injecting minority carriers into the substrate in principle is arranged on or near two center lines of the cross area. 7. The memory array formed in the area divided into four by the above-mentioned cross area is characterized in that it is configured as an aggregate of a plurality of unit memory mats of the same size including sense amplifiers. Semiconductor storage device. 8. The claim characterized in that the memory array divided into four by the cross area is provided with at least one of an X decoder or a Y decoder so as to divide each memory array. The semiconductor memory device according to item 7. 9. The semiconductor memory device according to claim 7, wherein the unit memory mat includes a control circuit that generates various timing signals for memory cell selection operations based on the mat selection signal. 10. Claims characterized in that the unit of memory mat is one in which a pair of adjacent memory mats is treated as one sub-block, and a control circuit for controlling the memory mat is provided for each sub-block. 9. The semiconductor memory device according to item 9. 11. Claim 9, characterized in that the pair of axially symmetrical sub-blocks is treated as one block, and a control circuit for controlling the memory mat is provided for each block. The semiconductor storage device described above. 12. The semiconductor according to claim 9, 10, or 11, wherein the control circuit is activated by the mat selection signal, subblock selection signal, or block selection signal. Storage device. 13. The control circuit precharges the complementary data line;
Activation of sense amplifier, control of shared sense amplifier, activation of X decoder, activation of Y decoder circuit, activation of word driver, selection of common output line, selection of main amplifier, or activation of main amplifier. The semiconductor memory device according to claim 9, 10, 11, or 12, wherein at least one of the semiconductor memory devices is controlled. 14. The semiconductor memory device according to claim 7, wherein said unit memory mat is supplied with a selection signal for selecting the word line and complementary data line belonging thereto. 15. A patent claim characterized in that a circuit for forming a selection signal for selecting a word line or complementary data line belonging to the unit memory mat is provided in common for a plurality of memory mats or subblocks. Range 7th and 9th
Or the semiconductor memory device according to item 10. 16. Claims 9, 10, and 11, wherein the memory mat or memory block selection signal is formed by decoding an address signal input through a dedicated address buffer. , 12th,
The semiconductor memory device according to item 13, 14, or 15. 17. Claims 1, 2, 3, 4, 5, and 6, characterized in that part or all of the voiding pad is arranged within the cross area.
Or the semiconductor memory device according to item 7. 18. The semiconductor memory device according to claim 17, wherein all the voiding pads are arranged in two rows in a zigzag shape in the vertical center of the cross area. 19. The semiconductor memory device according to claim 17, wherein the bonding pads arranged in the vertical center of the cross area are bonded to a LOC lead frame. 20. Of the bonding pads mentioned above, a plurality of pads are provided at appropriate intervals depending on the circuit block that requires them, and pads that provide the power supply voltage and ground potential of the circuit are provided. 20. The semiconductor memory device according to claim 19, wherein the semiconductor memory device is connected to a common LOC lead frame provided respectively. 21. The semiconductor memory device according to claim 19, wherein among the bonding pads, a plurality of pads for applying a ground potential are provided according to the chip distribution of the sense amplifier array to be activated. . 22. Arranging peripheral circuits and bonding pads in a cross area consisting of the vertical center and horizontal center of the semiconductor chip,
A semiconductor memory device characterized in that a memory array is arranged in the four regions divided by the above-mentioned cross area, and steps are provided at the four corners of the semiconductor chip. 23. Claim 22, characterized in that the steps provided at the four corners of the semiconductor chip are formed by stacking wiring layers formed by the same process as the manufacturing process of the memory array part. The semiconductor storage device described above. 24. Peripheral circuits are placed in the cross area consisting of the vertical center and the horizontal center of the semiconductor chip, the memory array is placed in the four areas divided by the cross area, and the substrate is placed on the outermost periphery of the semiconductor chip. A highly concentrated diffusion layer of the same conductivity type as the substrate is arranged to supply a substrate back bias voltage, and a guard ring made of a diffusion layer of the opposite conductivity type to the substrate is arranged inside the layer and a power supply voltage is supplied thereto. A semiconductor memory device characterized by: 25. It operates in response to a power supply voltage supplied from an external terminal, and consists of one or more output buffers for impedance conversion that receives a reference voltage generated by a reference voltage generation circuit, and forms the operating voltage of the internal circuit. A semiconductor memory device characterized by having one or more internal step-down voltage generating circuits. 26. The semiconductor memory according to claim 25, wherein the internal step-down voltage generating circuit is provided respectively corresponding to an operating voltage for a memory array and an operating voltage for a peripheral circuit. Device. 27. Claims characterized in that the step-down voltage generated by the internal step-down voltage generation circuit is set to a voltage approximately twice the logic threshold voltage of the input buffer circuit to which it is supplied. 25th or 26th
The semiconductor storage device described in 1. 28. The semiconductor according to claim 25, wherein the output buffer has a function of selectively outputting the power supply voltage through a P-channel MOSFET on the power supply voltage side among the output MOSFETs. Storage device. 29. An internal step-down voltage generation circuit consisting of one or more circuits that operates in response to a power supply voltage supplied from an external terminal and forms an operating voltage for the internal circuit, and a signal to be outputted formed by the internal circuit to the external circuit. a level conversion circuit that converts the signal level corresponding to the power supply voltage supplied from the terminal;
1. A semiconductor memory device comprising: an output circuit including a source follower type output MOSFET whose gate is supplied with a signal to be outputted through the level conversion circuit. 30. The output circuit including the source follower type output MOSFET has an output MOSFET that receives the signal formed by the internal circuit to be output as is, in contrast to the output MOSFET that receives the signal passed through the level conversion circuit.
29. The semiconductor memory device according to claim 29, wherein the semiconductor memory device is provided in parallel. 31. The step-down voltage generated by the internal step-down voltage generation circuit is controlled by a switch from the output terminal of the data output buffer by a signal at the food strap voltage or external power supply voltage level, with the data output buffer in the output high-impedance state in the test mode. 27. The semiconductor memory device according to claim 26, wherein the semiconductor memory device is capable of being selectively outputted via a switch MOSFET. 32. The selection signal for the word line or shared sense amplifier is formed by a selection circuit whose operating voltage is a high voltage formed by boosting the internal step-down voltage. 26. The semiconductor storage device according to item 25. 33. Arranging at least one pair of memory cell arrays symmetrically with respect to a main amplifier, the main amplifier is connected to the pair of memory cell arrays through a switch circuit that is switch-controlled in response to the selection operation of the pair of memory cell arrays. A semiconductor memory device characterized in that it is selectively connected to an input/output line of. 34. The memory cell array has a shared sense amplifier in which a sense amplifier is arranged in the center of the data line pair divided into two, and four pairs of inputs corresponding to the data line pairs divided into left and right by this sense amplifier. 34. The semiconductor memory device according to claim 33, wherein the output line is connected to the memory amplifier via a switch circuit that is switch-controlled in response to a selection operation of the memory cell array. 35. The semiconductor memory device according to claim 10, wherein the memory cell array is the memory mat. 36. A semiconductor memory device characterized in that a latch circuit is provided to receive and hold a word line selection signal in response to a control signal, and a word line drive signal is formed by an output signal of the latch circuit. 37. A semiconductor memory device characterized in that a shared sense amplifier has an operation mode in which both selected and non-selected data lines are connected. 38. In the function setting mode, a digital signal consisting of a plurality of bits corresponding to the address terminal is inputted from an address terminal consisting of a plurality of bits, and the state of the internal circuit is set to the voltage or delay time corresponding to the digital signal. Characteristic semiconductor memory device. 39. A semiconductor memory device comprising a refresh address counter circuit having an external reset or initial value setting function in response to a predetermined control signal. 40. A power supply monitor function that includes an internal power supply voltage generation circuit that forms the operating voltage of the internal circuit, compares the voltage based on the internal voltage with the voltage applied from the outside, and outputs a binary signal as a result of the comparison. A semiconductor memory device characterized by having: 41. Consists of CMOS configuration, sense amplifier, input buffer first stage circuit, output buffer final stage circuit, main amplifier first stage circuit, input/output line pull-up MOSFET,
Short MOSFET for complementary data lines and complementary input/output lines
and M in the form of a diode constituting the charge pump circuit.
A semiconductor memory device characterized in that a MOSFET used in at least one circuit among the OSFETs has a low threshold voltage. 42. At least one type of MOSFET among the column switch MOSFET, MOSFET constituting the sense amplifier, precharge MOSFET, short MOSFET, word line drive MOSFET, and shared sense amplifier cut MOSFET is connected to the memory as its source and drain contacts. MO for cell address selection
A semiconductor memory device characterized by using pad contacts similar to source and drain contacts of an SFET. 43. A pair of bit lines arranged in parallel are constructed by a bit line crossing method, and the first metal wiring layer constructed on the wiring layer constituting the bit line at the crossing part. 1. A semiconductor memory device characterized in that bit lines are replaced using a . 44. The first metal wiring layer also constitutes a column selection line, and one column selection line is provided corresponding to two bit line pairs, and is different from the bit line cross section. 44. The semiconductor memory device according to claim 43, wherein the semiconductor memory device is arranged so as to be bent so as to partially overlap from one bit line pair to the other bit line pair. 45. A semiconductor memory device characterized in that a step buffer region made of a dummy wiring layer is provided between a stacked memory cell array portion and its peripheral circuit. 46. The semiconductor according to claim 45, wherein the step buffering region has a guard ring diffusion layer to which a predetermined bias voltage is applied on the surface of the semiconductor substrate. Storage device. 47, having a memory array consisting of a collection of unit memory mats each having the same size and including a sense amplifier, and providing a redundant word line and/or a redundant data line for each memory mat; , a redundancy decoder is provided, the number of which is less than the total number of redundant word lines and/or data lines constituted by all of the above memory mats and greater than the number of redundant word lines and/or data lines provided in one memory mat. A defect relief method for a semiconductor memory device, characterized in that the defect relief method is used in common for each of the memory mats or a block consisting of a plurality of the memory mats. 48. Claim 47, characterized in that the redundant decoder circuit includes a defective address storage circuit and an address comparison circuit, and is provided adjacent to the corresponding X and Y address buffers. Semiconductor storage device defect relief method. 49. At the output of the word line or column selection circuit,
A spare word line and/or a spare column selection line having wiring that intersects each of a plurality of word lines and/or column selection lines is formed, and when a defective word line and/or defective data line occurs, physical means can be used. The output line of the word line and/or column selection circuit is selected as a defective word line and/or
Alternatively, a method for relieving defects in a semiconductor memory device, which comprises disconnecting a column selection line corresponding to a defective data line and connecting it to a spare word line and/or a spare column selection line. 50. In the multi-bit simultaneous test mode with multiple column selection, only the defective data line or column selection line among the multiple selection data lines or column selection lines corresponds to the memory cell array divided into multiple memory blocks. A method for relieving defects in a semiconductor memory device, comprising switching to a redundant data line or a redundant column selection line. 51. Divide the data line into a plurality of blocks using an address signal of a specific bit among the row system and/or column system address signals, an internally formed block address, or a combination of the above address signal and block address, and divide the data line into multiple blocks. 1. A defect relief method for a semiconductor memory device, characterized in that a defective data line is switched to a redundant data line only in a block where a defect exists by using a signal specifying the redundant data line. 52. Divide the word line into multiple blocks by assigning block addresses formed in the row system and/or internally, and use the signal specifying the block to remove the defective word line only in the block where the defective word line exists. A defect relief method for a semiconductor memory device characterized by switching to a redundant word line. 53. The defect relief method for a semiconductor memory device according to claim 51 or 52, wherein the block address is specified by the same programming means as the means for programming the defective address.