KR0178886B1 - Semiconductor memory device - Google Patents

Abstract

1. A semiconductor memory device, comprising: test means for testing a semiconductor memory device and a first external terminal receiving a low address strobe signal for efficient breeding, high speed of operation, stabilization, high reliability, and high speed address access. A second external terminal receiving a column address strobe signal, a third external terminal receiving a write enable signal, a fourth external terminal receiving a power supply voltage of the semiconductor memory device, and a fifth external terminal receiving a predetermined voltage And the voltage of the second external terminal and the voltage of the third external terminal are low level at a timing of changing the voltage of the first external terminal from a high level to a low level, coupled to the test means. The test means is set to the test mode by detecting that the fifth external terminal receives a voltage greater than the absolute value of the power supply voltage. It includes a mode setting means.

By using such a semiconductor memory device, efficiency of breed development, speed of operation, stabilization, high reliability, and speed of address access can be achieved.

Description

Semiconductor memory

1 to 3 are block diagrams showing one embodiment of a dynamic RAM to which the present invention is applied.

4 is a package appearance diagram showing one embodiment of the applied dynamic RAM of the present invention.

5 and 6 are terminal arrangement diagrams showing one embodiment thereof.

7 to 11 show an external appearance of a lead frame showing one embodiment thereof.

12 is a pad arrangement diagram showing one embodiment thereof.

Fig. 13 is an overall layout showing one embodiment of the dynamic RAM to which the present invention is applied.

14 to 22 are partial or enlarged views showing one embodiment thereof.

23 and 24 are power supply trunk diagrams showing two embodiments of a dynamic RAM to which the present invention is applied.

25 to 41 are timing charts showing one embodiment of each operation cycle of the dynamic RAM to which the present invention is applied.

42 to 79 are circuit diagrams showing one embodiment of the specific circuit configuration of each part.

80 to 82 are signal waveform diagrams showing one embodiment of the applied dynamic RAM of the present invention.

83 and 84 are schematic views of the mat selection concept and the selection method.

FIG. 85 is a sectional view showing one embodiment of a wiring area of a dynamic RAM to which the present invention is applied. FIG.

86 to 88 are layout views showing one embodiment of a precharge control signal line, a monitor word line, and a sense amplifier.

89 and 90 are equivalent circuit diagrams showing some embodiments of an input protection circuit of the applied dynamic RAM of the present invention.

91 is an equivalent circuit diagram showing an example of an input protection circuit of a conventional dynamic RAM.

92 to 97 are layout views showing some embodiments of an input protection circuit of a dynamic RAM to which the present invention is applied.

FIG. 98 is a layout diagram showing an example of an input protection circuit of a conventional dynamic RAM. FIG.

99 is a layout diagram showing one embodiment of a MOSFET included in a peripheral circuit of the applied dynamic RAM of the present invention.

100 is a schematic structural diagram of one embodiment of a semiconductor device according to the present invention.

FIG. 101 is a detailed view of the embodiment shown in FIG. 100;

FIG. 102 shows details of the modification of FIG. 101; FIG.

103 is a circuit diagram of an essential part in FIG. 102;

104 is a cross-sectional view taken along the line A-A in FIG. 102;

105 is a schematic structural diagram of a semiconductor device devised by the present inventors.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective for semiconductor devices, and more particularly to a semiconductor memory device, which is particularly effective for a dynamic RAM.

For information on the dynamic random access memory (RAM) and its package type, see, for example, Hitachi Seisakusho Co., Ltd., June 1987, pages 55 to 57, and pages 14 to 14 of the Hitachi IC Memory Data Book. It is listed on page 24.

In a dynamic RAM or the like having several package specifications as described above, the lead frame for mounting a semiconductor substrate has a different optimum shape for each package type. Therefore, the bonding pads for joining these lead frames and semiconductor substrates have different optimum layout positions for each package type. As a result, it is necessary to prepare several semiconductor substrates in correspondence with the bit structure and operation mode, for example, package type, and this is one of the reasons for limiting the low cost of the dynamic RAM and the like and inhibiting efficient breeding. It was.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device such as a dynamic RAM which aims at increasing the efficiency of breed development.

It is another object of the present invention to provide an output buffer and a protection circuit aimed at speeding up or stabilizing operation, and to provide several layout methods and test methods suitable for semiconductor memory devices such as dynamic RAM.

Another object of the present invention is to reduce the cost while increasing the performance and reliability of semiconductor memory devices such as dynamic RAM.

Another object of the present invention is to provide a semiconductor device capable of speeding up address access.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

The configuration of the present application is as follows.

(1) Test means for testing a semiconductor memory device, a first external terminal receiving a low address strobe signal, a second external terminal receiving a column address strobe signal, a third external terminal receiving a write enable signal, and the semiconductor A fourth external terminal receiving a power supply voltage of a storage device, a fifth external terminal receiving a predetermined voltage, and the test means, the timing at which the voltage of the first external terminal changes from a high level to a low level; The test means is tested by detecting that the voltage of the second external terminal and the voltage of the third external terminal are both at a low level and that the voltage of the fifth external terminal is greater than the absolute value of the power supply voltage. And mode setting means for setting to.

(2) In the above (1), the sixth external terminal includes a sixth external terminal for receiving an address signal, and the sixth external terminal at a timing at which the voltage of the first external terminal changes from a high level to a low level. The type of the test mode is designated according to the voltage level.

(3) In (2), the voltage of the second external terminal is low level and the voltage of the third external terminal is high level at a timing at which the voltage of the first external terminal changes from a high level to a low level. Is detected and the test mode is canceled.

(4) In the above (2), both the voltage of the second external terminal and the voltage of the third external terminal are high level at a timing at which the voltage of the first external terminal changes from a high level to a low level. Detect and cancel the test mode.

(5) In the above (2), the sixth external terminal is a terminal for outputting or inputting data.

This makes it possible to efficiently breed varieties of semiconductor memory devices such as dynamic RAMs having multiple package specifications, reduce power supply noise, and reduce signal transmission delay time while reducing the area required for layout. It is possible to speed up and stabilize operations such as dynamic RAM. As a result, the performance and reliability of the dynamic RAM and the like can be improved, and the cost can be reduced.

In addition, the peripheral circuits are formed at the centers of the dynamic memory cell regions at both ends in the long direction on the rectangular chip, and the I / O pads and the address pads formed at both ends in the long direction of the chip are connected to each other. The dynamic memory cell region of a semiconductor device having an I / O line arranged in parallel with a word line formed in the dynamic memory cell region in the dynamic memory cell region is formed such that the word line is parallel to the long side of the chip. .

As a result, the dynamic memory cell region is formed so that the word line is parallel to the long side of the chip, so that the I / O lines arranged parallel to the word line in the dynamic memory fine region are also arranged parallel to the long side of the chip in the region. By connecting the I / O lines in the memory cell regions dividedly arranged at both ends in a straight line, the length of the chip in the I / O line is not lengthened in the short side direction of the chip of the I / O line. Even if the length is longer, the length of the I / O line can be shortened by the effect that the length of the chip in the memory cell region can be reduced to less than or equal to the length between both ends of the chip in the short-side direction.

EMBODIMENT OF THE INVENTION Hereinafter, the structure of this invention is demonstrated with an Example.

3.1. Basic composition or method and its features

3.1.1. Block composition

FIG. 1 is a block diagram of one embodiment of an input unit of a dynamic RAM to which the present invention is applied. 2 and 3 show a block of one embodiment of the memory array of the dynamic RAM, its direct peripheral circuit and the output unit, respectively. The circuit elements constituting each block in FIGS. 1 to 3 are not particularly limited, but are formed on one semiconductor substrate made of P-type single crystal silicon. Incidentally, in Figs. 1 to 3 and the following circuit diagrams, signal lines relating to input or output signals and the like are displayed starting from the bonding pads formed on the surface of the semiconductor substrate. In addition, these figures are based on the case where the dynamic RAM inputs / receives the so-called x1 bit structure which inputs / restores the stored data in units of 1 bit, and has a so-called x4 bit structure that inputs / outputs the stored data in units of 4 bits. In the case, the description is given by adding a bullet.

In Fig. 1, the dynamic RAM is not particularly limited, but a low address strobe signal serving as a start control signal in an external memory control unit or the like. , Column address strobe signal And write enable signals Output enable signal in x4 bit configuration ) Is supplied. These start control signals are generated by the timing generator circuit TG. System control circuit, RTG, System control circuit CTG and It is supplied to the system control circuit WEG and the data output control circuit OTG, respectively. On the other hand, 11 address input terminals A0 to A10 (or A0 to A9) have X address signals X0 to X10 (or X0 to X9) and Y address signals Y0 to Y10 (or 10). Y0 to Y9) are supplied time-divisionally. These address signals are supplied to corresponding unit circuits of the X address buffer XAB or the Y address buffer YAB.

As described below, the dynamic RAM of this embodiment is classified into 21 types of products according to its bit structure, operation mode, and package type, and a semiconductor substrate common to all of these product types is prepared. Therefore, some of the bonding pads provided on the surface of the semiconductor substrate are used for different purposes according to the bit structure of the dynamic RAM, and some of the bonding pads shown in Table 2 are arranged at different positions by the package type of the dynamic RAM. do. In this embodiment, the pads shown in Table 2 are each provided with several individual input buffers or unit circuits, and these input buffers or unit circuits are arranged in close proximity to the corresponding pads, respectively. Although not particularly limited, the pad ZIP for specifying the package type of the dynamic RAM and the pads FP0 and FP1 for specifying the operation mode are provided on the semiconductor substrate surface. As described below, the bonding process for these pads is selectively performed to selectively specify the package type or operation mode of the dynamic RAM. At this time, the plurality of input buffers and unit circuits are selectively enabled according to the internal signal ZIP or the inverted internal signal ZIP formed in accordance with the bonding process to the pad ZIP, whereby the corresponding bonding pads are selectively enabled. .

In FIG. 2, the dynamic RAM is not particularly limited, but includes eight memory mats MAT0 to MAT7. These memory mats include the corresponding Y address decoders YAD0 to YAD7, two memory arrays MARY00 and MARY01 to MARY70 and MARY71 disposed therebetween, and their direct peripheral circuits, respectively. In this embodiment, the memory mats MAT0 and MAT1 to MAT6 and MAT7 are not particularly limited, but are paired two by two, as can be inferred from FIG. 2, and arranged symmetrically with a corresponding X-based selection circuit therebetween. do. Each memory mat is provided with four sets of common I / O lines each for four memory errors, and is arranged to penetrate two memory mats paired with each common I / O line. In addition, these memory mats are operated at the same time in two different predetermined combinations as described below, resulting in four memory arrays being selected at the same time. A total of eight memory cells are selected at the same time, two in each of the four memory arrays to be selected, and connected to the corresponding eight sets of common I / O lines.

In FIG. 3, common I / O lines IO0L0 to IO0L3 and IO0H0 to IO0H3 to IO6L0 to IO6L3 and IO6H0 to IO6H3 coupled to memory mats MAT0 and MAT1 to MAT6 and MAT7 (here, for example, non-inverting common I / O Invert common I / O line with line IO0L0 Add together and display like common I / O line IO0L0. The same applies to the complementary signal lines hereinafter) and is also coupled to the corresponding common I / O line selection circuits IOS0 to IOS15. Eight memory cells connected to the corresponding common I / O line by the selection operation are selectively connected to the data input buffers DIB0 to DIB3 or the main amplifiers MA0 to MA7 via the corresponding common I / O line selection circuits IOS0 to IOS15. Connected. The main amplifiers MA0 to MA7 are also selectively connected to the data output buffers DOB0 to DOB3. As a result, a write or read operation to one or four memory cells to be designated is selectively executed.

The detailed structure and operation of each block of the dynamic RAM and its features will be described in detail below.

3.1.2. Product Type

Table 3 shows the product type of one embodiment of the dynamic RMA to which the present invention is applied. The dynamic RAM of this embodiment is not particularly limited, but is classified according to the bit structure, operation mode, and package type to have a total of 21 types of product types. That is, as shown in Table 3, dynamic RAMs are first classified into two types, x1 and x4 bit configurations, according to the bit configurations. Of these, x1-bit configuration is classified into three types of fast page mode, static column mode and nibble mode according to its operation mode, and x4-bit configuration is fast page mode and static column which does not have mask write mode function. It is classified into four types, a fast page mode and a static column mode having a mode and a mask write mode. The seven types of products are provided with three types of packages, DIP, SOJ and ZIP.

3.1.3. Package Type

4 shows an external view of an embodiment of a dynamic RAM to which the present invention is applied. In the dynamic RAM of this embodiment, as described above, three types of package specifications of DIP, SOJ, and ZIP are prepared, and the external appearance of each package specification is shown in FIGS. 4A to 4C, respectively. .

5 shows a terminal arrangement diagram of one embodiment of a dynamic RAM of an x1-bit configuration to which the present invention is applied. 6 shows a terminal arrangement diagram of one embodiment of a dynamic RAM of an x4 bit configuration to which the present invention is applied. In addition, Table 4 shows the names and functions of the external terminals shown in the terminal arrangement diagrams of FIGS. In addition, Table 4 shows the names and functions of the external terminals shown in the terminal arrangement diagrams of FIGS. 5 and 6, the terminal arrangement diagram seen from the top is shown for the DIP and SOJ packages of (a) and (b), and the terminal arrangement diagram is seen from the bottom for the ZIP package of Fig. (C). It is.

7 to 11 show partial plan views of lead frames used in each package specification of the dynamic RAM to which the present invention is applied. Among these, the lead frame of FIG. 7 is used for a dynamic RAM having a DIP package and has an x1 bit configuration, and the lead frame of FIG. 8 is used for a dynamic RAM having an x4 bit configuration. Similarly, the lead frame of FIG. 9 is shared by the dynamic RAM of x1 and x4 bit configuration in the SOJ package, and the lead frame of FIGS. 10 and 11 is a ZIP package and also the dynamic of x1 bit configuration and x4 bit configuration. Each type is used for RAM. In addition, in FIG. 7 thru | or 11, the front-end | tip part of each lead frame with a diagonal line has shown the bonding post for bonding a wire.

In the case of the DIP and SOJ packages as shown in Figs. 7 to 9, each lead frame extends radially toward the corresponding external terminal. However, in the case of a ZIP package, as shown in FIGS. 10 and 11, the three sides except for the upper side extend toward the external terminals disposed on one side of the package, and no bonding post is provided on the upper side.

On the other hand, Fig. 12 shows a pad arrangement diagram of one embodiment of a common semiconductor substrate of a dynamic RAM to which the present invention is applied. Table 5 shows the names and functions of the bonding pads shown in FIG. In Fig. 12, the names of pads used in the dynamic RAM of the DIP and SOJ package specifications are indicated on the inside of the dotted line, and the names of the pads used in the dynamic RAM of the ZIP package specification are described on the outside thereof. In the same figure, the right side of the semiconductor substrate surface corresponds to the upper side of the lead frame of the dynamic RAM of the ZIP package specification shown in FIGS. 10 and 11.

As described above, when the dynamic RAM is a ZIP package specification, no bonding post is provided on the upper side of the lead frame. Therefore, the pad provided on the right side of the surface of the semiconductor substrate as shown in FIG. And A6 to A9 ( ) Are pads provided on the upper and lower sides of the semiconductor substrate surface. And A6Z to A9Z ( ).

3.1.4. Breeding method

As described above, the dynamic RAMs of this embodiment are classified into a total of 21 types of products according to the bit structure, operation mode, and package type. Therefore, in this embodiment, a certain product type is selected by providing a semiconductor substrate common to all of the 21 types of product types, changing a part of the poco mask, or selectively performing bonding processing on a predetermined pad. It can be realized as an enemy. As a result, it is possible to efficiently provide the dynamic RAM having the 21 types of products based on the unique common semiconductor substrate.

(1) Switching bit configuration

In the dynamic RAM of this embodiment, as described above, two types of bit configurations, x1 and x4 bit configurations, are provided. The switching of these bit configurations must be performed in the part which determines the access time of the relatively dynamic RAM as is well known. For this reason, in the present embodiment, as described below, the switching of the bit configuration is performed in the 50th, 57th, 58th, 63th, 66th, 70th, 71th, 73th and 73th degrees. This is realized by partially changing the photomask at each connection switching point indicated in the dotted line of the circuit diagram of 75 degrees and selectively forming a joining wiring made of aluminum in the second layer.

(2) Switching of operation mode

In the dynamic RAM of this embodiment, as shown in Table 3 above, a total of seven types and substantially five types of operation modes are prepared. The switching of these operation modes can be performed at a portion which does not determine the access time of the relatively dynamic RAM as is well known. For this reason, in this embodiment, as shown in FIG. 12 and Table 5, the pads FP0 and FP1 for switching the operation mode are provided on the surface of the common semiconductor substrate, and the bonding processing for these pads is performed selectively. The operating mode of the type RAM can be selectively designated.

Table 6 shows the relationship between the bonding process for pads FP0 and FP1 and the operating mode of the dynamic RAM.

When the dynamic RAM has an x1 bit configuration, as shown in Table 6, the dynamic RAM enters the fast page mode, provided that the bonding processing for the pads FP0 and FP1 is not performed. The dynamic RAM is not particularly limited, but is in a static column mode provided that only the pad FP1 is bonded to the power supply voltage VCC of the circuit, and the nibble mode is provided on the condition that only the pad FP0 is bonded to the ground potential VSS of the circuit. .

On the other hand, in the case where the dynamic RAM has an x4 bit configuration, the dynamic RAM is not particularly limited, but in the fast page mode that does not involve the mask write mode function provided that the bonding process for the pads FP0 and FP1 is not performed. The pad FP1 is brought into the static column mode without the mask write mode function provided that the pad FP1 is bonded to the power supply voltage VCC of the circuit. In addition, the pad page mode with the mask write mode function is provided on the condition that the pad FP0 is bonded to the ground potential VSS of the circuit, and the mask write mode function is provided with the pad FP1 bonded to the power supply voltage VCC of the circuit. Static column mode is used.

Details of each operation mode will be described later in detail.

(3) switching of package specifications

The dynamic RAM of this embodiment is provided with three types of package specifications as described above, and the optimum placement positions of the bonding pads are different in the dual DIP and SOJ packages and the ZIP package. Therefore, in this embodiment, as shown in FIG. 12 and Table 5, the column address strobe signal is described. And address signals A6 to A9 (output enable signal in case of x4 bit configuration). Pads placed in positions suitable for DIP and SOJ packages with respect to pads for And A6 to A9 ( And pads placed in a suitable location for the ZIP package And A6Z to A9Z ( ) Is provided in duplicate. As described below, the timing generating circuit TG The system control circuit CTG and each address buffer (the data output control circuit OTG of the timing generation circuit TG in the case of the x4 bit configuration) are provided with an input buffer or a unit circuit corresponding to each of the pads, respectively. Is placed close to the corresponding pad. A pad ZIP for switching package specifications is also provided on the surface of the semiconductor substrate, and the above-described input buffers or unit circuits are selectively activated by selectively performing a bonding process on the pads, thereby providing a dynamic RAM. The package specification is optionally switched.

A detailed circuit configuration and operation of the input buffer and the unit circuit provided corresponding to the pad will be described in detail below.

3.1.5. Operation cycle

Table 7 shows the operation cycle of one embodiment of the dynamic RAM to which the present invention is applied. As described above, the dynamic RAM of this embodiment is classified into 21 types of products according to its bit configuration, operation mode, and package type, and is not particularly limited in each of these types of products, but is classified into 10 types as shown in Table 7. The operating cycle of is prepared. The operation cycles of claims 1 to 4 are capable of continuous operation corresponding to the operation mode of the single operation and the dynamic RAM, and the operation cycles of claims 2 to 3 can be combined with the mask write mode.

By the way, the dynamic RAM of this embodiment is not particularly limited, but has a public test mode and a private vendor test mode defined by the Joint Electron Device Engineering Council (JEDEC). The dynamic RAMs enter the open test mode or the vendor test mode by executing the corresponding set cycles, respectively, and are released from their test mode by executing the RAS only regeneration cycle of claim 5 or the CBR regeneration cycle of claim 7. . Details of each test mode are described below.

25 to 41 show timing charts for defining input conditions of some representative operation cycles of the operation cycles shown in Table 7. As shown in FIG. Based on these drawings, an outline of some typical operation cycles of the dynamic RAM of this embodiment will be described.

(1) lead cycle

The dynamic RAM has a column address strobe signal as shown in FIG. Enable signal at falling edge of The lead cycle is provided on the condition that is a high level. Low address strobe signal is applied to the address input terminals A0 to A10 (or A0 to A9 for the x4 bit configuration). The X address signals X0 to X10 (X0 to X9 in the case of the x4 bit configuration) of 11 bits (10 bits in the case of the x4 bit configuration) are supplied in synchronization with the falling edge of the column address strobe signal. The Y address signals Y0 to Y10 (Y0 to Y9 in the case of the x4 bit configuration) are supplied in synchronization with the falling edge of. The data output terminal Dout (data input / output terminals I / O1 to I / O4 in the case of the x4 bit configuration) is normally in a high impedance state, and read data of a specified address is output when a predetermined access time has elapsed. At this time, in the case of x-bit configuration, the output enable signal It is a requirement to be low level.

(2) early light cycle

The dynamic RAM has a column address strobe signal as shown in FIG. Enable signal at falling edge of The early light cycle is provided on the condition that is low level. The X address signal and the Y address signal are input under the same conditions as the read cycle. In addition, the column address strobe signal is applied to the data input terminal Din (data input / output terminals I / O1 to I / O4 in the case of the x4 bit configuration). The write data is supplied in synchronization with the falling edge of.

(3) delay light cycle

Dynamic RAM is a column address strobe signal as shown in FIG. Since the write enable signal WE is at the high level at the falling edge of, the column address selection operation that is the same as the read cycle is started. The signal is then delayed slightly to enable the write enable signal. The write operation is executed by temporarily lowering the level. Write enable signal to data input terminal Din (or data I / O terminals I / O1 to I / O4) The write data is supplied in synchronization with the falling edge of. At this time, in case of x4 bit configuration, output enable signal Condition is to be at a high level.

(4) lead modification light cycle

This operation cycle, that is, an operation cycle combining the read cycle and the delay write cycle, and the dynamic RAM shows the column address strobe signal as shown in FIG. Enable signal at falling edge of Since is high level, the read cycle is first started. Then, the read data of the designated address is output from the data output terminal Dout (or data input / output terminals I / O1 to I / O4), and the write enable signal is output. The write data supplied from the data input terminal Din (or the data input / output terminals I / O1 to I / O4) is written to the address at the time when the level becomes low level temporarily.

(5) mask light cycle

In the dynamic RAM, as shown in FIG. 29, the write enable signal WE is a low address strobe signal. So-called WBR which becomes low level before before Cycle) to enter the mask write mode, and then the column address strobe signal. And light enable signals The early write cycle, delayed write cycle, or read modification write cycle are selectively executed according to the combination of. Low address strobe signal to data I / O terminals I / O1 to I / O4 first 4 bits of mask data are supplied in synchronization with the falling edge of the Fall or light enable signal for The write data of 4 bits is supplied in synchronization with the second falling edge of?. These write data are selectively written on the condition that the corresponding mask data is logical zero.

(6) FP lead cycle

In the dynamic RAM in fast page mode, as shown in FIG. 30, the low address strobe signal is shown. Column address strobe signal when is set to low level By repeatedly turning to low level, the fast continuous read operation in the fast page mode is executed. The low address strobe signal is first applied to the address input terminals A0 to A10 (or A0 to A9). The X address signals X0 to X10 (or X0 to X9) are supplied in synchronization with the falling edge of C, and the column address strobe signal is subsequently supplied. The Y address signals Y0 to Y10 (or Y0 to Y9) are repeatedly supplied in synchronization with the falling edge of. Column address strobe signal Enable signal at each falling edge of Becomes a high level. In dynamic RAM, the first low address strobe signal The word line designated as the X address signal is alternatively selected at the falling down of the column address strobe signal. The read data of one or four memory cells designated by the Y address signal among the memory cells coupled to the word line selected in each drop of is sequentially output.

(7) FP light cycle

Column address strobe signal as shown in FIG. 31 for dynamic RAM in fast page mode Enable signal at each falling edge of Is lowered, the dynamic RAM executes the fast continuous write operation by the early write cycle in the fast page mode. At this time, the column address strobe signal is applied to the data input terminal Din (or the data input terminals I / O1 to I / O4). A series of write data is supplied sequentially in synchronization with each falling edge of. Light enable signal Column address strobe signal In the case where the delay is lowered at each falling level, the dynamic RAM selectively executes a delay write cycle or a read correction write cycle in the fast page mode.

(8) SC lead cycle

In the dynamic RAM in the static column mode, as shown in FIG. 32, the low address strobe signal is shown. And column address strobe signal When the Y address signals Y0 to Y10 (or Y0 to Y9) supplied to the address input terminals A0 to A10 (or A0 to A9) are changed while the low level is set, the high-speed continuous read by the read cycle in the static column mode The action is executed. The dynamic RAM includes an address transition detection circuit ATD and the output signal of the address transition detection circuit ATD becomes effective because the Y address signal is changed even by one bit. Dynamic RAM is the first low address strobe signal. In synchronism with the falling edge of, the X address signals X0 to X10 (or X0 to X9) supplied via the address input terminal are fetched, and the corresponding word line is alternatively selected. When the output signal of the address transition detection circuit ATD becomes valid, read data of one or four memory cells designated by a new Y address signal among memory cells coupled to the selected word line are sequentially output.

(9) SC light cycle

In the dynamic RAM in the static column mode, as shown in FIG. 33, the write enable signal is shown. By repeatedly changing to a low level, the high speed continuous write operation by the write cycle of the static column mode is executed. At this time, the write enable signal is applied to the data input terminal Din (or the data input / output terminals I / O1 to I / O4). A series of write data is supplied sequentially in synchronization with each falling edge of. Light enable signal To remain at the low level, and the column address strobe signal By repeatedly changing to low level, the dynamic RAM executes write cycles in the same static column mode.

(10) NB lead cycles

In the dynamic RAM in nibble mode, as shown in FIG. 34, the low address strobe signal is shown. Column address strobe signal when is set to low level By repeatedly going to the low level, the 4-bit high speed continuous read operation by the nibble mode read cycle is executed. The low address strobe signal is first applied to the address input terminals A0 to A10 (or A0 to A9). The X address signals X0 to X10 which designate the low address signal in synchronization with the falling edge of are supplied, followed by the column address strobe signal. The Y address signals Y0 to Y10 which designate the leading column address in synchronization with the falling edge of are supplied. Column address strobe signal Enable signal at each falling edge of Becomes a high level. In dynamic RAM, the first low address strobe signal The word line designated by the X address signal is selected at the falling edge of the column, and the column address strobe signal is selected. In each drop of the read data of four memory cells to which the address consecutive to the head of the memory cell designated by the head column address is assigned is sequentially output.

(11) NB light cycle

In the dynamic RAM in nibble mode, as shown in FIG. 35, the column address strobe signal is shown. Enable signal at each falling edge of Is lower level, the dynamic RAM executes the 4-bit high-speed continuous write operation by the early write cycle in nibble mode. At this time, the column address strobe signal is applied to the data input terminal Din (or the data input / output terminals I / O1 to I / O4). A series of write data is supplied sequentially in synchronization with each falling edge of. Light enable signal Column address strobe signal In the case where the delay is lowered at each fall of the signal, the dynamic RAM selectively executes a delay write cycle or a read correction write cycle in the fast page mode.

(12) Only play cycle

The dynamic RAM has a column address strobe signal as shown in FIG. And light enable signals Becomes high level and only the low address strobe signal RAS becomes low level. Executes only replay cycle. Low address strobe signal is applied to the address input terminals A0 to A10 (or A0 to A9). A reproducing address, i.e., X address signals X0 to X9, for specifying a word line to be reproduced in synchronization with the falling edge of is supplied.

(13) hidden regeneration cycles

As shown in FIG. 37, the dynamic RAM uses a column address strobe signal after normal memory access ends. Address strobe signal when is set to low level Is changed back to the low level to execute the hidden regeneration cycle. The low address signal specifying the word line to be reproduced in this hidden reproduction cycle is supplied from the reproduction counter RFC. The hidden regeneration cycle is equivalent to the case where the CBR regeneration cycle described in the next section is executed following the normal memory access.

(14) CBR regeneration cycle

The dynamic RAM has a low address strobe signal as shown in FIG. Column address strobe signal before Becomes the low level, so-called CBR ( before Cycle) to execute the CBR regeneration cycle. At this time, the write enable signal Needs to be at a high level, and the low address of the word line to be reproduced is supplied from the reproduction counter RFC.

(15) counter test cycle

In the dynamic RAM, as shown in FIG. 39, after the CBR regeneration cycle of the preceding paragraph is completed, the column address strobe signal is used. Is again at the low level to execute the counter test cycle. The column address strobe signal after the second time to the address input terminals A0 to A10 (or A0 to A9). The Y address signals Y0 to Y10 (or Y0 to Y9) are supplied in synchronization with the falling edge of. This makes it possible to selectively perform a read or write test on the memory cells coupled to the word lines selected in the CBR regeneration cycle.

(16) public test mode set cycle

The dynamic RAM has a low address strobe signal as shown in FIG. Column address strobe signal before And light enable signals Is the low level, so-called WCBR ( · before ) Cycles into the open test mode.

Dynamic RAM The release from this open test mode is effected by the execution of only regeneration cycles or CBR regeneration cycles.

(17) Vendor Test Mode Set Cycles

In the dynamic RAM, as shown in FIG. 41, a high voltage SVC of 10 V, for example, higher than the power supply voltage of the circuit is supplied to the data output terminal Dout (data input / output terminal I / O3 in the case of x4 bit configuration). The WCBR cycle is used to enter the vendor test mode. Address input terminals A0 to A9 and A10 (output enable signal with x4 bit configuration) Low address strobe signal The test mode setting signal for specifying the content of the vendor test mode is supplied in synchronization with the falling edge of.

Dynamic RAM Above This vendor releases the test mode by executing only a regeneration cycle or a CBR regeneration cycle.

3.1.6. Test method

The dynamic RAM of this embodiment has an open test mode defined by JEDEC and an original vendor test mode as described above. These test modes can be carried out after the package is sealed via an external terminal of the dynamic RAM. Dynamic RAM also has several test pads for performing several probe tests at the wafer level.

(1) open test mode

The dynamic RAM of this embodiment has a low address strobe signal as described above. Column address strobe signal before And light enable signals When the so-called WCBR cycle is executed, which becomes low level, the test mode is opened.

When the read cycle is executed in this open test mode, a total of 8 bits of stored data are simultaneously read and combined in each of two bits in four memory arrays simultaneously selected in the dynamic RAM. As a result, if these data are all bits matched, a high level output signal is sent from the data output terminal Dout, and if there is a mismatch, a low level output signal is sent out. In the case where the dynamic RAM has an x4 bit configuration, the output signals transmitted from the data input / output terminals I / O1 to I / O4 can be matched to the combination result of the corresponding 2-bit stored data, respectively.

Dynamic RAM is released from the open test mode by executing a RAS only refresh cycle or a CBR refresh cycle as described above.

This open test mode allows the user of the dynamic RAM to efficiently test the normality of a series of memory regions.

(2) vendor test mode

In the dynamic RAM of this embodiment, as described above, the high voltage SVC higher than the power supply voltage of the circuit is supplied to the data output terminal Dout (data input / output terminal I / O3 in the case of the x4 bit configuration) and the WCBR cycle is executed. To enter the vendor test mode. At this time, address input terminals A0 to A9 and A10 (output enable signal in case of x4 bit configuration) Low address strobe signal The test mode setting signal is supplied in synchronization with the falling edge of, thereby specifying the details of the vendor test mode.

Table 8 shows the specific test mode provided as the vendor test mode of the dynamic RAM of this embodiment. In addition, as shown in Table 8, the test mode setting signal supplied as the address signals A3 to A8 is not used in the present state, and becomes money care.

In Table 8, the dynamic RAM enters the binary mode by first turning the tenth bit of the test mode setting signal supplied as the address signal A9 to logic 0 and the other bits to logic 1. At this time, when the read cycle is executed, the dynamic RAM executes the same 8-bit read combination test as the open test mode.

Next, when the tenth bit of the test mode setting signal becomes logic 1 again, the dynamic RAM is in ternary mode. At this time, when the read cycle is executed, the dynamic RAM similarly executes an 8-bit read combination test. As a result, if all the bits of the read data (corresponding 2 bits in the case of the x4 bit configuration) coincide with logic 0 or logic 1, the data output terminals Dout (or data input / output terminals I / O1 to I / O4) correspond. Outputs high or low level output signals. If the read data do not match, the output of the data output terminal Dout (or the corresponding data input / output terminals I / O1 to I / O4) is in a high impedance state.

In the dynamic RAM, the third and eleventh bits of the test mode setting signal supplied as the address signals A2 and A10 become logic 1, and the other bits become logic 0 to enter the first VPL stress mode. Then, the second bit of the test mode setting signal supplied as the address signal A1 instead of the third bit becomes logic 1, thereby entering the second VPL stress mode. Further, the second and third bits of the test mode setting signal supplied as the address signals A1 and A2 become logic 1, and the other bits become logic 0, thereby entering the VBB stop mode. In these test modes, the operation of the voltage generators VG1 and VG2 having the relatively large current supply capability of the built-in voltage generator HVC or the substrate back bias voltage generator VBBG is substantially stopped in the dynamic RAM. In the first and second VPL stress modes, the plate voltage VPL is selectively fixed to the ground potential of the circuit or the power supply voltage VCC. As a result, the functional test of the memory cell in the VPL stress state can be performed after the package is sealed, and the normality check test of the internal circuit can be performed by the micro current measurement.

(3) probe test

Table 9 shows test pads for probe testing provided in the dynamic RAM of this embodiment. These test pads are used, for example, in probe tests performed at the wafer stage of a dynamic RAM, and have no meaning after package encapsulation.

Although the pad ICT in Table 9 is not particularly limited, as described below, the pad ICT has a function of completely stopping the operation of the reference potential generating circuit VL and the substrate back bias voltage generating circuit VBBG by supplying the supply voltage VCC. As a result, the standby current of the dynamic RAM is stopped. At this time, the dynamic RAM can supply an arbitrary substrate back bias voltage VBB through the pad VBB, so that it is possible to test and confirm the substrate back bias voltage dependence of the internal circuit and to stop the standby current. The internal circuits can be tested for normality.

Next, the pad VPLG has a function of substantially stopping the operation of the voltage generating circuit HVC by supplying the power supply voltage VCC as described below. At this time, since the plate RAM VPL can be supplied to the dynamic RAM via the pad VPL, the plate voltage dependency of the memory cell can be tested and confirmed.

On the other hand, the pad FCK serves to enable fuse inspection of the redundant circuit by supplying the power supply voltage VCC as described below. In the dynamic RAM of this embodiment, four redundant word lines and redundant data lines are provided, respectively, as described below. Four redundant X and redundant redundant circuits correspond to these redundant word lines and redundant data lines, respectively. Is prepared. These X redundant circuits and Y redundant circuits each consist of one enable circuit and eight address comparison circuits each including a fuse. Therefore, at the time when the power supply voltage VCC is supplied to the pad FCK, a selection signal for alternatively designating the X- or Y-based redundancy circuit is supplied as the X address signals X5 to X8 or the Y address signals Y2 to Y5, respectively. A selection signal for alternatively designating the enable circuit or the address comparison circuit of the redundant circuit is supplied as the X address signal X0 or X1 to X8 or the X address signal X4 or Y address signal Y1 to Y8. At this time, a power supply voltage for fuse inspection is supplied to the pad VCF, and the current value flowing through one selected fuse at this power supply voltage is measured. For example, the disconnection or partial disconnection of the fuse can be tested and confirmed. have.

In addition, the pad RCK serves to force each redundant circuit to a selected state by supplying a power supply voltage VCC as described below. This allows the redundant word line or redundant data line to be selectively selected before redundancy relief is performed, and its normality can be tested and confirmed.

The detailed configuration and operation of the test mode control circuit will be described in detail below.

3.1.7. Basic layout

FIG. 13 is a layout view of one embodiment of a common semiconductor substrate surface of a dynamic RAM to which the present invention is applied. In addition, in the following description, the left side of the semiconductor substrate surface of FIG. 13 is called the upper side of the semiconductor substrate surface, and the right side is called the lower side thereof. In addition, according to this, the upper side of the semiconductor substrate surface of FIG. 13 is called the right side of the semiconductor substrate surface, and the lower side is called the left side. The center line parallel to the long side of the semiconductor substrate surface is called the longitudinal center line, and the center line parallel to the short side is called the horizontal center line.

In FIG. 13, the dynamic RAM of this embodiment includes eight memory mats MAT0 to MAT7 as described above. Of these, the four memory mats MAT0, MAT2, MAT4 and MAT6 are not particularly limited, but are disposed below the middle side peripheral circuit, part of the peripheral circuit arranged along the horizontal center line of the semiconductor substrate, and on the outside of the semiconductor mat. Another part of the peripheral circuit, that is, the lower side peripheral circuit, is disposed along the lower side of the substrate surface. On the other hand, the remaining four memory mats MAT1, MAT3, MAT5 and MAT7 are arranged on the upper side of the peripheral circuit of the middle side, the other side of the peripheral circuit, that is, the upper side peripheral circuit is disposed along the upper side of the semiconductor substrate surface. Another part of the peripheral circuit, that is, the central peripheral circuit, is disposed between the memory mats MAT3 and MAT5 and between MAT2 and MAT4, respectively.

The memory mats MAT0 to MAT7 include Y address decoders YAD0 to YAD7 and a pair of memory arrays MARY00 and MARY01 to MARY70 and MARY71 arranged with these Y address decoders, respectively. These memory arrays adopt a divided word line method as described below, each word line starting from a word line driver circuit included in a peripheral circuit of the intermediate side, and facing each short side of the semiconductor substrate surface. It is arranged so-called vertically. As a result, the arrangement of the X-based selection circuit which determines the access time is optimized, and the operation of the dynamic RAM is speeded up.

FIG. 14 and FIG. 15 show the layout of one embodiment of the upper side of the semiconductor substrate surface, that is, the upper side peripheral circuit in FIG. 13, and the enlarged layout of the upper side peripheral circuit of FIG.

Although not particularly limited to the upper left corner of the semiconductor substrate surface in FIG. Is placed on the bottom of the pad Also, on the right side, pads ICT, Din (I / O2 in the case of x4 bit configuration), I / O1, VBB, VSS1 and VSS2 are disposed, respectively. Corresponding input protection circuits are disposed around these pads, respectively. In addition, pad A portion of the substrate back bias voltage generation circuit VBBG is disposed between the and ICTs, and corresponding data output buffers DOB2 and DOB1 are disposed between the pads Din (or I / O2) and I / O1. Corresponding common I / O line selection circuits IOS0 to IOS7 and sense amplifier driving circuits are disposed above the memory mats MAT1 and MAT3, and main amplifiers MA0 to MA3 and between these circuits and the pads. And System control circuits are arranged.

Next, although not particularly limited to the upper right corner of the semiconductor substrate surface in FIG. 15, the pad A9Z (x4 bit configuration) ) Is placed on the bottom of the pad In addition, the left side is pad , Dout (I / O3 in the case of a x4 bit configuration), I / O4, FP0 and VSS3 are disposed, respectively. A corresponding input protection circuit is arranged around these pads. In addition, pad A9Z (or The corresponding unit circuits of the X address buffer XAB and the Y address buffer YAB are arranged close to the " Again, Pat And another portion of the substrate back bias voltage generation circuit VBBG is disposed between Dout (or I / O3), and corresponding data output buffers DOB3 and DOB4 are disposed between the pads Dout (or I / O3) and I / O4. Corresponding common I / O line selection circuits IOS8 to IOS15 and sense amplifier drive circuits are disposed above the memory mats MAT5 and MAT7, and main amplifiers MA4 to MA7 and these pads are disposed between the circuits and the pads. System control circuits are arranged.

In this embodiment, the layout area of each peripheral circuit of the dynamic RAM is classified into a device area provided in a band shape and a wiring area provided between these device areas as typically shown in the enlarged layout of FIG. Among them, circuit elements such as MOSFETs (insulated gate type deployment effect transistors) constituting each peripheral circuit are formed in the element region, and signal lines for coupling between these circuit elements are formed in the wiring region. As a result, the layout design of the peripheral circuit composed of the random logic circuit becomes efficient.

By the way, although it does not restrict | limit especially in the wiring area of FIG. 16, For example, the two-layer metal wiring layer which consists of aluminum or an aluminum alloy is used. Of these, the second aluminum wiring layer A12 provided in the upper layer is formed with a larger film thickness than the first aluminum wiring layer A11 provided in the lower layer as shown in FIG. Therefore, in this dynamic RAM, the second aluminum wiring layer A12 is used as a main signal line for coupling between circuit elements, and the first aluminum wiring layer A11 is used in correspondence with the circuit elements formed in the element region. It is used as an outgoing signal line for joining arc lines. As a result, it is possible to suppress the resistance value of the main signal lines arranged over a relatively long distance, shorten the signal propagation delay time, and promote the speed of the dynamic RAM.

On the other hand, each peripheral circuit of the dynamic RAM has a signal transmission path formed by combining a CMOS (complementary MOSFET) logic gate circuit, for example, as shown in Fig. 99A. In this embodiment, the gate electrodes of MOSFETs Q1 to Q6 constituting the CMOS logic gate circuit are substantially between source regions S1 to S6 and drain regions D1 to D6, i.e., channel phases, as shown in FIG. And the gate layers G1 to G6 provided with a predetermined insulating film interposed therebetween, and these gate layers are not particularly limited, but are formed of a polysilicon layer (poly si) having a relatively high resistance value. Accordingly, the aluminum wiring layer A11 which transmits the input signal corresponding to the gate layers G1 to G6 of each MOSFET is not particularly limited, but is divided through two contacts C1 and C2, which are branched and provided on the outer side of each gate. To the gate layer G1 or the like. As a result, the propagation delay time of the input signal to each gate layer is substantially reduced, thereby speeding up the operation of each MOSFET and further, the peripheral circuit.

17 and 18 show an arrangement of one embodiment of the peripheral circuits around the mid-side of the semiconductor substrate surface of FIG.

Although not particularly limited to the left end of the center portion of the semiconductor substrate surface in FIG. 17, pads A10 (A9 in the case of x4 bit configuration) and A0 are disposed. A corresponding input protection circuit is arranged around these pads. In addition, the positions adjacent to these pads are arranged so that the corresponding unit circuits of the Y address buffer YAB and the address transition detection circuit ATD and the X address buffer XAB are substantially symmetrical with the horizontal center line of the semiconductor substrate surface interposed therebetween. On the right side of these unit circuits, corresponding unit circuits such as the X predecoder PXAD and the X-based long-circuit circuit XRC are similarly arranged to be substantially symmetrical with the horizontal center line of the semiconductor substrate surface interposed therebetween.

However, in the dynamic RAM of this embodiment, as described below, four sets of common I / O lines are provided corresponding to each memory array, and these common I / O lines are symmetric with the horizontal center line of the semiconductor substrate surface interposed therebetween. It penetrates through two memory arrays arranged as a penetrator. The inverted and non-inverted signal lines constituting each common I / O line are crossed and equalized at approximately the center of the semiconductor substrate surface as described below. For this reason, as shown in FIG. 17, the common I / O line equalization circuits IOEQ0 and IOEQ1 provided corresponding to the memory mats MATO and MAT1, MAT2 and MAT3 are on the extension line of the corresponding common I / O line in the peripheral circuit. Each is arranged.

Meanwhile, although not particularly limited to the right end of the center portion of the semiconductor substrate surface in FIG. 18, the pad A9 (x4 bit configuration) is used. ) And A8 are prepared. A corresponding input protection circuit is arranged around these pads. In addition, the positions adjacent to these pads are arranged such that the corresponding unit circuits of the Y address buffer YAB and the address transition detection circuit ATD and the X address buffer XAB are substantially symmetrical with the horizontal center line of the semiconductor substrate surface interposed therebetween. On the left side of these unit circuits, corresponding unit circuits such as X predecoder PXAD and X redundant circuit XRC are similarly arranged to be substantially symmetrical with the horizontal center line of the semiconductor substrate surface interposed therebetween. On the extension line of each common I / O line, the common I / O line equalization circuits IOEQ2 and IOEQ3 provided corresponding to the memory mats AMT4 and MAT5 and MAT6 and MAT7 are disposed, respectively.

As such, the X predeco constituting the intermediate side peripheral circuits are arranged symmetrically with unit circuits such as PXAD and X-based redundant circuits XRC across the horizontal center line of the semiconductor substrate to improve the efficiency of layout and layout design. Can be planned.

19 and 20 show a layout of one embodiment of the lower side of the semiconductor substrate surface of FIG. 13, that is, the peripheral circuit of the lower side. 21 shows a partially enlarged arrangement of the peripheral circuit of the lower side of FIG.

Although not particularly limited, the pad A2 is disposed at the lower left end of the surface of the semiconductor substrate in FIG. 19, the pad A1 is disposed on the upper side, and the pads A3, FCK, RCK, VCF, VPLG, VPL, ZIP, FP1, VCC1 and VCC2 are arranged. A corresponding input protection circuit is arranged around these pads. In addition, corresponding unit circuits of the X address buffer XAB, the Y address buffer YAB and the address transition detection circuit ATD are arranged at positions close to the pads A1 to A3. Further, a part of the Y predecoder PYAD and the Y-based redundant circuit YRC is disposed between these pads and the memory mats MAT0 and MAT2.

On the other hand, in Fig. 20, although not particularly limited, the pad A6 is disposed at the lower right end of the semiconductor substrate surface, the pad A7 is disposed above the pads, and the pads A8Z, A7Z, A6Z, A5 and A4 are disposed on the left side thereof. A corresponding input protection circuit is arranged around these pads. In addition, corresponding unit circuits of the X address buffer XAB, the Y address buffer YAB, and the address transition detection circuit ATD are arranged at positions close to these pads. Further, between the pad and the memory mats MAT4 and MAT6, other parts such as the X predecoder PXAD and the Y predecoder PYAD are disposed.

In this embodiment, each unit circuit of the X address buffer XAB, the Y address buffer YAB, and the address transition detection circuit ATD is disposed at a position close to the corresponding bonding pad as described above. In addition, the unit circuit of the double Y address buffer YAB is basically disposed at a position closer to the corresponding pad than the corresponding unit circuit of the X address buffer XAB. As is well known, in a dynamic RAM or the like employing the address multiplex method, the access time is determined by the propagation delay time of the Y address signal supplied later. In this embodiment, since the unit circuits of the Y address buffer YAB are arranged closer to the corresponding pads, the transfer delay time of the Y address signal is reduced, and the dynamic RAM can be speeded up. In addition, by disposing each unit circuit of the address transition detection circuit ATD in a position close to the corresponding pad, the overall transfer delay time of the address transition detection circuit ATD is reduced and the dynamic RAM in the static column mode The operation speeds up.

3.1.8. Power supply method

FIG. 23 shows a power supply main diagram of an embodiment of a dynamic RAM to which the present invention is applied. In the dynamic RAM of this embodiment, as described above, the power supply voltage VCC and the ground potential VSS of a circuit having + 5V as the center voltage are supplied as the operating power supply, and the two-layer metal wiring layer whose power supply voltages are made of aluminum or aluminum alloy. It is supplied to each circuit via. In FIG. 23, the power supply mains for supplying the power supply voltage VCC of the circuit is indicated by a dashed line, and the power supply mains for supplying the ground potential VSS of the circuit is indicated by the solid line. In addition, in each power supply trunk, what is called a double supply line which uses the 1st aluminum layer A11 and the 2nd aluminum layer A12 in parallel, respectively, is represented by a thick line.

In FIG. 23, as described above, the eight types of memory mats MAT0 to MAT7, which are divided by the vertical center line and the horizontal center line (straight line) of the semiconductor substrate surface and a part thereof are disposed along the two center lines. A peripheral portion is provided on the outside of the memory mat so as to be parallel to the short side of the surface of the semiconductor substrate. Therefore, in this embodiment, six power supply voltage supply lines SVCC21 to SVC26 and four ground potential supply lines SVSS21 to SVSS24 (second power supply line) that are parallel to each other along the horizontal center line of the semiconductor substrate surface are first provided. Three voltage supply lines SVCC31 to SVC33 and ground potential supply lines SVSS31 to SVSS33 (third power supply line) and two supply voltage supply lines SVSS41 to SVSS42 and ground potential supply lines SVSS41 to SVSS42 respectively according to each short side of the semiconductor substrate surface. 4 power supply line) is provided. These power supply voltage supply lines and ground potential supply lines are commonly coupled via two power supply voltage supply lines SVCC11 and SVCC12 and ground potential supply lines SVSS11 and SVSS12 (first power supply line) arranged along the longitudinal center line of the semiconductor substrate surface.

In this embodiment, the power supply voltage supply lines SVCC11 and SVCC12 are coupled to a pad VCC2 disposed closest to the intersection with the power supply voltage supply lines SVCC41 to SVVC42, and the ground potential supply lines SVSS11 and SVSS12 are connected to the ground potential supply lines SVSS31 to SVSS33. It is coupled to the pad VSS2 disposed closest to the intersection. These power supply voltage supply lines, SVCC11 and SVCC12, and ground potential supply lines SVSS11 and SVSS12 are so-called double supply lines, most of which are used by combining two layers of aluminum wiring layers A11 and A12 in parallel, as shown in bold lines in FIG. do. As a result, the overall impedance of these power supply trunks is reduced, thereby suppressing power supply noise, so that the operation of the dynamic RAM is stabilized and speeded up.

The dynamic RAM of this embodiment, however, is provided with two pads VCC1 and VCC2 for supplying the power supply voltage of the circuit and three pads VSS1 to VSS3 for supplying the ground potential of the circuit. Of these, the pad VCC2 is coupled to the power supply voltage supply lines SVCC11 and SVCC12, and the pad VSS2 is coupled to the ground potential supply lines SVSS11 and SVSS12. In this embodiment, the remaining pads VCC1 are coupled to the power supply voltage supply lines SVCC71 and SVCC72 for supplying the power supply voltage of the circuit to the data output buffers DOB0 to DOB3 as shown in FIG. 23, and the pads VSS1 and VSS3 are connected to the data output buffer. It is coupled to ground potential supply lines SVSS71 and SVSS72 for supplying the ground potential of the circuit to DOB0 to DOB3, respectively. In other words, the power supply trunk for intermittently supplying a relatively large operating current to the data output buffers DOB0 to DOB3 is provided separately from the power supply trunk for parts of the pad and bonding wires and other general peripheral circuits. As a result, power supply noise caused by simultaneous operation of the data output buffers DOB0 to DOB3 can be suppressed to further stabilize the operation of the dynamic RAM.

Figure 24 shows a power supply trunk diagram of another embodiment of a dynamic RAM to which the present invention is applied.

In FIG. 24, the power supply line SVCC5 and the ground potential supply line SVSS5 (fifth power supply line) are arranged on the semiconductor substrate surface of the dynamic RAM in accordance with the long side of the semiconductor substrate surface in FIG. ) And a power supply voltage supply line SVCC6 and a ground potential supply line SVSS6 (sixth power supply line). These power supply voltage supply lines and ground potential supply lines are respectively coupled to the corresponding pads VCC2 or VSS2 at one end thereof, and the power supply voltage supply lines SVCC21 to SVC26 to SVCC41 and SVCC42 or ground potential supply lines SVSS21 to SVSS24 to SVSS41 and SVSS42. Is coupled to the other end. As a result, the power supply line of the dynamic RAM becomes more low-impedance, making its operation more stable.

3.1.9. Address structure and selection method

FIG. 83 is a conceptual diagram for explaining the address structure of the dynamic RAM to which the present invention is applied. FIG. 84 is a conceptual diagram for explaining the array configuration, redundant configuration and selection method of the dynamic RAM.

The dynamic RAM of this embodiment has eight memory mats MAT0 to MAT7 each comprising two pairs of memory arrays MARY00 and MARY01 to MARY70 and MARY71 and their direct peripheral circuits as described above. The two memory arrays constituting each memory mat are not particularly limited, but 256 word lines W0 to W255 and four redundant words are arranged parallel to the vertical direction as representatively showing the memory arrays MARY00 and MARY01 of FIG. 1024 sets of complementary data lines D0 to D1023 and 16 sets of redundant complementary data lines DR00 to DR03 to DR30 to DR33 parallel to the lines WR0 to WR3 and the horizontal direction, and a plurality of grid lines arranged at the intersections of these word lines and the complementary data lines Each of the dynamic memory cells is included. As described below, the word lines and the complementary data lines constituting each memory array are divided into groups of four or four sets, and the units of the X address decoder XAD or the Y address decoder YAD are grouped by these word line groups or the complementary data line groups. The circuit is ready.

In this embodiment, the memory mats MAT0 to MAT7 are paired with a combination of the memory mats MAT0 and MAT1, MAT2 and MAT3, MAT4 and MAT5 or MAT6 and MAT7 as described above, respectively, with corresponding X address decoders interposed therebetween. It is arranged symmetrically. Each of these memory mats is provided with eight sets of common I / O lines. Four sets of common I / O lines are arranged to pass through the corresponding memory arrays MARY00 and MARY10 to MARY60 and MARY70 on the left side, and the remaining four sets of common I / O lines are corresponding to the memory arrays MARY01 and MARY11 to MARY61 and It is arranged to penetrate MARY71 respectively. That is, the dynamic RAM of this embodiment is provided with a total of 32 sets of common I / O lines, and these common I / O lines are coupled to the common I / O line selection circuits IOS0 to IOS15 corresponding to each of 2 sets. The input / output terminals of these common I / O line selection circuits are also commonly coupled in pairs and then coupled to the corresponding main amplifiers MA0 to MA7. As a result, eight sets of common I / O lines are selectively connected to the main amplifiers MA0 to MA7.

The memory mats MAT0 to MAT7 are not particularly limited, but are selected simultaneously by two of each of the combinations of the memory mats MAT0 and MAT4, MAT1 and MAT5, MAT2 and MAT6 or MAT3 and MAT7 as exemplified by the diagonal lines in FIG. As a result, the corresponding four memory arrays are simultaneously selected. A total of eight sets of complementary data lines are simultaneously selected in two sets of these memory arrays, respectively, and are connected to the main amplifiers MA0 to MA7 via corresponding two sets of eight sets of common I / O lines. As a result, a substantial address space of each memory array has 256 addresses of row addresses and 512 addresses of column addresses. The row address space of each memory array is alternatively designated by the corresponding X address decoders XAD00 and XAD01 to XAD70 and XAD71, and the column address space is alternatively designated by the corresponding Y address decoders YAD0 to YAD7.

In FIG. 84, the X address signals X0 to X10 (or X0 to X9) and the Y address signals Y0 to Y10 (or Y0 to Y) supplied time-divisionally through the address input terminals A0 to A10 (A0 to A9 in the case of the x4 bit configuration). Y9) is fetched and held in the corresponding X address buffer XAB and Y address buffer YAB, respectively, in accordance with the latch timing signal XL or YL. As a result, the complementary internal address signals BX0 to BX10 are formed corresponding to the X address signals X0 to X10, and the internal address signals CY0 to CY10 are formed corresponding to the Y address signals Y0 to Y10. The complementary internal address signal AY9C is formed corresponding to the Y address signal Y9, and the internal address signals BY1 to BY8 are formed by gate controlling the internal address signals CY1 to CY8 according to the timing signal RG.

The complementary internal address signals BX0 and BX9 are not particularly limited but are supplied to the mat selection circuit MS and the X decoder control circuit XDGB. The complementary internal address signal AY9C is also supplied to the X decoder control circuit XDGB. The mat selection circuit MS alternatively forms mat selection signals MS0 to MS3 based on the complementary internal address signals BX0 and BX9. These mat selection signals are used to simultaneously select two memory mats MAT0 to MAT7. On the other hand, the X decoder control circuit XDGB inverts the selection signal based on the internal signal address signals BX0 and BX9. of And And And or And Are optionally formed in combination with each other. Further, the complementary internal address signals AY9C are selectively formed by complementary selection signals Y0 and Y1. Dual Invert Select Signal Are supplied to the corresponding X address decoders XAD00 and XAD01 to XAD70 and XAD71, respectively, and are used to selectively put these X address decoders in an operational state. The complementary selection signals Y0 and Y1 are supplied to the Y address decoders YAD0 to YAD7, and are used to selectively specify two sets of complementary data lines from four sets of complementary data lines in the selected complementary data line group. As a result, the X address signals X0 and X9 are used to selectively specify two of the memory mats MAT0 to MAT7 as shown in FIG. 83, and the Y address signal Y9 is provided in four sets corresponding to each memory array. It is used to selectively designate two sets of I / O lines.

The two-bit complementary internal address signals BX1 and BX2 are then supplied to the word line drive signal generation circuit XIJ. The word line select timing signal X is supplied to the word line drive signal generation circuit XIJ, and the internal signal XNK is supplied from the redundant circuit XRC. The word line selection timing signal X is an inversion timing signal. The high level becomes a boost level higher than the power supply voltage VCC of a circuit.

Here, the X-based redundant circuit XRC includes four unit circuits XRC0 to XRC3 provided corresponding to the redundant word lines WR0 to WR3. These unit circuits include eight fuse means for holding a bad address assigned to a corresponding redundant word line, a bad address held by these fuse means, and an 8-bit X address externally given during memory access, that is, a complementary internal address. And an address comparison circuit for comparing and combining the signals BX1 to BX8. In this embodiment, the address comparison circuit provided in each unit circuit of the X-based redundant circuit XRC does not match the coincidence detection circuit that determines that the defective address and the address given correspond to all bits. Both sides are provided, respectively. These detection circuits are so-called selective drawing circuits that selectively take out the charges of the predetermined output nodes precharged in accordance with the timing signal XP in accordance with the address comparison combination result as described below. As a result, the internal signal XRK indicating that the defective address and the given address are inconsistent with the internal signal XNK indicating that all bits match is exclusively converted to a high level. This makes it possible to speed up the operation of the X-based redundant circuit XRC serving as a critical path since these internal signals are used as they are as the logic conditions of the circuits in the next stage without strobe at a predetermined timing.

The word line drive signal generation circuit XIJ has a basic configuration of a selective drawing circuit which operates in accordance with the timing signal XP, similarly to the X-based redundant circuit XRC. The word line selection driving signal X00 is selectively transmitted by selectively transmitting the word line selection timing signal X on the condition that the internal signal XNK is at a low level, that is, the bad address allocated to all redundant word lines does not coincide with the assigned X address. , X01, X10 or X11. These wand line selection drive signals are supplied to the X address decoders XAD00 and XAD01 to XAD70 and XAD71 and used to alternatively designate four word lines in the selected word line group.

However, if the corresponding bad address and the given X address in the unit circuit of any of the X redundant circuit XRC coincide with all bits, the output signal of the corresponding unit circuit, that is, the internal signals XRA0 to XRA3 is alternatively low level. The internal signal XNK becomes high level. For this reason, the operation of the word line drive signal generation circuit XIJ is stopped and the internal signal XRK is at a low level, so the redundant word line drive signal generation circuit XRIJ is brought into an operation state. In this operation state, the redundant word line driving signal generating circuit XRIJ selectively transmits the word line selecting timing signal X and becomes an output signal thereof, that is, the redundant word line selecting driving signal XRIJ. The redundant word line selection drive signal XRIJ is supplied to the X address decoders XAD00 and XAD01 to XAD70 and XAD71 together with the internal signals XRA0 to XRA3 and used to selectively select the redundant word lines WR0 to WR3 of each memory array. do.

The remaining six bits of complementary internal address signals BX3 to BX8 are supplied to the X predecoder PXAD. The X predecoder PXAD alternately sets the predecode signals AX30 to AX33, AX50 to AX53, and AX70 to AX73, respectively, by sequentially combining the complementary internal address signals BX3 to BX8 by two bits. These predecode signals are supplied to the X address decoders XAD00 and XAD01 to XAD70 and XAD71 and used to alternatively specify the word line group of each memory array.

X address decoders XAD00 and XAD01 to XAD70 and XAD71 correspond to the inverted selection signals. Becomes low level, thereby selectively operating. In this operation state, each X address decoder combines the word line selection drive signals X00, X01, X10 and X11 or redundant word line selection drive signals XRIJ and predecode signals AX30 to AX33, AX50 to AX53 and AX70 to AX73. The corresponding one word line or redundant word line is alternatively placed in a high level selection state.

On the other hand, of the internal address signals outputted from the Y address buffer YAB, 8-bit internal address signals CY1 to CY8 are supplied to the Y redundant circuit YRC. The Y redundant circuit YRC includes four unit circuits YRC0 to YRC3 provided corresponding to the redundant complementary data lines DR00 to DR03 to DR30 to DR33, similarly to the X based redundant circuit XRC.

These unit circuits each include eight fuse means for holding a defective address assigned to a corresponding redundant complementary data line, and an address comparison circuit for determining that these defective addresses coincide with Y addresses given upon memory access. Each unit circuit of the Y-based redundant circuit YRC is selectively operated in accordance with the timing signal RG. In this operation state, each unit circuit of the Y redundant circuit YRC compares and combines the corresponding bad address and the given address, that is, the internal address signals CY1 to CY8 bit by bit, and the output signal provided that these addresses match all the bits. Ie inverted internal signal Selectively low level. Invert this to internal signal Is supplied to the Y predecoder PYAD.

The 8-bit internal address signals BY1 to BY8 are supplied to the Y predecoder PAYAD and the Y address buffer YAB, and the mat selection signals MS0 to MS3 are supplied to the mat selection circuit MS. The Y predecoder PYAD is selectively operated in accordance with the timing signal RG. In this operation state, the Y predecoder PYAD decodes the internal address signals BY1 to BY8 by sequentially combining the two bits, and decodes the inverted internal signal. The predecode signals AY10 to AY13, AY30 to AY33, AY50 to AY53, and AY70 to AY73 are alternatively set to a high level on the condition that they are at a high level. That is, the predecode signals AY10 to AY13 are inverted internal signals. Becomes high level in accordance with the internal address signals BY1 and BY2, and the predecode signals AY30 to AY33 are inverted internal signals. Is at a high level, alternatively at a high level in accordance with the internal address signals BY3 and BY4. Similarly, the predecode signals AY50 to AY53 are inverted internal signals. Becomes high level in accordance with the internal address signals BY5 and BY6, and the predecode signals AY70 to AY73 are inverted internal signals. Is at a high level, alternatively at a high level in accordance with the internal address signals BY7 and BY8. These pre decoder signals are supplied to the Y address decoders YAD0 to YAD7 and used to alternatively specify the complementary data line group in each memory array.

However, when the corresponding bad address and the given Y address coincide with all bits in one unit circuit of the Y redundant circuit YRC, the corresponding output signal, that is, the inverted internal signal Becomes low level. For this reason, the corresponding predecode signal is not formed in the Y predecode PYAD, but instead the inverted internal signal. Is optionally at a low level. These inverted internal signals are supplied to the Y address decoders YAD0 to YAD7 and used to alternatively specify the redundant complementary data line group.

The Y address decoders YAD0 to YAD7 are selectively put into operation according to the inversion timing signal PC. In this operation state, the Y address decoders YAD0 to YAD7 are the complementary selection signals Y0 and Y1 and the predecode signals AY10 to AY13, AY30 to AY33, AY50 to AY53 and AY70 to AY73 or the inverted internal signal. By combining the two complementary data lines or redundant complementary data lines of the corresponding memory array, each pair is connected to the corresponding two sets of common I / O lines.

That is, in the dynamic RAM of this embodiment, as shown in FIG. 83, first, two memory mats MAT0 to MAT7 are simultaneously selected in accordance with two-bit X address signals X0 and X9. In a total of four memory arrays constituting two memory mats to be selected at the same time, one word and four total word lines designated by 8-bit X address signals X1 to X8 are selected. In each memory array, two sets of eight sets of complementary data lines each designated by the eight-bit Y address signals Y1 to Y8 are selected and connected to the corresponding sets of eight sets of common I / O lines.

Of the 32 sets of common I / O lines provided in the dynamic RAM, 8 sets of common I / O lines to which the designated 8 sets of complementary data lines are selectively connected are connected through the common I / O line selection circuits IOS0 to IOS15. It is connected to the amplifiers MA0 to MA7. The main amplifiers MA0 to MA7 are alternatively operated according to the Y address signal Y0 of the least significant bit and the X address signal X10 and Y address signal Y10 of the most significant bit when the dynamic RAM has the x1 bit configuration, and the data input terminals Din, It is also alternatively coupled to the data output terminal Dout. In addition, when the dynamic RAM is composed of x4 bits, four pieces are selectively operated in accordance with the least significant bit Y address signal Y0, and are selectively coupled to the corresponding data input / output terminals I / O1 to I / O4. When the dynamic RAM is in x1 bit configuration and is in nibble mode, four main amplifiers MA0 to MA7 are selectively operated by four, and are selectively coupled to the data input terminal Din or the data output terminal Dout according to the output signal of the nibble counter. do.

In the above, the dynamic RAM of this embodiment has an address space of row address and column address mode 2048 and a so-called 4M bit storage capacity when configured in the x1 bit configuration. When the dynamic RAM is composed of x4 bits, the most significant bit of the X address signal X10 and the Y address signal Y10 become invalid, and the dynamic RAM has an address space of 1024 for both the row address and the column address.

3.2. Specific composition of each part, layout and operation and its features

42 to 79 show a circuit diagram of one embodiment of each part of the dynamic RAM to which the present invention is applied. 80 and 81 show timing charts of one embodiment of the read cycle and write cycle of the dynamic RAM of this embodiment, and FIG. 82 shows the timing charts of one embodiment of the reproduction counter RFC. . FIG. 86 shows an arrangement conceptual diagram of one embodiment of the precharge control signal line of the dynamic RAM of this embodiment, and FIGS. 87 and 88 show an arrangement diagram of one embodiment of the monitor word line and sense amplifier, respectively. have. 89 to 91 show circuit diagrams of several embodiments of the input protection circuit of the dynamic RAM of this embodiment, and FIGS. 92 to 98 show arrangement diagrams of several embodiments of the input protection circuit. It is. Based on these drawings, the detailed structure, arrangement and operation of each part of the dynamic RAM of this embodiment will be described, and the features thereof will be described.

Incidentally, in the following circuit diagram, the MOSFET to which the arrow is added to the channel (back gate) portion is displayed separately from the N-channel MOSFET to which the arrow is added as a P-channel type. In the right end of each circuit diagram, the block name of the corresponding peripheral circuit is described, and at the bottom thereof, the layout position of each peripheral circuit (that is, the U included in the upper side peripheral circuit, and the peripheral side and lower side peripheral circuits) are included. Are indicated by C and D, respectively, and the installation coefficients are indicated by adding (). For a negative logic signal, a horizontal line is usually added above the signal name, but B may be added at the end of the signal name.

3.2.1. Memory mat

As described above, the dynamic RAM of this embodiment is provided with eight pairs of memory mats MAT0 and MAT1 to MAT6 and MAT7, respectively. These memory mats are a pair of symmetrically arranged Y-address decoders YAD0 and YAD1 to YAD6 and YAD7 correspondingly provided as representatively showing the memory mats MAT0 and MAT1 shown in FIG. 78 and these Y address decoders. Memory arrays MARY00 and MARY01 to MARY70 and MARY71, sense amplifiers SAP00, SAN00 and SAP01, SAN01 to SAP70, SAN70 and SAP71, SAN71, column switches CSW00 and CSW01 to CSW70 and CSW71 and X address decoders XAD00 and XAD01 to XAD70 and XAD71, respectively Include.

3.2.2. Memory array

The memory arrays MARY00 and MARY01 to MARY70 and MARY71 constituting the memory mats MAT0 to MAT7 are not particularly limited, but are 256 word lines W0 to W255 arranged in parallel with the vertical direction as exemplarily shown in FIG. Four redundant word lines WR0 to WR3 and 1024 sets of complementary data lines D0 to D1023 arranged in parallel with the horizontal direction and 16 sets of redundant redundant data lines DR0 to DR15 not shown. At the intersection of these word lines and complementary data lines, 260 x 1040 dynamic memory cells are arranged in a grid.

The dynamic memory cells constituting each memory array include, but are not particularly limited to, an information accumulation capacitor and an address selection MOSFET as illustrated in FIG. 78, respectively. The input / output terminals of the 260 memory cells arranged in the same column, that is, the drain of the address selection MOST are alternately coupled to the non-inverting signal line or the inverting signal line of the corresponding complementary data line or redundant redundant data line with predetermined regularity. Further, the control terminals of the 1040 memory cells arranged in the same row, that is, the gates of the address selection MOSFETs are commonly coupled to the corresponding word lines or redundant word lines.

The word lines and redundant word lines constituting each memory array are divided into four groups, and a unit circuit of an X address decoder is prepared corresponding to these word line groups. Similarly, the complementary data lines and redundant redundant data lines constituting each memory array are divided into groups of four sets each, and a unit circuit of a Y address decoder is prepared corresponding to four sets of complementary data groups, that is, 16 sets of complementary data lines in total.

The word line and redundant word line constituting each memory array are not particularly limited, but are coupled to the ground potential of the circuit via a corresponding clear MOSFET on one side thereof as exemplarily shown in FIG. 78, and on the other side. The corresponding X address decoders XAD00 and XAD01 to XAD70 and XAD71 correspond to the corresponding unit circuits. On the other hand, the complementary data lines and redundant redundant data lines constituting each memory array are not particularly limited, but are coupled to corresponding unit circuits of the corresponding sense amplifiers SAP00 and SAP01 to SAP70 and SAP71 on one side thereof. The other side is coupled to the corresponding unit circuits of the corresponding sense amplifiers SAN00 and SAN01 to SAN70 and SAN71, and to the corresponding switch MOSFETs of the corresponding column switches CSW00 and CSW01 to CSW70 and CSW71.

3.2.2. X address decoder

The unit circuits of the X address decoders XAD00 and XAD01 to XAD70 and XAD71 each include four word line driving MOSFETs provided corresponding to four word lines of the corresponding word line group of the memory array, as exemplarily shown in FIG. Include. Sources of these word line driving MOSFETs are coupled to corresponding word lines, and at their drains, corresponding word line selection driving signals X00, X01, X10 and X11 in the word line driving signal generation circuit XIJ (the signals supplied to each memory array are U or D is added or the number of the memory mat is added by the layout position of the memory array, but the description thereof becomes cumbersome, so it is abbreviated and abbreviated. The gates of these word line driving MOSFETs are commonly coupled to the internal node n1 via corresponding cut MOSFETs. The internal node n1 is coupled to the output terminal of the inverter circuit. Input terminal and inverting selection signal line of this inverter circuit In between, three series MOSFETs which receive predecode signals AX30 to AX33, AX50 to AX53, and AX70 to AX73 in a predetermined combination are provided to form a so-called decoder tree. As a result, the internal node n1 has a corresponding inversion selection signal. Becomes low level and, optionally, becomes high level when the predecode signals become high level simultaneously in corresponding combinations. As a result, word line selection drive signals X00, X01, X10 or X11, which are alternatively at the boost level, are transmitted to corresponding word lines in the corresponding word line group, and the word lines are alternatively selected.

However, when a bad address assigned to any one of the redundant word lines WR0 to WR3 is designated, as described above, all of the word line selection driving signals are fixed at a low level while the corresponding internal signals XRA0 to XRA3 are alternatively at a low level. do. Further, the redundant word line selection drive signal XRIJ is at the subsuit level, and the corresponding internal signals XIJL0 to XIJL7 are alternatively at the low level. For this reason, when the timing signal XDP for precharging becomes high, the internal node n2 is alternatively left at the high level, whereby the boost level of the redundant word line selection driving signal XRIJ is alternatively corresponding to the redundant word line. This redundant word line may alternatively be selected.

3.2.4. Sense amplifier

The sense amplifier of the dynamic RAM of this embodiment is not particularly limited, but the sense amplifiers SAN00 and SAN01 disposed inside and the Sans amplifiers SAP00 and SAP01 to SAP70 and SAP71 disposed outside of the corresponding memory array as shown in FIG. SAN70 and SAN71 are included.

The dual sense amplifiers SAP00 and SAP01 to SAP70 and SAP71 are each provided with 1040 unit circuits provided corresponding to the complementary data lines and redundant redundant data lines of the memory array. Each unit circuit includes a pair of P-channel MOSFETs whose gates and drains are cross-coupled with each other, as exemplarily shown in FIG. 78. Gates and drains, to which these P-channel MOSFETs are cross-coupled, are coupled to corresponding complementary data lines of the memory array, the sources of which are commonly coupled to a common source line CSPN or CSNP.

The sense amplifiers SAN00 and SAN01 to SAN70 and SAN71 are each provided with 1040 unit circuits provided corresponding to the complementary data lines and redundant information data lines of the memory array. Each unit circuit includes a pair of N-channel MOSFETs whose gate and drain are cross-coupled with each other, as exemplarily shown in FIG. 78. Commonly coupled gates and drains of these N-channel MOSEFTs are coupled to corresponding complementary data lines of the memory array, the sources of which are commonly coupled to the common source line CSNP or CSPN. Each unit circuit further includes a precharge circuit comprising two N-channel MOSFETs arranged in series between the non-inverting signal line and the inverting signal line of each complementary data line of the memory array, and one N-channel MOSFET provided in parallel therewith. It includes each. The gates of these MOSFETs are all commonly coupled, and are commonly coupled to the corresponding precharge control signal lines PC0NB to PC7NB. In addition, a predetermined constant voltage HVC is commonly supplied to a common coupled node of two MOSFETs in series. The center voltage of the constant voltage HVC is not particularly limited, but is 1/2 of the power supply voltage VCC of the circuit, that is, + 2.5V.

In this case, the pair of P-channel MOSFETs constituting the unit circuits of the sense amplifiers SAP00 and SAP01 to SAP70 and SAP71 is connected to the pair of N-channel MOSEFTs constituting the corresponding unit circuits of the sense amplifiers SAN00 and SAN01 to SAN70 and SAN71. Together, one unit amplifier circuit is constructed. These unit amplification circuits are selectively put into operation by supplying the power source voltage and ground potential of the circuit to the corresponding common source lines CSPN and CSPN in a predetermined combination. In this operation state, each unit amplification circuit amplifies the micro read signal outputted through the corresponding complementary data line from the memory cell coupled to the word line to be the selected state of the memory array to be a high level or low level binary read signal. .

However, the source regions PS1, PS2, drain regions PD1, PD2, and gate regions PG1, PG2 of the P-channel MOSFETs constituting the sense amplifiers SAP00 and SAP01 to SAP70 and SAP71 and N constituting the sense amplifiers SAN00 and SAN01 to SAN70 and SAN71 The source regions NS1, NS2, the drain regions ND1, ND2, and the gate regions NG1, NG2 of the channel MOSFET are line-symmetric with a straight line intersecting at right angles in the extending direction of the corresponding complementary data line, respectively, as shown in FIG. 88 (b). In addition, it is formed in parallel with the straight line, respectively. For this reason, when mask shift | offset | difference arises, for example in a manufacturing process, the change of the parasitic capacitance which generate | occur | produces in the non-inverting and inverting signal line of each information data line cancels each other. As a result, the capacity of the complementary data lines is balanced and the signal amount margin is secured, so that the read operation of the dynamic RAM is stabilized.

On the other hand, the three N-channel MOSFETs constituting the precharge circuits of the respective unit circuits of the sense amplifiers SAN00 and SAN01 to SAN70 and SAN71 have a dynamic RAM in a non-selected state and corresponding precharge control signals PCONB to PC7NB at a high level. Is selectively turned ON. As a result, the non-inverting signal line and the inverting signal line constituting each complementary data line of the memory array are short-circuited, respectively, and their levels are all at the constant voltage HVC.

By the way, in the dynamic RAM of this embodiment, the common source lines CSPN and CSNP provided corresponding to two memory arrays of paired memory mats are formed to cross each other at the center of the semiconductor substrate surface. That is, as shown in FIG. 78, for example, the common source line CSPN in which the sources of the P-channel MOSFET pairs constituting the sense amplifier SAP00 in the memory array MARY00 are commonly coupled is configured the sense amplifier SAN00 in the memory array MARY01. The common source line CSNP, in which the sources of the N-channel MOSFET pairs are commonly coupled, and the sources of the N-channel MOSFET pairs, which constitute the sense amplifier SAN00 in the memory array MARY00, are commonly coupled to form a sense amplifier SAP00 in the memory array MARY01. The sources of P-channel MOSFET pairs are commonly coupled. As shown in FIG. 46, common coupling of the same common source line is performed for the other memory mats.

The common source line CSPN of each pair of memory arrays is coupled to the common source line driving circuits CSN1, CSN3, CSN5, and CSN7 of corresponding radix numbers at the top thereof, as shown in FIG. The common source line driving circuits CSP0, CSP2, CSP4, and CSP6 of the number are coupled. Similarly, the common source line CSNP of each pair of memory arrays is coupled to the common source line driving circuits CSNO, CSN2, CSN4 and CSN6 of the corresponding even number at the top thereof, and the common source line driving circuit of the corresponding odd number at the bottom thereof. Is bound to CSP1, CSP3, CSP5 and CSP7. The paired common source lines CSPN and CSNP are also coupled to the corresponding common source line equalization circuit CSS at the bottom thereof.

The common source line driving circuits CSNO to CSN7 have a circuit configuration as illustrated in FIG. 46, and selectively select the ground potential of the circuit to the corresponding common source line CSNP or CSPN in accordance with the timing signal R3 and the mat selection signals MS0 to MS3. Supply. Similarly, the common source line driving circuits CSP0 to CSP7 selectively supply the power supply voltage of the circuit to the corresponding common source line CSPN or CSNP in accordance with the timing signals R3 and P2 and the mat selection signals MS0 to MS3. On the other hand, the common source line equalization circuit CSS is selectively operated when the mat select signals MS0 to MS3 are all low level, and the corresponding common source lines CSPN and CSNP are shorted to a half precharge level such as a constant voltage HVC. The operation of the common source line equalization circuit CSS is optionally stopped when the corresponding matte selection signal becomes high level.

In this case, the common source line CSPN of each pair of memory arrays is used by supplying the ground potential of the circuit to the sense amplifier disposed above and supplying the power supply voltage of the circuit to the sense amplifier disposed below. The common source line CSNP is also used to supply the power supply voltage of the circuit to the sense amplifier disposed above and to supply the ground potential of the circuit to the sense amplifier disposed below. For this reason, the shape of the common source line CSPN is thinned at the intersection with the corresponding common source line CSNP as exemplarily shown in FIG. As a result, while stabilizing the operation of the sense amplifier, the common source line and the common source line driving circuit can be shared to reduce the area required for the layout of the memory array and the peripheral portion.

On the other hand, the precharge control signal line for controlling the precharge circuit of each sense amplifier unit circuit is driven at its outer end, for example by the precharge control signal PCOFB or PC1FB, as illustrated in FIG. 78, and both ends thereof. Is driven by the precharge control signal PCONB or PC1NB, for example. As a result, the operation of the precharge circuit can be speeded up while reducing the line width of the precharge control signal line. However, the precharge control signals PCOFB and PC1FB and the like are formed via a total of six logic gate circuits in the internal address signals BX0 and BX9 as shown by the mat selection circuit MS and the precharge control circuit PCUB of FIG. The precharge control signals PC0NB and PC1NB and the like are formed via a total of four stage logic gate circuits in the internal address signals BX0 and BX9 as shown by the X decoder control circuit XDGB in FIG. Accordingly, a timing difference occurs between the precharge control signals PC0FB and PC1FB and corresponding precharge control signals PC0NB and PC1NB, thereby causing a through current to flow through the precharge signal line. For this reason, in this embodiment, as shown by the X table in FIG. 78, the precharge control signal line is cut at a position inversely proportional to the propagation delay time of both precharge control signals, thereby preventing the deviation of the transfer time.

3.2.5. Column switch and common I / O line

As described above, the dynamic RAM of this embodiment corresponds to four sets of common I / O lines IOOLO to IOOL3, IO2LO to IO2L3, IO4LO to IO4L3, and IO6LO to IO6L3, and IOOHO to IOOH3, and IO2HO to correspond to each memory array that is paired up and down as described above. IO2H3, IO4HO-IO4H3, and IO6HO-IO6H3 are provided. As described above, these common I / O lines cross the non-inverting and inverting signal lines at the centers of the two memory arrays forming the upper and lower pairs, and the corresponding common I / O lines are equalized as shown in FIG. The equalization processing by the circuits IOEQ0 to IOEQ3 is received.

The common I / O line equalization circuits IOEQ0 to IOEQ3 are eight pairs of complementary transfer gates provided between the non-inverting and inverting signal lines of eight sets of common I / O lines corresponding to each pair of memory mats as shown in FIG. Each includes a MOSFET. These transfer gate MOSFETs are normally turned ON, and the output signal of the common I / O line precharge control circuit IOP, that is, the inverted internal signal IOPOB, is at a high level, and the corresponding inverted internal address signal BX9B or the non-inverted internal address signal BX9 is It is turned off selectively on condition that it is at a high level.

As shown in FIG. 62, the output signal IOPOB of the common I / O line precharge control circuit IOP is attained by the high level of the output signals AT0 to AT4 or the internal signal WPC of each part of the address transition detection circuit ATD. Optionally low level. Of these, the output signals AT0 to AT4 of the address transition detection circuit ATD are fixed at a high level when the dynamic RAM becomes non-selected as described below. In addition, once the dynamic RAM is in the selected state, once the low level is set, the corresponding Y address signal is changed to a high level temporarily. On the other hand, the internal signal WPC is formed by the Y-based activation circuit YACT of FIG. 62, and the rising edge of the inverted internal timing signal W3B for forming the write pulse WYP when the dynamic RAM goes into the fast page mode or the static column mode, In other words, immediately after the end of the write, it temporarily becomes a high level, and becomes a start signal for starting the read operation after the write. As a result, even when there is no address transition, the common I / O line precharge control circuit IOP and the Y system activation circuit YACT are started to execute a series of read operations starting from the common I / O line equalization operation. When the dynamic RAM enters nibble mode, the internal signal WPC remains low.

The output signal IOPOB of the common I / O line precharge control circuit IOP is normally low level when the dynamic RAM is in the non-selected state, and becomes high level when the dynamic RAM is in the selected state, and then outputs the address transition detection circuit ATD. The signal is temporarily turned low in accordance with the signals AT0 to AT4 or the internal signal WPC. Therefore, the non-inverting and inverting signal lines of each common I / O line are normally shorted, and when the dynamic RAM is selected, the short is selectively released in accordance with the logic level of the internal address signal BX9, that is, the X address signal X9. Then, when the change of the Y address signal is detected by the address transition detection circuit ATD, or immediately after the write operation by the fast page mode or the static column mode is finished, the state is temporarily shorted.

In this way, the common I / O line equalization circuits IOEQ0 to IOEQ3 are arranged in the center portion, thereby speeding up the equalization processing of the common I / O line for arranging a relatively long distance over two memory arrays forming an upper and lower pair.

The common I / O lines are commonly coupled to the complementary data lines of the corresponding memory arrays through the corresponding pairs of column switches CSW00 and CSW01 to CSW70 and CSW71 at four pair intervals as illustrated in FIG. The gates of these switch MOSFETs are not particularly limited but are commonly coupled in pairs, and corresponding data line selection signals YS00, YS01, and the like are supplied from the corresponding Y address decoders YAD0 or YAD1, respectively. As a result, four sets of complementary data lines arranged adjacent to each other in the two memory arrays constituting each memory mat are selected at the same time, and the common I / O lines IOOL0 and IOOL2, or IOOL1 and IOOL3, and the common I / O. Wire IOOHO and IOOH2 etc. or IOOH1 and IOOH3 etc.

3.2.6. Y address decoder

The Y address decoders YADO to YAD7 each include 64 unit circuits provided corresponding to 16 sets of complementary data lines of the corresponding memory array and 4 unit circuits provided corresponding to 4 sets of redundant complementary data lines. The unit circuit provided corresponding to 16 pairs of complementary data lines is provided between the internal node N3 and the power supply voltage or timing signal line PC (matte selection number m or n of the circuit), as illustrated in FIG. 79. It includes several P-channel and N-channel MOSFETs, each arranged in parallel or in series. These MOSFETs constitute a series of decoder trees by supplying predecode signals AY10 to AY13, AY30 to AY33, AY50 to AY53, and AY70 to AY73 to their gates in corresponding combinations. As a result, the internal node n3 of each unit circuit is selectively made low, provided that the timing signal PC becomes low and all the corresponding predecode signals become high.

The level of the internal node n3 of each unit circuit also becomes the data line selection signals YS00, YS01 and the like through a negative AND circuit with corresponding complementary selection signals Y0 and Y1. Here, the complementary selection signals Y0 and Y1 are Y level activation signals YACT as high level as shown by the X decoder control circuit XDGB in FIG. 47, and when the complementary internal address signal AY9C, that is, the Y address signal Y9 becomes logical 0 or logic 1, Optionally, logical one. As a result, for example, the data line selection signal YS0 becomes a high level when the predecode signals AY10, AY30, AY50 and AY70 are all high level, and when the complementary selection signal Y0 becomes logic 1, that is, the Y address signal Y9 becomes logic 0, selectively. It becomes In addition, the data line selection signal YS1 becomes a high level when the predecode signals AY10, AY30, AY50 and AY70 are all at a high level, and when the complementary selection signal Y1 becomes a logic 1, that is, a Y address signal Y9 becomes a logic 1, it becomes selectively high level. Of course, these data line selection signals are selectively formed for each memory mat corresponding to the mat selection signal or the like.

On the other hand, the unit circuit of each Y address decoder provided corresponding to four sets of redundant complementary data lines is not particularly limited, but the inverted internal signals corresponding to the complementary selection signals Y0 and Y1 as illustrated in FIG. It consists of two negative AND circuits. The inversion internal signal in these unit circuits The node to which is supplied corresponds to the internal node n3. The output signal of each unit circuit is supplied to two sets of redundant complementary data lines of each redundant word line group as redundant data line selection signals YSR0 to YSR7. Thus, for example, the redundant data line selection signal YSR0 is the corresponding inverted internal signal. Becomes low level, and when the complementary selection signal Y0 becomes logic 1, that is, the Y address signal Y9 becomes logic 0, it becomes selectively high level. The redundant data line selection signal YSR1 is a corresponding inverted internal signal. Becomes low level, and when the complementary selection signal Y1 becomes logic 1, that is, the Y address signal Y9 becomes logic 1, it becomes selectively high level. Of course, these redundant data line selection signals are selectively formed for each memory mat.

3.2.7. X address buffer

As shown in Figs. 50 and 51, the X address buffer XAB has address input terminals A0 to A8 and A9 (output enable signal input terminal in case of x4 bit configuration). 11 unit circuits XAB0 to XAB10 and address input terminals A6Z to A8Z and A9Z provided in response to A10 (address input terminal A9 in the case of x4 bit configuration) and output enable signal input terminals in the case of x4 bit configuration. Four unit circuits XAB6Z to XAB9Z are provided. As described above, these unit circuits are arranged close to the corresponding bonding pads, and address buffer control circuits XABCO to XABC6 are provided corresponding to one or several unit circuits arranged in close proximity.

The X address buffer XAB also provides a number of connection switching points at which a predetermined aluminum wiring is selectively formed according to the bit structure of several input control MOSFETs and dynamic RAM provided between the input terminal Ai of each unit circuit and the ground potential of the circuit. Have

An internal signal ZIP or an inverted internal signal is provided at a gate of the input control MOSFET. Is optionally supplied. Where internal signal ZIP and inverted internal signal Although not particularly limited, as shown in FIG. 76, the dynamic RAM is in the form of a DIP or SOJ package, and becomes low level when the pad ZIP is opened. The dynamic RAM is in the form of a ZIP package, and the pad ZIP is a power supply for the circuit. When bonded with voltage, it is at a high level. As a result, the input terminal Ai of the unit circuits XAB6 to XAB9 is forcibly short-circuited to the ground potential of the circuit when the dynamic RAM becomes a ZIP package type, and the input terminal Ai of the unit circuits XAB6Z to XAB9Z is DIP or When in SOJ package form, it is forcibly shorted to the ground potential of the circuit. The input control MOSFETs corresponding to the unit circuits XAB0 to XAB5 and XAB9 and XAB10 are normally turned off by supplying the inverted signal of the circuit's power supply voltage, that is, a fixed low level signal.

The address buffer control circuits XABC0 to XABC6 receive a two-input NAND gate circuit that receives the input signals ZIP and R1 at its two input terminals and the output signal of the NAND gate circuit at one of its input terminals, as illustrated in FIG. And a two-input NOR gate circuit that receives an input signal CBR at its other input terminal. The output signal of this NOR gate circuit is supplied to the 3rd input terminal of a 3 input NOR gate circuit through two inverter circuits, and becomes an output signal BXIE via two inverter circuits. Input signals R3 and CBR are supplied to the first and second input terminals of the three-input NOR gate circuit, and the output signals thereof become non-inverted timing signals XL and inverted timing signals XLB through one or two inverter circuits. .

In this embodiment, the inverting internal signal is applied to the input terminals Z of the address buffer control circuits XABC2 and XABC3. Is supplied, and the internal signal ZIP is supplied to the input terminals Z of the address buffer control circuits XABC1 and XABC4. The input terminal Z of the address buffer control circuits XABCO and XABC5 and XABC6 is coupled to the power supply voltage of the circuit. Input terminals R1 and R3 of each address buffer control circuit include the timing generation circuit TG. The timing signals R1 and R3 are supplied from the system control circuit RTG, respectively, and the internal signal CBR is supplied to the input terminal CBR. Here, the internal signal CBR is selectively raised to a high level at a predetermined timing when the dynamic RAM becomes a CBR regeneration cycle as described below.

In this case, the internal signal BXIE output from each address buffer control circuit becomes high when both the corresponding input signals Z and R1 become high level and the input signal CBR becomes low level, that is, the dynamic RAM becomes the corresponding package and at the same time other than the CBR regeneration cycle. When it becomes a selection state in the cycle of, it is selectively made high level according to the timing signal R1. Similarly, the complementary timing signal XL output from each address buffer control circuit becomes logic 1 under the same condition as the internal signal BXIE, and returns to logic 0 when the timing signal R3 becomes high level.

Each unit circuit of the X address buffer XAB has a three-input NAND gate circuit that receives the corresponding address signal Ai and the inversion timing signal XLB as shown in FIG. 49, and 1 becomes complementary to the complementary timing signal XL. A pair of clock inverter circuits is included. The inverted output signal of the NAND gate circuit is supplied to the input terminal of one of the clock inverter circuits, and the other clock inverter circuit is latched together with the inverter circuit of the rear stage. As a result, each address signal is transferred to the latch on the condition that the timing signal R1 becomes high and the complementary timing signal XL becomes logic 0. When the complementary timing signal XL goes to logic 1, the latch is held and is not affected by the input address signal.

Each unit circuit of the X address buffer XAB receives an inverted and non-inverted output signal of the latch at its respective gate, and an open-drain type in which the drain potential corresponds to the output signal BX1 and the inverted output signal BXIB of the corresponding unit circuit. It contains a pair of output MOSFETs. The common coupled source of these output MOSFETs is coupled to the ground potential of the circuit via a MOSFET that receives the internal signal BXIE at its gate.

The output terminals BXI and inverted output terminals BXIB of the unit circuits XAB1 to XAB5 are not particularly limited but are coupled to the complementary input terminals of the corresponding termination circuit BXL1. The output terminals BXI and inverted output terminals BXIB of the unit circuits XAB6 to XAB8 are coupled to the complementary output terminals of the corresponding unit circuits XAB6Z to XAB8Z and then to the complementary input terminals of the corresponding termination circuit BXL1. Similarly, output terminal BXI and inverted output terminal BXIB of unit circuit XAB0 are coupled to the complementary input terminal of corresponding termination circuit BXL0. Further, the output terminal BXI and the inverted output terminal BXIB of the unit circuit XAB9 are coupled to the complementary output terminal of the corresponding unit circuit XAB9Z and then to the complementary input terminal of the corresponding termination circuit BXL0.

The complementary input terminals of the ten termination circuits BXL1 and BXL0 are commonly combined with the complementary output terminals of the corresponding bits of the reproduction counter RFC described below. These termination circuits, their precharge circuits, and each unit circuit of the regeneration counter RFC are disposed in the middle side of the semiconductor substrate surface in order to increase noise resistance. As a result, the output of the unit circuit except the unit circuit XAB10 of the X address buffer XAB is in the form of a connection logic sum with the output of the corresponding bit of the reproduction counter RFC. Of course, the output of the unit circuit XAB6 NAVI XAB9 of the X address buffer XAB is also in the form of a wiring logic sum with the output of the corresponding unit circuits XAB6Z to XAB9Z. In these wiring logic states, the output of each unit circuit of the X address buffer XAB is selectively enabled by the corresponding internal signal BXIE becoming high level.

In this way, the logical structure of the address buffer is formed by connecting a plurality of unit circuits provided corresponding to each package type of the X address buffer XAB or each unit circuit of the X address buffer XAB and the corresponding unit circuit of the reproduction counter RFC. The number of logical stages can be reduced while giving the degree of freedom to the circuit. For this reason, unit circuits are provided for each package type, and at the same time, the unit circuits are arranged in close proximity to the corresponding pads, thereby reducing the input capacity of the unit circuits, and without being aware of the propagation delay time of the address signals. Output signals can be logically combined. As a result, the number of circuit elements of the X address buffer XAB can be reduced, thereby reducing the layout area and increasing the speed of the dynamic RAM.

On the other hand, the output terminal BX1 and the inverted output terminal BXIB of the unit circuit XAB10 are coupled to the complementary input terminal of the termination circuit AB10. The output signal of this termination circuit AB10 is supplied to the nibble counter circuit NC described below as an internal address signal AX10. When the dynamic RAM has an x4 bit configuration, the output of the unit circuit XAB10 corresponds to the output of the unit circuit XAB9.

Termination circuits BXL1 and BXL0 are the output terminals BXI and inverted output terminals as illustrated in FIG. And a pair of reset MOSFETs provided correspondingly to each other, and a pair of reset MOSFETs provided between these output terminals and the power supply voltage of the circuit. The timing signal R2 is supplied to the gate of the reset MOSFET of the double termination circuit BXL1, and the logic sum of the output signal of the NAND gate circuit receiving the inversion timing signals R1B and R3B, that is, the timing signal R1 and R3, is supplied to the gate of the reset MOSFET of the termination circuit BXL0. The signal is supplied. As a result, the complementary internal address signals BX1 to BX8 transmitted through the termination circuit BXL1 are valid when the timing signal R2 is at a high level, and are reset when the timing signal R2 is at a low level. Similarly, the complementary internal address signals BX0 and BX9 transmitted via the termination circuit BXL0 are made effective by the inversion timing signal R1B being low level and reset by the inversion timing signal R3B being high level. That is, the output signals of the unit circuits, that is, the complementary internal address signals BX0 to BX9, become non-selected in the dynamic RAM, and both the non-inverting and inverting signals become high when each unit circuit is in the reset state. When the dynamic RAM is selected and the reset state is released, the non-inverting or inverting signal is selectively made low depending on the X address signals X0 to X10 supplied during memory access.

As described above, the complementary internal address signals BX0 and BX9 are used to form the mat select signals MS0 to MS3, and it is a requirement to be reset at the end of the operation sequence of the dynamic RAM. In this way, by intentionally changing the reset timing of each address signal according to its use, sequence control by the internal address signal is possible. As a result, the configuration of the peripheral circuit is simplified, and therefore the operation of the dynamic RAM is speeded up.

3.2.8. Mat selection circuit

As shown in FIG. 46, the mat selection circuit MSL is provided corresponding to each of the four memory mats on the upper side and the lower side, and further includes eight unit circuits MS in which the complementary internal address signals BX0 and BX9 are received in a predetermined combination. One common source line driving circuit CSN and CSP and a common source line equalizing circuit CSS are included. The output signal of the unit circuit MS is supplied to each circuit of the dynamic RAM as the mat selection signals MS0 to MS3 which are the basis of the selection operation.

3.2.9. Word line control circuit

The word line control circuit WLC is not particularly limited, but is provided in correspondence with two word line select timing signal generating circuits XU and XD provided corresponding to each of the four memory mats on the upper and lower sides, and a pair of memory mats to be simultaneously selected. Four X decoder monitor circuits DECM, eight word line clear circuits WCUB, X decoder control circuits XDGB, redundant word line drive signal generation circuits XRIJ and 32 word line drive signal generation circuits XIJ It is provided.

The double word line clear circuit WCUB uses the internal signals WCOU to WC3U and WCOD to WC3D which are alternatively formed in accordance with the complementary internal address signals BX0 to BX2 in the word line clear signal generation circuit WCU or WCD as shown in FIG. Basically, inverted word line clear signals WCOOB to WCO3B to WC70B to WC73B are formed. These inversion word line clear signals are all at a high level when the dynamic RAM is in an unselected state, and alternatively at a low level when the dynamic RAM is in a selected state. As a result, word line clear MOSFETs corresponding to one of the four word lines constituting each word line group in the corresponding memory mats MAT0 to MAT7 are turned off, and the short to the ground potential of the circuit is canceled.

Next, the X decoder control circuit XDGB activates the X address decoders XAD00 and XADO1 to XAD70 and XAD71 based on the X-based decoder precharge signal XDP and the complementary internal address signals BX0 and BX9 for mat selection as shown in FIG. And an internal signal XIJL for activating the inverted internal signal XDGB and the word line driving signal generation circuit XIJ and the redundant word line driving signal generation circuit XRIJ described below. As described above, the X decoder control circuit XDGB selectively forms the above-described precharge control signal PCINB based on the inverted internal signal XDGB, and selectively forms complementary selection signals Y0 and Y1 based on the complementary internal address signal AY9C. It has a function together.

The X decoder monitor circuit DECM includes a plurality of MOSFETs corresponding to the decoder tree and the word line driving MOSFET of each unit circuit of the X address decoder XAD described above as illustrated in FIG. 44, and are approximately equivalent to these unit circuits. It has a transmission characteristic. Each X decoder monitor circuit is triggered by a precharge signal AX30 to AX33 having the heaviest load among the internal signal XDGB and the precharge signal output from the corresponding X decoder control circuit XDGB. Then, a low level internal signal DMJ is formed at the timing when the selection operation of the corresponding X address decoder XAD ends. The pair of internal signals DMJ corresponding to the memory mat of the upper side or the lower side are combined via a negative logic sum circuit, respectively, and then logically multiplied with the timing signal R2 to form an inverted internal signal XONUB or XONDB. These inverted internal signals are supplied to the corresponding word line selection timing signal generating circuits XU and XD as their trigger signals, and then passed through the negative logic circuit and then as the internal signals XM. It is supplied to the word line monitor circuit of the system control circuit RTG.

The word line selection timing signal generation circuits XU and XD each include a boost capacitor CB1 as shown in FIG. These boost capacitors CB1 are precharged so that the electrode on the right becomes high level and the electrode on the left becomes low when the dynamic RAM becomes non-selected. When the dynamic RAM enters the selection state, the corresponding mat selection signals MX0 to MX3 become high level, and the corresponding left internal signal XONUB or XONDB becomes low level, and the electrode on the left becomes high level. As a result, the electrode on the right is pushed up to a boost level higher than the power supply voltage of the circuit, whereby the word line selection timing signal XU or XD becomes the boost level. The word line selection timing signals XU and XD are supplied to the word line drive signal generation circuit XIJ and the redundant word line drive signal generation circuit XRIJ.

The word line drive signal generation circuit XIJ boosts a level based on the internal signal XIJL and the complementary internal address signals BX1 and BX2 for word line selection corresponding to the word line selection timing signal XU or XD as shown in FIG. The word line select drive signals XIJ, i.e., X00, X01, X10 and X11, are alternatively formed and supplied to the corresponding X address decoders.

As described above, the word line drive signal generation circuit XIJ is supplied with an internal signal XNK, which is selectively at a high level when the address supplied during memory access in the X-based redundant circuit XRC and the bad address assigned to any redundant word line match. do. When the internal signal XNK becomes high level, the operation of the word line driving signal generation circuit XIJ is substantially stopped so that the word line selection driving signal is not formed.

Similarly, the redundant word line driving signal generation circuit XRIJ forms a redundant level redundant line selection drive signal XRIJ based on the internal signal XIJL and the internal signal XRK corresponding to the word line selection timing signal XU or XD to correspond to the X address. Supply to the decoder. Here, the internal signal XRK is formed as a logical sum signal of the inverted internal signals XRA0B to XRA3B, as shown by the transfer circuit XRA in FIG. These inverted internal signals are selectively set to high level when the address supplied during memory access and the bad address assigned to any redundant word line do not coincide with each other as described below, and accordingly, the internal signal XRK is selectively It becomes a high level. When the internal signal XRK becomes high, the operation of the redundant word line drive signal generation circuit XRIJ is substantially stopped, so that the word line selection drive signal XRIJ is not formed. That is, the boost level word line selection timing signals XU and XD formed by the word line selection timing signal generation circuit XU or XD pass through the word line drive signal generation circuit XIJ when the internal signal XRK becomes high level. , X01, X10 or X11. When the internal signal XN becomes high, it is transmitted as the redundant word line selection drive signal XRIJ via the redundant word line drive signal generation circuit XRIJ.

Reference is made to FIG. 48 by integrating the relationship between the complementary internal address signal supplied to the word line control circuit WLC, each internal signal, a word line selection timing signal, a word line selection drive signal and a redundant word line selection drive signal.

3.2.10. X predecoder

The X predecoder PXAD is not particularly limited but includes three unit circuits AXNL, namely, AXNL, AX3U, AX5U and AX7U provided in correspondence with the upper memory mat, and three unit circuits AXNL, AX3D, AX5D and With AX7D.

The dual unit circuits AX3U, AX5U and AX7U are selectively operated by the inverted internal address signal BXOB being at a low level, and a combination of the corresponding 2-bit complementary internal address signals BX3 and BX4, BX5 and BX6 or BX7 and BX8, respectively By decoding, the predecode signals AX30U to AX33U, AX50U to AX53U, or AX70U to AX73U are selectively formed. These predecode signals are commonly supplied to eight X address decoders XAD10 and XAD11, XAD30 and XAD31, XAD50 and XAD51 and XAD70 and XAD71 provided on the upper side.

Similarly, the unit circuits AX3D, AX5D and AX7D are selectively operated by the non-inverting internal address signal BX0 being low level, and the corresponding 2-bit complementary internal address signals BX3 and BX4, BX5 and BX6 or BX7 and BX8 are respectively applied. By decoding in combination, the predecode signals AX30D to AX33D, AX50D to AX53D, or AX70D to AX73D are selectively formed. These predecode signals are commonly supplied to eight X address decoders XAD00 and XAD01, XAD20 and XAD21, XAD40 and XAD41 and XAD60 and XAD61 provided on the lower side.

Each unit circuit AXNL of the X predecoder PXAD has a non-inverting internal address signal BX0 or an inverted internal address signal as illustrated in FIG. And three three-input AND circuits each receiving a common combination and receiving a non-inverting and inverting signal of a corresponding two-bit complementary internal address signal in a predetermined combination. As described above, the complementary internal address signals BX0 to BX10 correspond to the address signals supplied during memory access when the non-inverting and inverting signals become high level together when the dynamic RAM becomes non-selected and the dynamic RAM is selected. Either of the non-inverting and inverting signals is selectively made low. Therefore, the output signal of each unit circuit AXNL of the X predecoder PXAD, that is, the predecode signal, is fixed at a low level when the dynamic RAM is in an unselected state, and is at a high level when the dynamic RAM is in a selected state.

In this embodiment, each unit circuit of the X predecoder PXAD is provided corresponding to the upper and lower memory mats as described above, and is selectively operated in accordance with the complementary internal address signal BX0. Further, the output signal of this unit circuit is alternatively at a high level when each unit circuit is put into an operating state, whereby the X decoder at the next stage is selectively put into an operating state. As a result, the upper and lower memory mats and their peripheral circuits are alternatively operated in accordance with the complementary internal address signal BX0, thereby increasing the power consumption of the dynamic RAM.

3.2.11. X-based redundant circuit

The dynamic RAM of this embodiment includes four redundant word lines as described above, and includes four X-based redundant circuits XRC0 to XRC3 provided corresponding to the redundant word lines. These X redundant circuits each include XCMP with eight address comparison circuits provided for one redundant enable circuit XRE and complementary internal address signals BX1 to BX8.

The dual redundant enable circuit XRE is selectively blown when the corresponding redundant word line is switched to a defective word line in which a fault is detected, as illustrated in FIG. 53, that is, when the corresponding X redundant circuit is valid. Each includes. When these fuse means FUSE are cut, the output signal XRE1 of each redundant enable circuit XRE, i.e., the internal signals XRE0 to XRE3, is at a high level, and the XCMP is substantially operated with corresponding eight address comparisons.

The redundant enable circuit XRE also has the function of precharging the mismatch detection node XRAI of the XCMP, i.e., the internal nodes XRA0 to XRA3, in the address comparison according to the precharge signal XP, and the fuse inspection function and redundant inspection function described below.

On the other hand, the address comparison XCMP includes a fuse means FUSE that is selectively cut when the corresponding bit of the bad address assigned to the corresponding X-based redundant circuit is logic 1, as shown in FIG. And a coincidence detection circuit and a mismatch detection circuit for determining that the corresponding bit of the allocated bad address and the corresponding bit of the address supplied at the time of memory access, that is, the complementary internal address signals BX1 to BX8 match or are inconsistent. Each address comparison section selectively operates when the corresponding internal signals XRE0 to XRE3 become high levels. At this time, if the corresponding addresses match, the internal node n4 goes to a high level, and the output terminal XRB0 and XRBU are disconnected through the corresponding N-channel MOSFET. In the case where the corresponding address is inconsistent, the internal node N5 is brought to a high level, and the output terminal XRAB and the ground potential of the circuit are shorted through the corresponding N-channel MOSFET.

The address comparison circuit XCMP also has a fuse test function and a redundant test function described below.

The output terminals XRB0 and XRBU of the XCMP are address-combined constituting each X-based redundant circuit XRC, respectively, as illustrated in FIG. At one end, it is coupled to the corresponding termination circuit XENB, and at the other end it is coupled to the corresponding input terminal of the common termination circuit XNK. As a result, in any X-based redundant circuit, provided that the output terminals XRB0 and XRBU to the corresponding eight address comparison circuits are all shorted, that is, the allocated bad address and the address supplied at the time of memory access coincide every bit. Under the condition that the output signal of the termination circuit XNK, that is, the internal signal XNK, is selectively raised to a high level.

Similarly, in the eight address comparisons constituting each X-based redundant circuit XRC, the output terminal XRAB of the XCMP is commonly coupled to the corresponding mismatch detection nodes XRA0 to XRA3, respectively. The levels of these mismatch detection nodes are inverted in the transfer circuit XRA of FIG. 47 and supplied to the respective X address decoders as corresponding internal signals XRA0 to XRA3, and at the same time, a negative logic sum is taken from the transfer circuit XRA to form the internal signal XRK described above. . As a result, the corresponding eight address comparisons in all X-based redundant circuits, provided that the output terminal XRAB of any of the XCMPs is coupled to the ground potential of the circuit, that is, the assigned bad address and which address is supplied during memory access. The internal signal XRK is selectively brought to a high level, provided it is inconsistent in bits.

However, when the dynamic RAM enters the fuse test mode, as shown in FIG. 76, the power supply voltage VCC of the circuit is supplied to the pad FCK, whereby the internal signal FCK becomes high level. The pad VCF is supplied with a predetermined fuse inspection power supply voltage VCF, and is supplied to the redundant enable circuit and the address comparison circuit of each X-based redundant circuit. At this time, a selection signal for alternatively designating the X redundant circuits XRC0 to XRC3 as the address input signals X5 to X8 is supplied and fetched to the latch FEC shown in FIG. The output signals of these latches are supplied to the corresponding redundant enable circuit XRE as a fuse check enable signal, that is, internal signals FCEOX to FCE3X. After the selection signal is fetched to the latch FCE, a fuse selection signal for alternatively designating a fuse of each X series redundant circuit, that is, a redundant enable circuit or an address comparison path, is supplied as the address input signals X0 to X8.

In the redundant enable circuit XRE of each X-based redundant circuit, the corresponding internal signals FCEOX to FCE3X become high level, and the current path through the fuse means FUSE is formed when the corresponding non-inverting internal address signal BX0 becomes high level. In the XCMP address comparison of each X-based redundant circuit, the corresponding internal signals FCEOX to FCE3X become high levels, and the corresponding non-inverting internal address signals BX1 to BX8 become high levels, thereby providing a current path through the fuse means FUSE. Is formed. Thus, by measuring the current value supplied to each X-based redundant circuit at the fuse inspection power supply voltage VCF, the disconnection or partial disconnection of the fuse means FUSE provided in the redundant enable circuit or the address comparison circuit can be detected. There is a number.

On the other hand, when the dynamic RAM enters the redundant test mode, the pad RCK of Fig. 76 is supplied with the power supply voltage VCC of the circuit, whereby the internal signal RCK becomes high level. At this time, a test address provided to each redundant word line is supplied as the X address signals X1 to X8, that is, the complementary internal address signals BX1 to BX8.

In each X-based redundant circuit, first, the P-channel MOSFET provided between the voltage supply point VCF of the redundant enable circuit XRE and the corresponding fuse means FUSE is turned OFF. For this reason, the output signal of each redundant enable circuit, i.e., redundant enable signals XRE0 to XRE3 are at a high level irrespective of the cutting state of the fuse means FUSE, and all the address comparison paths are operated at the same time. At this time, in each address comparison path, the P-channel MOSFET provided between the voltage supply point VCF and the corresponding fuse means FUSE is turned OFF. For this reason, the bad address to be allocated to each X-based redundant circuit is substantially fixed in accordance with the short-circuit path which is parallel with the P-channel MOSFET and optionally provided. As a result, the corresponding XRA0 to XRA3 and the internal signal XNK are selectively set to a high level, provided that the defective address and the test address match all bits, and the internal signal XRK is provided on the condition that any bits are inconsistent. Optionally high level. As a result, the redundancy word lines WR0 to WR3 are alternatively selected prior to the redundancy relief, and the normality of the memory cells coupled to these redundancy word lines can be tested in advance.

3.2.12. Replay Counter

The regeneration counter RFC is constituted by ten unit circuits RC substantially coupled in series with one count pulse generation circuit REF as shown in FIG. The double count pulse generation circuit REF forms a count pulse REF based on the inversion timing signal R1B and the internal signal CBR which is selectively at a high level in the CBR regeneration cycle. In addition, the unit circuit RC includes a master latch and a sleeve latch each having a serial form, and carry input signal CAI supplied from the count pulse REF and the unit circuit RC of the preceding stage as shown in FIG. The carry input terminal of the second unit circuit RC is coupled to the power supply voltage VCC of the circuit.

The complementary output terminal of each bit of the regeneration counter RFC is synchronized to the count pulse REF and is selectively coupled to the ground potential of the circuit via an open drain type MOSFET. These complementary output terminals are commonly coupled to the complementary input terminals of the corresponding termination circuits BXL1 or BXL0 as described above, and are in the form of wiring logic respectively with the complementary output terminals of the corresponding unit circuits of the X address buffer XAB. As a result, the transfer delay time of the X address signal is shortened while reducing the area required for the layout of the X system selection circuit.

3.2.13. Y address buffer

The Y address buffer YAB is an eleven unit circuit provided corresponding to the address input terminals A0 to A8 and A9 (or the output enable signal input terminal OE) and A10 (or A9) as shown in FIGS. 51 and 57. YAB0 to YB10 and address input terminals A6Z to A8Z and A9Z (or output enable signal input terminal OEZ) are provided and four unit circuits YAB6Z to YAB9Z, which are selectively valid when the dynamic RAM becomes a ZIP package, are provided. do. These unit circuits have a circuit configuration as shown in FIG. 56, and fetches and holds corresponding address signals in accordance with the timing signal YL.

The output signals of the unit circuits YAB0 to YAB5 are supplied to the Y-based redundant circuits YRC0 to CRC3 and the address transition detection circuit ATD as the internal address signals CY0 to CY5. The output signals of the double unit circuits YAB1 to YAB5 are further logically multiplied with the timing signal RG and supplied to the Y predecoder PYAD as the internal address signals BY1 to BY5. On the other hand, the output signals of the unit circuits YAB6 to YAB8 and YAB6Z to YAB8Z are supplied to the Y-based redundant circuits YRC0 to YRC3 and the address transition detection circuit ATD as the internal address signals CY6, CY7 and CY8 and CY6Z to CY8Z. After the logical product of the timing signal RG is taken, it is supplied to the Y predecoder PYAD or the like as the internal address signals BY6 to BY8. In addition, the output signals of the unit circuits YAB9 and YAB9Z are supplied to the corresponding unit circuits of the address transition detection circuit ATD as the internal address signals CY9CR and CY9U, and are connected and logic-coupled through the corresponding clock inverter circuits to form the internal address signals CY9B. The internal address signal CY9B and the output signal of the unit circuit YAB10, i.e., the internal address signal CY10 (or CY9CL) and the internal address signal CY0, become complementary internal address signals AYOU and AY9U or AY9C through the connection switching point of FIG. It is supplied to the line selection circuit IOS.

In this embodiment, however, as shown in FIG. 57, the internal address signal line CY9B disposed between the upper and middle side peripheral circuits of the semiconductor substrate surface is placed on the master slice when the dynamic RAM has an x4 bit configuration. This is used as a signal line OECB for transmitting the internal signal OECB formed based on the output enable signal OE.

As a result, the number of signal lines arranged over a relatively long distance in a relatively narrow wiring area is reduced, and the layout efficiency is improved.

3.2.14. Y predecoder

As shown in FIG. 56, the Y predecoder PYAD has 16 unit circuits AYNL, AY01, AY03 and AY05, AY07 to AY61, AY63, AY65, and a total of four unit circuits each provided in correspondence with two memory mats which are paired up and down. AY67 is provided. Of the four unit circuits AY01 to AY61, the corresponding 2-bit internal address signals BY1 and BY2 and the inverted internal signals Supplied to the unit circuits AY03 to AY63, and the internal address signals BY3 and BY4 and the inverted internal signals. Is supplied. Similarly, the four unit circuits AY05 to AY65 have internal address signals BY5 and BY6 and inverted internal signals. Is supplied, and the internal address signals BY7 and BY8 and inverted internal signals are supplied to AY07 to AY67 as unit codes. Is supplied.

Invert internal signal here Is formed by the Y-based redundant circuits YRC0 to YRC3 described below, and selectively goes to a low level when a defective address assigned to a corresponding redundant complementary data line and an address supplied at memory access do not match.

Each unit circuit of the Y predecoder PYAD has a circuit configuration as shown in FIG. 56, and is selectively operated according to the mat selection signals MSI and MSJ, i.e., MS0 to MS3. In this operation state, each unit circuit decodes a combination of the corresponding 2-bit internal address signals and corresponding inverted internal address signals. The predecode signals AY010 to AY013, AYO30 to AY033, AY050 to AY053 and AY070 to AY073 to AY610 to AY613, AY630 to AY633, AY650 to AY653, and AY670 to AY673 are alternatively set to the high level, provided that they are at the high level. Also, the corresponding inverted internal signal Does not form the corresponding predecode signal when the low level is reached, but instead the corresponding inverted internal signals YRMKB, that is, YR00B to YR03B to YR60B to YR63B, are alternatively set to low level. These predecode signals or inverted internal signals are supplied to the corresponding Y address decoders YA00 and YAD1 to YAD7.

3.2.15. Y-based redundant circuit

The dynamic RAM of this embodiment includes four sets of redundant complementary data lines as described above, and includes four Y redundant circuits YRC0 to YRC3 provided corresponding to these redundant word lines. Each Y-based redundant circuit includes YCMP with eight address comparison circuits provided corresponding to one redundant enable circuit YRE and internal address signals CY1 to CY8, as shown in FIG.

The dual redundant enable circuit YRE is a fuse that is selectively disconnected when the corresponding redundant complementary data line group is switched to the defective complementary data line group where a failure is detected, as illustrated in FIG. 59, that is, when the corresponding Y based redundant circuit becomes valid. Each of the means FUSE is included. When these fuse means fuses are disconnected, the output signal YREJ of each redundant enable circuit YRE, that is, the internal signals YRE0 to YRE3 is at a high level, and the YCMP is substantially operated with corresponding eight address comparisons.

On the other hand, the address inversely YCMP includes fuse means FUSE selectively cut when the corresponding bit of the bad address assigned to the corresponding Y-based redundant circuit is logic 1, as shown in FIG. In addition, the corresponding bit of the allocated bad address and the corresponding bit of the address supplied when accessing the memory, that is, the internal address signals CY1 to CY8 (in the case of YCMP6 to YCMP8 in comparison with addresses), are selectively enabled when the dynamic RAM becomes a ZIP package type. And a comparison circuit for comparing and combining the internal address signals CY6Z to CY8Z. In each address comparison, the YCMP is selectively operated when the corresponding internal signals YRE0 to YRE3 become high levels. In this operation state, each address comparison circuit selectively sets the output signal YRIJ to a low level provided that the corresponding address is inconsistent.

The output signal TRIJ of the YCMP is composed of eight address comparison circuits constituting each Y-based redundant circuit YRC, respectively, as shown in FIG. Becomes As a result, the inverted internal signal When the bad address assigned to the corresponding Y redundant circuit is inconsistent with the address supplied at the memory access, the low level is selectively lowered.

The Y-based redundant circuits YRC0 to YRC3 also have a fuse inspection function and a redundant inspection function similarly to the X-based redundant circuits XRC0 to XRC3. However, when the dynamic RAM enters the fuse check mode, a selection signal for alternatively designating the Y redundant circuits YRC0 to YRC3 is supplied to the latch FCE as the Y address signals Y2 to Y5 as shown in FIG. In addition, a fuse selection signal for alternatively designating a fuse of each Y-based redundant circuit, that is, a redundant enable circuit or an address comparison path, is used as the X address signal X4 or the Y address signals Y1 to Y8 as shown in FIG. It is supplied to YCMP by YRE or 8 address comparisons.

3.2.16. Address transition detection circuit

The address transition detection circuit ATD includes ten unit circuits ATD provided corresponding to the Y address signals Y0 to Y9, and a common I / O line precharge control circuit IOP and Y-based activation circuit YACT which are provided in common with these unit circuits. .

The dual common I / O line precharge control circuit IOP and the Y-based active circuit YACT are disposed almost at the center of the semiconductor substrate surface as shown in FIG. On the other hand, the unit circuit ATDs are distributed in close proximity to the corresponding address input pads, respectively, and as shown in FIG. 61, the output terminals of the unit circuit ATDs arranged in close proximity are in the form of wiring logic. It constitutes -ATD4. That is, the unit circuit group ATD0 includes three unit circuits ATD corresponding to pads A1 to A3 disposed on the lower left side of the semiconductor substrate surface as shown in FIG. 19, and the unit circuit group ATD1 is shown in FIG. As shown, seven unit circuits ATD corresponding to pads A4 to A7 and A6Z to A8Z are disposed on the lower right side. Similarly, the unit circuit group ATD2 includes two unit circuits ATD corresponding to pads A0 and A10 (or A9) disposed on the left middle side of the semiconductor substrate surface as shown in FIG. 17. As shown in the figure, pads A8 and A9 (or It includes two unit circuits ATD corresponding to). In addition, as shown in FIG. 15, the unit circuit group ATD4 includes the pad A9Z (or the upper right side of the semiconductor substrate). One unit circuit ATD corresponding to "

These unit circuits are provided in parallel between the output terminal ACB and the ground potential of the circuit as shown in FIG. 61, and the corresponding internal address signals are provided. And two sets of series N-channel MOSFETs each receiving the inversion delay signal or the inversion internal address signal CY1 and the inversion delay signal. These MOSFETs are temporarily turned on simultaneously when the corresponding internal address signal CY1 changes from low level to high level or from high level to low level to temporarily short between the corresponding output terminal ACB and the ground potential of the circuit. As a result, the output signals AT0 to AT4 of the unit circuit groups ATD0 to ATD4 are fixed at a high level when the dynamic RAM is not selected and the timing signals RG or R3 are at a low level. When the dynamic RAM is selected and the timing signal RG or R3 becomes high level, the timing signal RG or R3 is all low level, and then the output terminal ACB of one or several unit circuits ATD is coupled to the ground potential of the circuit. That is, each of the corresponding internal address signals is temporarily raised to a high level on the condition that they transition from a low level to a high level or from a high level to a low level.

The output signals AT0 to AT4 of the unit circuit groups ATD0 to ATD4 are concentrated in a common I / O line precharge control circuit IOP disposed at almost the center of the semiconductor substrate surface. As a result, as described above, any one of the output signals AT0 to AT4 becomes high level, so that the inverted internal signal IOPOB for precharging the common I / O line is selectively low level.

3.2.17. Common I / O Line Selection Circuit

A total of 32 sets of common I / O lines IOOL0 to IOOL3 and IOOH0 to IOOH3 to IO6L0 to IO6L3 and a total of 2 sets of 8 sets of complementary data lines, respectively, in a total of 4 memory arrays of two memory mats that are simultaneously selected. IO6HO to IO6H3 are coupled to the common I / O line selection circuits IOSO to IOS15 corresponding to two sets, respectively, as shown in FIG. 68, and through these common I / O line selection circuits, the corresponding eight main amplifiers MA0 to It is selectively connected to MA7.

Each common I / O line selection circuit may alternatively select any one of two sets of common I / O lines corresponding to the mat select signals MSI and MSJ, that is, MS0 to MS3 and the complementary internal address signal AY9U, as illustrated in FIG. Select and connect the corresponding main amplifiers MA0 to MA7. That is, when the corresponding mat selection signals MS0 to MS3 become high level and the inverted internal address signal AY9UB becomes high level, the complementary signal line HI or H0 coupled to the corresponding main amplifier is selected by selecting the common I / O line on the left side of the same drawing. To H7. When the corresponding mat selection signals MS0 to MS3 become high level and the non-inverting internal address signal AY9U becomes high level, the common I / O line on the right side of the same figure is selected and connected to the corresponding complementary signal lines H0 to H7. .

On the other hand, each common I / O line selection circuit has a complementary internal input data DHI supplied from the corresponding data input buffers DIB0 to DIB3 by supplying a high level internal signal ZWPI from the corresponding main amplifiers MA0 to MA7, that is, ZWP0 to ZWP7. A write signal according to DH0 to DH3 is formed and selectively transmitted to any one of the two sets of common I / O lines. At this time, the high level of these write signals is lowered by the threshold voltage of the N-channel MOSFET at the power supply voltage VCC of the circuit, and the low level becomes almost the ground potential of the circuit.

Each common I / O line selection circuit also has the function of equalizing two sets of common I / O lines when the corresponding mat selection signals MS0 to MS3 become low level or when the complementary internal signal CPU for precharging becomes logic 1. Have together.

3.2.18. Main amplifier

The dynamic RAM of this embodiment includes eight main amplifiers MA0 to MA7 as described above, and includes a main amplifier driving circuit MAD for transmitting various driving signals to these main amplifiers.

The main amplifiers MA0 to MA7 are provided corresponding to the complementary signal lines H0 to H7 as illustrated in FIG. 69, and have a basic configuration of two pairs of static amplifiers which are respectively coupled in series. These main amplifiers are selectively supplied according to the selection signal AXYI supplied from the nibble counter NBC, that is, AXY0 to AXY3 and the complementary internal address signal AY0 of the least significant bit when the low-level inversion driving signal MADB is supplied from the main amplifier driving circuit MAD. It becomes a high level. Here, the inversion drive signal MADB is temporarily low level as a trigger of a low level change of the inverted internal signal CPOB for precharge when the timing signal RG becomes high level as shown in FIG. The select signals AXY0 to AXY3 are all fixed at a high level when the dynamic RAM has an x4 bit configuration, and are selectively at a high level according to the output signal of the nibble counter NBC when the x1 bit configuration is used.

At this time, if the dynamic RAM is in nibble mode, the output signal of the nibble counter NBC first becomes high level in accordance with the most significant bit X address signal X10 and Y address signal Y10 as described below, and then the high level is applied to the nibble operation. Correspondingly shifted sequentially. However, in the fast page mode or the static column mode, the nibble counter NBC does not perform a shift operation but actually functions as a decoder. That is, when the dynamic RAM has an x4 bit configuration, the main amplifiers MA0 to MA7 are selectively and simultaneously operated four by four in accordance with the complementary internal address signal AY0 of the least significant bit. At this time, each of the main amplifiers is selectively formed by four of the internal signals ZWP0 to ZWP7 for write at the same time and in accordance with the corresponding internal mask data MKBI, that is, MKB0 to MKB3.

On the other hand, when the dynamic RAM has an x1 bit configuration, and enters the nibble mode, the main amplifiers MA0 to MA7 are likewise selectively operated at the same time by four. The output signals of these main amplifiers are alternatively output in accordance with the corresponding selection signals AXY0 to AXY3 as described below. In this nibble mode, the internal signals ZWP0 to ZWP7 for writing are alternatively formed in accordance with the selection signals AXY0 to AXY3. However, when the dynamic RAM has an x1 bit configuration and is in the fast page mode or the static column mode, the main amplifiers MA0 to MA7 are selectively operated according to the complementary internal address signals AY0 and the selection signals AXY0 to AXY3. At the same time, corresponding internal signals ZWP0 to ZWP7 for writing are alternatively formed.

The main amplifiers MA0 to MA7 also have a function of equalizing the complementary input node, the complementary output node and the complementary coupling node of the two pairs of static amplifiers according to the complementary internal signal EQ, that is, the complementary internal signal CPU for precharging.

Complementary output terminals M0I, M00 to M07, of main amplifiers MA0 to MA7 are selectively connected to complementary input terminals CBI, namely CB0 to CB3, of data output buffers DOBO to DOB3 via corresponding coupling circuits CBS0 to CBS7 as shown in FIG. Combined. At this time, the output signal of each main amplifier is selectively transmitted in synchronization with the inverted internal signal DSB for the data strobe and in accordance with the selection signals AXY0 to AXY3 and the complementary internal address signal AY0 of the least significant bit. Further, the complementary input terminals of the data output buffers CB0 to CB3 are logically coupled to the corresponding complementary output terminals of the test logic circuits SX4T and SX1T of the test mode control circuit TST as described below.

3.2.19. Nibble counter

The nibble counter NBC includes a 4-bit unit circuit that constitutes a ring-shaped shift register by being coupled in series as shown in FIG. These unit circuits each include a master latch and a sleeve latch that are coupled in series, perform an initial set operation in accordance with the internal signal SS, and perform a shift operation in accordance with the internal signal SR. That is, when the internal signal SS goes low level, the sleeve latch of each unit circuit may alternatively be output according to the X address signal X10 of the most significant bit, that is, the internal address signal AX10 and the Y address signal Y10 of the most significant bit, that is, the internal address signal CY10. Is initially set to become high level. This high level is transferred as the output signal of each unit circuit as it is when the dynamic RAM enters the fast page mode or the static column mode. However, in the nibble mode, the initial set is fixed by the internal signal YL being high level and the internal signal SS being high level, and the inside of the nibble counter NBC is shifted in a ring shape in accordance with the internal signal SR.

As described above, by making the nibble counter NBC a shift register type, the selection operation can be speeded up, and the data rate of the dynamic RAM in the nibble mode can be increased.

The output signals of the unit circuits of the nibble counter NBC are supplied to the main amplifiers MA0 to MA7 and the coupling circuits CBS0 to CBS7 as the selection signals AXY0 to AXY3. These output signals are fixed to the power supply voltage VCC, i.e., high level, of the circuit when the dynamic RAM has an x4 bit configuration as described above.

3.2.20. Data input buffer

The dynamic RAM of this embodiment is provided with four data input buffers DIB0 to DIB3, which are selectively used according to its bit configuration. That is, when the dynamic RAM is x4 bit configuration, all data input buffers DIB0 to DIB3 are used. At this time, the input terminal of each data input buffer is coupled to the corresponding data input / output terminals I / O1 to I / O4, respectively. On the other hand, when the dynamic RAM has an x1 bit configuration, only one data input buffer DIB1 is used, and the other three data input buffers are not used. At this time, the input terminal of the data input buffer DIB1 is coupled to the data input terminal Din.

The data input buffers DIB0 to DIB3 each include one data latch holding corresponding input data and one mask data latch holding corresponding mask data as illustrated in FIG. The double data latch fetches the corresponding input data according to the internal signal DL for data latch, and holds this. The output signals of these data latches are supplied to the corresponding common I / O line selection circuits IOS0 to IOS15 as the complementary internal input data DH1 or DH0 to DH3. On the other hand, the mask data latch of each data input buffer fetches and holds corresponding mask data in accordance with the internal signal WB for mask data latch when the dynamic RAM is selected in the write cycle of the mask write mode. The output signals of these mask data latches are supplied to the corresponding main amplifiers MA0 to MA7 as the internal mask data MKBO to MKB3.

3.2.21. Data output buffer

The dynamic RAM of this embodiment has four data output buffers DOB0 to DOB3, which are selectively used according to its bit configuration. That is, all data output buffers DOB0 to DOB3 are used when the Diana RAM has an x4 bit configuration. At this time, the output terminal of each data output buffer is coupled to the corresponding data input / output terminals I / O1 to I / 04, respectively. On the other hand, when the dynamic RAM has an x1 bit configuration, only one data output buffer DOB2 is used, and the other three data output buffers are not used. At this time, the output terminal of the data output buffer DOB2 is coupled to the data output terminal Dout.

As shown in FIG. 71, the data output buffers DOB0 to DOB3 each include an output latch formed by cross-connecting two clock inverter circuits which are selectively transferred in accordance with the inverted internal signal OLB for output data latch. The complementary input and output nodes of this output latch are further coupled to the other input terminals of a pair of two input NAND gate circuits which are gate controlled in accordance with the internal signal DOE for data output. The output signals of these NAND gate circuits are inverted by the corresponding pair of inverter circuits and then selectively transferred to the gates of the pair of output MOSFETs of the corresponding pair of output MOSFETs or data output buffer DOB2.

In this embodiment, the data output buffers DOB0 to DOB3 have an equalization circuit provided between the non-inverting and inverting input / output nodes of the output latch. These equalizing circuits include the inverted internal signal OLB and the inverted internal signal for the data strobe described above. When both are high, short the non-inverting and inverting I / O nodes of the output latches to the ground potential of the circuit. As a result, the inversion operation of the output latch is speeded up, and in particular, the data rate of the dynamic RAM in nibble mode, static column mode or fast page mode is speeded up.

3.2.22. Input protection circuit

The dynamic RAM of this embodiment is not particularly limited, but includes a plurality of input protection circuits provided corresponding to the input bonding pads.

92 to 97 show the layout of the first sixth embodiment of the input protection circuit used in this dynamic RAM. 89 and 90 show equivalent circuit diagrams of the input protection circuits of FIGS. 92 through 96 and 97, respectively. FIG. 98 shows an example of the layout of the conventional input protection circuit used in the conventional dynamic RAM and the like, and FIG. 91 shows the equivalent circuit diagram. Based on these drawings, an outline of the configuration and operation of each embodiment of the input protection circuit and its features will be described.

In FIG. 92, the input protection circuit includes an N ⁺ diffusion layer (hereinafter referred to as a diffusion layer only) provided corresponding to each input pad PAD, that is, an input diffusion layer L1 (first diffusion layer). The input diffusion layer L1 is coupled to the corresponding pad PAD via a corresponding metal wiring layer, that is, aluminum wiring layer AL1 and a contact CONT. The input diffusion layer L1 is coupled to the drain region D of the clamp MOSFET QC1 of the same figure through the diffusion layer Lr and the aluminum wiring layer AL1 constituting the protection resistor R1 of FIG. 89, and to the input terminal of the corresponding internal circuit. A parasitic diode D1 of FIG. 89 is equivalently formed between the protection resistor R1 and the semiconductor substrate SUB, and a parasitic diode D2 is formed between the clamp MOSFET QC1 and the semiconductor substrate SUB.

In this embodiment, the aluminum wiring layer AL1 for coupling the diffusion layer Lr and the drain region D of the clamp MOSFET is formed over the almost entire upper layer of the drain region D of the clamp MOSFET QC1 and is coupled to the drain region D through several contacts. . Similarly, the source region S of the clamp MOSFET QC1 is also coupled to the ground potential VSS of the circuit via the aluminum wiring layer AL1 formed over almost the entire layer and several contacts. As a result, the connection resistance of the coupling node in each region is reduced, and a stable clamp MOSFET can be formed.

The input protection circuit is also provided in close proximity to the input diffusion layer L1 and in close proximity to the input diffusion layer L1 like the diffusion layers L2 and L2 '(second diffusion layer) which are coupled to the power supply voltage VCC of the circuit via corresponding aluminum wiring layers AL1 and contacts. And a diffusion layer L3 (third diffusion layer) which is coupled to the ground potential VSS of the circuit via a corresponding aluminum wiring layer AL1 and several contacts. Well regions NWELL are formed in the periphery of the input diffusion layer L1 and the front edges of the diffusion layers L2, L2 'and L3 to surround the input diffusion layer L1. The diffusion layers L2 and L2 'together with the input diffusion layer L1 constitute the lateral biplane transistor BT1 of FIG. Similarly, the diffusion layer L3 forms the lateral bipolar transistor BT2 of FIG. 89 together with the input diffusion layer L1. These transistors are turned on when the parasitic diode D1 or the like breaks down and the potential of the semiconductor substrate SUB rises when the spike noise is input through the corresponding pad PAD, and the spike noise is rapidly turned on by the power supply voltage supply point of the circuit. Or absorbs into the ground potential supply point.

As a result, the input protection circuit of this embodiment increases the surge absorption effect on the power supply voltage VCC and the ground potential VSS of the circuit as compared with the conventional input protection circuit. In addition, by forming a well region so as to surround the input diffusion layer L1, it is possible to prevent breakage of the input diffusion layer L1 at the time of breakdown, and to suppress surge absorption to the semiconductor substrate SUB and to suppress variation in the substrate potential. There is a number.

In FIG. 93, the input protection circuit includes the input diffusion layer L1 and the input diffusion layer L1 (first and fourth diffusion layers) with a predetermined well region interposed between the diffusion layers L2 and L3 constituting the lateral bipolar transistors BT1 and BT2. Diffused layer L5 (fifth diffused layer) formed to face each other). The well region provided between the input diffusion layer L1 and the diffusion layer L5 acts as a well resistance to form the negative of the protection resistor R1 of FIG. 89, that is, the first protection resistance.

The diffusion layer L5 is coupled to the polysilicon resistor R2 (second protection resistor) via the corresponding aluminum wiring layer AL1 and to the drain region D of the clamp MOSFET QC1. The polysilicon resistor R2 constitutes the protection resistor R1 of FIG. 89 together with the well resistance, that is, the first protection resistor.

In this embodiment, the lateral bipolar transistors BT1 and BT2 are configured between the input diffusion layer L1 and the diffusion layers L2 and L3, that is, between the pad PAD and the power supply voltage VCC and the ground potential VSS of the circuit, so that the same effects as in the first embodiment can be obtained. Obtained. In addition, by forming the protection resistor R1 by the well resistance, the area required for the grayout can be reduced, and a well region provided between the input diffusion layer L1 and the diffusion layer L5 is not formed at the rear edge of the diffusion layer L5. The junction concentration gradient between the substrate SUB and the diffusion layer L5 is steep, and the breakdown voltage of the parasitic diode D1 is reduced.

In FIG. 94, the input diffusion layer L1 is formed relatively thin and long, and the aluminum wiring layer AL1 and the contact for coupling the input diffusion layer L1 and the corresponding pad PAD are formed inside except the periphery of the input diffusion layer L1. Underlying these contacts, well regions are formed to surround the bottom of the contacts. This increases the internal pressure of the diffusion layer under the contact.

The input diffusion layer L1 is further coupled to the diffusion layer L4 (fourth diffusion layer) constituting the well resistance NWr together with the diffusion layer L5 (the fifth diffusion layer) via the corresponding aluminum wiring layer AL1.

The diffusion layer L5 is coupled to the drain region D of the clamp MOSFET QC1 and to the input terminal of the corresponding internal circuit. In this embodiment, the protection resistor R1 is composed of only the well resistance NWr. As a result, the layout area required for the protection resistor R1 is further reduced.

On the other hand, the diffusion layer L2 constituting the lateral bipolar transistor BT1 together with the input diffusion layer L1 is formed to surround the upper half of the input diffusion layer L1, and the diffusion layer L3 constituting the lateral bipolar transistor BT2 together with the input diffusion layer L1 has the lower half. It is formed to surround. The aluminum wiring layers AL1 and the contacts for coupling these diffusion layers L2 and L3 with the power supply voltage VCC and the ground potential VSS of the circuit are formed on the inner side except for the front edge of each diffusion layer. In this manner, the breakdown voltage of the parasitic diode D1 is reduced and the ON resistances of the lateral bipolar transistors BT1 and BT2 are reduced.

In the embodiment of FIG. 95, a well region is added to the input diffusion layer L1 and the front edge portions of the diffusion layers L2 and L3 of FIG. In the embodiment of FIG. 96, a well region is further added to the lower layers of the diffusion layers L2 and L3 of FIG. As a result, damage to the diffusion layers L1 to L3 due to overcurrent during breakdown can be prevented.

In FIG. 97, the aluminum wiring layer AL1 for coupling the pad PAD corresponding to the input diffusion layer L1 in FIG. 94 is formed over the upper part of the front edge portions of the diffusion layers L2 and L3. Therefore, between the input diffusion layer L1 and the diffusion layers L2 and L3, that is, between the corresponding pad PAD and the power supply voltage VCC and the ground potential VSS of the circuit, two aluminum parasitic MOSFETs having the aluminum wiring layer AL1 as the gate region, that is, the clamp MOSFET at 90 degrees QC4 and QC5 are equivalently formed, respectively.

On the other hand, the aluminum wiring layer AL1 for coupling the diffusion layers L2 and L3 and the power supply voltage VCC or the ground potential VSS of the circuit is formed over the upper part of a part of the opposing front edge portion of the input diffusion layer L1, respectively. For this reason, between the diffusion layers L2 and L3 and the input diffusion layer L1, i.e., between the power supply voltage VCC and the ground potential VSS of the circuit and the corresponding pad PAD, two aluminum parasitic MOSFETs having the gate area AL1 as the gate region, that is, the clamp MOSFETs of FIG. QC2 and QC3 are each formed equivalently.

In this, the spike noise input to the corresponding pad PAD is absorbed through the clamp MOSFET having a relatively large threshold voltage to secure the large supply voltage VCC or the large ground potential VSS characteristic of the input protection circuit.

3.2.23. Timing generating circuit

The dynamic RAM of this embodiment includes a timing generation circuit TG for forming various timing signals for controlling the operation of the respective circuits. The timing generating circuit TG is not particularly limited, but the row address strobe signal. Prepared in response to System control circuit RTG and column address strobe signal Prepared in response to System control circuit CTG and write enable signal Prepared in response to System control circuit WTG. The timing generation circuit TG also includes a data output control circuit OTG for controlling the output operation of the dynamic RAM and a mode control circuit MOD for managing the operation mode thereof. Hereinafter, the structure and operation of each part of the timing generation circuit TG according to FIGS. 42, 43, 55, 64, 65, 66, 75, and 76 will be described. It demonstrates. Please refer to the timing diagrams of FIG. 80 and FIG. 81 in the description of these.

(One) System control circuit

Timing Generation Circuit of TG The system control circuit RTG is a low address strobe signal supplied as a control signal from the outside as shown in FIG. The timing signals R1, R2, R3, RG and P2, and XDP and XP are formed based on the above.

Dual timing signal R1 is a row address strobe signal The timing signal R2, the XDP, and the like are formed in accordance with the timing signal R1.

In the dynamic RAM, the X address signals X0 to X10 are fetched into the X address buffer XAB in accordance with the timing signal R1, and the precharge operation of the X address decoder XAD is stopped in accordance with the timing signal XDP. As a result, the decoding operation of the X address decoder XAD is substantially started, and the word line selection operation is executed. The drive signal of the word line is monitored by the word line monitor circuit as described above so that its output signal, i.e., the internal signal XM, It is fed back to the system control circuit RTG.

The internal signal XM is delayed through the delay circuits XDLY3 to XDLY5 in series form and transmitted through two sets of word line monitor circuits, and then combined under a predetermined logic condition to form an inverted timing signal R3B. In this embodiment, the word line monitor circuit to which the internal signal XM is transmitted has different transfer characteristics due to the high or low logic threshold level of the inverter circuit provided at the rear end of the word line for monitoring. Several propagation paths of the internal signal XM including these word line monitor circuits are selectively laser trimmed at cut points indicated by zero marks in the same drawing to set appropriate delay times. Further, the trailing end node of each cutting point is coupled to the semiconductor substrate SUB via the N ⁺ well region. As a result, the node whose corresponding cutting point is cut by the laser is discharged through the corresponding well region to reach a low level.

By the way, the word lines constituting the memory array of the dynamic RAM are so-called divided word lines, separated in the extending direction, and also divided into multiple divided word lines and aluminum wiring layers formed by polysilicon or polysides or silicides. The main word line is formed by a metal wiring layer, such as a plurality of divided word lines. Therefore, the transmission speed of the drive signal in each word line depends on the divided word lines having a relatively large distribution resistance value, so that the driving state of the word lines can be checked equivalently by monitoring the drive signals transferring on the divided word lines. There is a number. For this reason, in the word line monitor circuit of this embodiment, a monitor word line corresponding to one-half the length of the divided word line is provided, and a word is appropriately measured in the time period for the internal signal XM to be transmitted in these monitor word lines. It is determined that the drive operation of the line is finished.

In this embodiment, the two monitor word lines are arranged at the same pitch as the actual word lines constituting the memory array, with dummy word lines interposed therebetween, and the same dummy words on the outside thereof as shown in FIG. Each line is placed.

As a result, the monitor word line has a transfer characteristic close to the actual word line constituting the memory array, and as a result, the monitor precision of the word line monitor circuit is improved.

(2) System control circuit

Timing Generation Circuit of TG The system control circuit CTG is a column address strobe signal supplied as a control signal from the outside as shown in FIG. The timing signals C1, C2, etc. are formed based on the above. The timing signal C1 and Internal signals RN, RF and CBR are formed based on the timing signals R1 and R3 formed by the system control circuit RTG.

Dual timing signal C1 is column address strobe signal Is formed according to the timing signal C1.

On the other hand, the internal signal RN is subject to the timing signal C1 being low level at the time when the timing signal R1 becomes high level, that is, the column address strobe signal. Low address strobe signal The high level is selectively provided provided that the low level is not set before the low level. Further, the internal signals RF and CBR are conditional on the timing signal C1 being high level when the timing signal R1 becomes high level, that is, the column address strobe signal. Low address strobe signal A high level is optionally provided on condition that it is low level before. These internal signals are supplied to the mode control circuit MOD of the timing generating circuit TG and used for setting the operation cycle of the dynamic RAM.

(3) System control circuit

Timing Generation Circuit of TG The system control circuit WTG is a write enable signal supplied from the outside as shown in FIGS. 64 and 65. The timing signals W1 to W3 and WYP are formed based on. In addition, the internal signals RW are formed and the timing signals CE, YL, DL, and ODCB are formed.

Among these, the timing signals W1 and W2 are write enable signals. Are sequentially formed in accordance with the timing signal W2 and The timing signal WYP is formed based on the timing signal C2 supplied from the system control circuit CTG. This timing signal WYP is used as a write pulse for controlling the write operation of the dynamic RAM.

Next, the internal signal RW is equal to the timing signal W1. It is formed based on the timing signals R1 and R3 supplied from the system control circuit RTG. The internal signal RW is a write enable signal provided that the timing signal W1 is at a high level when the timing signal R1 is at a high level. Low address strobe signal A high level is optionally provided on condition that it is low level before. The internal signal RW is supplied to the mode control circuit MOD and used to set the operation cycle of the dynamic RAM.

The timing signal CE It becomes high level according to the timing signal RG supplied from the system control circuit RTG, and becomes low level according to the timing signal R1. This timing signal CE Used as enable signal of system. On the other hand, the timing signal YL is formed in accordance with the timing signal C2 or W3. The timing signal YL is supplied to the Y address buffer YAB and used for the fetch operation of the Y address signals Y0 to Y10.

The timing signal DL is formed in accordance with the timing signals C2 and W2 or W3 and is used for the fetch operation of write data for the data input buffers DIB0 to DIB3. Incidentally, the timing signal ODCB is formed in accordance with the timing signal DL and the timing signal CE and used for the output control operation.

(4) data output control circuit

As shown in Figs. 65 and 66, the data output control circuit OTG of the timing generating circuit TG has the internal signals DS0 and CPUB supplied from the main amplifiers MA0 to MA7 described above. Timing signal C1 (output enable signal in x4 bit configuration) supplied from the system control circuit CTG ), The inversion timing signals DSB and OLB and the timing signal DOE are formed.

The double inversion timing signal DSB becomes a one short pulse formed at the rising edge of the internal signal DS0 and is used as a strobe signal of the internal output data for the data output buffers DOB0 to DOB3. The inversion timing signal OLB is formed in accordance with the inversion timing signal DSB and the internal signal CPUB to be used to control the operation of the output latches of the data output buffers DOB0 to DOB3. When the inversion timing signals DSB and OLB become high together, non-inverting of the output latch and equalization of the inverting input / output nodes are performed in the data output buffers DOB0 to DOB3.

On the other hand, the timing signal DOE is a write enable signal. Becomes high level, i.e., when the dynamic RAM becomes a read cycle, it becomes high level according to the timing signal C1. This timing signal DOE is used to control the output operation of the data output buffers DOB0 to DOB3.

(5) mode control circuit

The mode control circuit MOD of the timing generating circuit TG is an operating mode of the dynamic RAM as the bonding pads FP0 and FP1 are selectively bonded to the ground potential VSS or the power supply voltage VCC of the circuit as shown in FIGS. 75 and 76. Set. In addition, the internal signal WB is formed based on the internal signals RN and RW described above, and a predetermined test signal or test voltage is supplied through the test pads FCK, RCK, ICT, and VCF. Set it.

The mode control circuit MOD also has a function of switching the package type of the dynamic RAM by selectively bonding the pad ZIP to the power supply voltage VCC of the circuit.

In FIG. 75, the mode control circuit MOD sets both the inverted internal signals FP0EB and FP1EB to high levels when the pads FP0 and FP1 are both open. For this reason, the dynamic RAM enters the fast page mode as shown in Table 6 above. Next, when only pad FP0 is bonded to the ground potential of the circuit, the inverted internal signal FP0EB goes low. For this reason, when the x1 bit configuration, the internal signal NE is at a high level, the dynamic RAM is in nibble mode, and when the x4 bit configuration is, the internal signal MWE is at a high level, and the dynamic RAM is in the mask light mode. On the other hand, when only the pad FP1 is bonded to the power supply voltage VCC of the circuit, the inverted internal signal FP1EB becomes low level.

For this reason, provided that the internal signal SCB is at a low level, provided that the internal signal NE is at a low level, the dynamic RAM is in a static column mode.

As shown in FIG. 75, the internal signal WB is provided with the internal signal MWE and RW and the inverted internal signal TEB at high level, and the internal signal RN is at high level, that is, the dynamic RAM is in the mask light mode. Also, low address strobe signal when not in test mode Go light enable signal Slower, but also column address strobe signal The condition is to go to a low level before the condition, and optionally to a high level. This internal signal WB is supplied to the data input buffer DIB and used for the fetch operation of mask data in the mask write mode.

The mode control circuit MOD enables the fuse inspection test with the internal signal FCK at a high level by supplying the circuit power supply voltage VCC to the pad FCK. At this time, a predetermined fuse test power supply voltage is used for the pad VCF as described above. On the other hand, the mode control circuit MOD enables the redundancy inspection test by setting the internal signal RCK to a high level by supplying the power supply voltage VCC of the circuit to the pad RCK. In addition, by supplying the power supply voltage VCC of the circuit to the pad ICT, the operation of the reference potential generation circuit VL and the substrate back bias voltage generation circuit VBBG is selectively stopped with the internal signal ICT at a low level. As a result, the standby current of the dynamic RAM can be stopped and the leakage current can be confirmed due to a circuit failure.

The mode control circuit MOD sets the internal signal ZIP to a high level by bonding the pad ZIP to the power supply voltage VCC of the circuit. In the X address buffer XAB and Y address buffer YAB of the dynamic RAM and the CAS system control circuit CTG of the timing generating circuit TG, the internal signal ZIP becomes high level so that the input buffer provided corresponding to the ZIP package type is operated. The corresponding pad is selectively enabled. As a result, the package type of the dynamic RAM is switched and efficient deployment is achieved.

The mode control circuit MOD includes, but is not particularly limited to, the voltage generating circuit HVC, the reference potential voltage generating circuit VL, and the signature output circuit SIG. The dual voltage generation circuit HVC forms a constant voltage HVC which is one half of the power supply voltage VCC of the circuit. The constant voltage HVC is supplied to the precharge circuit of the sense amplifier and the like and to the memory cells constituting the memory array at the plate voltage VPL. As described above, the plate voltage VPL is selectively switched to the power supply voltage VCC or ground potential VSS of the circuit when the dynamic RAM enters the vendor test mode and also enters the VPL stress mode.

3.2.24. Test mode control circuit

The dynamic RAM has various test modes as described above, and has a test mode control circuit TST for selectively executing these test modes.

The test mode control circuit TST is a high voltage for identifying that a predetermined high voltage SVC exceeding the power supply voltage VCC of the circuit is supplied to the data output terminal Dout (data input / output terminal I / O3 in the case of x4 bit configuration) as shown in FIG. A set for determining the set cycles and reset cycles of each test mode on the basis of the detection circuit SCV, the output signal of this high voltage detection circuit SVC, that is, the internal signal SVC and the internal signals RF, RW, timing signals R1, RG, C1 described above. The cycle determination circuit FSR and the reset cycle determination circuit FR are provided.

Among these, the high voltage detection circuit SVC selectively sets the output signal, that is, the internal signal SVC, to a high level when a high voltage such as + 10V is supplied to the data output terminal Dout (or data input / output terminal I / O3).

The set cycle determination circuit FSR then outputs its output signal, i.e., the internal signal FSR, provided that the timing signal R1 goes low and the internal signals RF and RW go high together, i.e., the dynamic RAM goes to WCBR cycle. May be selectively set to a high level according to the internal signal SVC, or the inverted internal signal TEB may be selectively set to a low level. That is, the set cycle determination circuit FSR identifies the WCBR, and also determines the vendor test mode of the dynamic RAM when the internal signal SVC becomes high level, and sets the internal signal FSR to high level. On the other hand, the WCBR is identified, and when the internal signal SVC goes low, the open test mode of the dynamic RAM is determined and the internal signal TEB is made low. These internal signals FSR and TEB are reset when the output signal of the reset cycle determination circuit FR, i.e., the inverted internal signal FRB goes low.

On the other hand, the reset cycle determination circuit FR has the internal signal RF going to a high level when the timing signal RG goes to a high level, and the dynamic RAM becomes a CBR regeneration cycle, provided that the internal signal RW is at a low level. On the condition that it is at a high level, or at the rising edge of the timing signal R1, the timing signal C1 is at the low level, and the timing signal R1 is at the falling edge, that is, the dynamic RAM becomes a RAS only regeneration cycle, and the timing signal R1 The output signal, i.e., the inverted internal signal FRB, is selectively set to the low level on the condition that the low level is reached. As described above, the inverted internal signal FRB becomes low level, thereby canceling the vendor test mode and the open test mode of the dynamic RAM.

However, when the internal signal FSR becomes high, the test mode control signal TST fetches a test mode setting signal for specifying the details of the vendor test mode as shown in FIG. That is, in the vendor test mode, as described above, the address signals A0 to A10 (or the output enable signal). ), I.e., internal address signals AY0 to AY10 (or OB) or BY0 to BY10, and the test mode setting signal is supplied. Based on this, the test contents of the dynamic RAM are set in accordance with Table 8 above. Therefore, if the inverted internal address signal AYOUB is at a low level, the internal signal BTE for specifying the 8-bit simultaneous lead test is at a high level, and if the inverted internal address signal AY9UB is at a low level, the internal signal TRI for specifying a ternary test is at a high level. The combination of these internal signals BTE and TRI optionally specifies an 8-bit simultaneous lead test of the binary or ternary output of the dynamic RAM. On the other hand, when the internal address signal BYI is at a low level, the internal signal VPLL for designating the VPL stress mode 1 is at a low level. When the internal address signal BY2 is at a high level, the internal signal VPLH for designating the VPL stress mode 2 is at a low level. When the internal address signal AYIO (or OEOB) is at a high level, the internal signal VBS for designating the VBB stop mode becomes the whale bell.

The test mode control circuit TST combines the read data output via the main amplifiers MAO to MA7 in the 8-bit simultaneous read test, and provides four test data combination circuits SX4T for transferring the result to the corresponding data output buffers DOBO to DOB3. And one test data combination circuit SXIT. The outputs of these test data combination circuits are logically coupled to the complementary input terminals of the corresponding data output buffers DOBO to DOB3 together with the output terminals of the coupling circuits CBSO to CBS7 described above.

The test data combination circuit SX4T is selectively operated when the dynamic RAM has an x4 bit configuration as shown in FIG. 73, and the complementary output signals M00 and the corresponding two main amplifiers MA0 and MA1 to MA6 and MA7. MO1 to MO6 and MO7 are received and the complementary output signals CB0 to CB3 are selectively formed. In other words, when the dynamic RAM has an x4 bit configuration and is in the open test mode or the vendor test binary test mode, the test data combination circuit SX4T logic the complementary output signal if the corresponding 2 bits of read data match. If it does not match, the complementary output signal is set to logic 0. However, when the dynamic RAM has an x4 bit configuration and the vendor test ternary test mode, if the corresponding 2 bits of read data match, the complementary output signal is set to logic 1 or logic 0 according to the read data. If there is a mismatch, the complementary output signal is placed in a high impedance state.

On the other hand, the test data combination circuit SX1T is selectively operated when the dynamic RAM has an x1 bit configuration as shown in FIG. 73, and receives the complementary output signals M00 to M07 of the eight main amplifiers MA0 to MA7. Complementary output signal CB2 is selectively formed. In other words, when the dynamic RAM has an x1 bit configuration and is in the open test mode or the binary test mode of the vendor test, the test data combination circuit SX1T logic the complementary output signal CB2 when all 8 bit read data match. If it is inconsistent, the complementary output signal CB2 is logical 0. However, when the dynamic RAM has a x4 bit configuration and the vendor test ternary test mode, if all 8 bits of read data match, the complementary output signal CB2 is set to logic 1 or logic 0 according to the read data. If there is a mismatch, the complementary output signal CB2 is placed in a high impedance state.

3.2.25. Substrate back bias voltage generation circuit

The dynamic RAM mounts the substrate back bias voltage generation circuit VBBG which forms the substrate back bias voltage VBB which becomes a predetermined negative voltage based on the power supply voltage VCC of the circuit.

The substrate back bias voltage generation circuit VBBG is not particularly limited, but as shown in FIG. 77, one level detection circuit LVM and two oscillation circuits OSC1. OSC2 and three voltage generation circuits VG1 (first voltage generation circuit), VG2 (second voltage generation circuit), and VG3 (third voltage generation circuit) are provided.

The level detection circuit LVM is selectively put into an operational state by supplying a high level internal signal ICT from the above-described test mode control circuit TST. In this operation state, the level detection circuit LVM identifies that the absolute value of the substrate back bias voltage VBB is less than or equal to the predetermined value, and selectively sets the source signal, that is, the internal signal VBI, to a high level. The internal signal VB1 is forced to a high level irrespective of the value of the substrate back bias voltage VBB due to the dynamic RAM being selected and the timing signal RI described above being high.

The oscillator circuit OSC1 includes five CMOS logic gate circuits that constitute one ring oscillator by being coupled in a ring shape. The ring oscillator is selectively operated in the condition that the internal signal VBI is at a high level and the internal signal VBS is at a low level, thereby forming a pulse signal having a predetermined frequency. The pulse signal is supplied to the voltage generator circuit VGI after passing through the inverter circuit of 9 stages in series and through the inverter circuit of 6 stages, and to the voltage generator circuit VG2 via the inverter circuit of 5 stages. As a result, the pulse signals supplied to the voltage generating circuits VG1 and VG2 have a phase difference of 180 degrees.

The voltage generating circuits VG1 and VG2 each include a predetermined boost capacitance and form a substrate back bias voltage VBB corresponding to the corresponding pulse signal. Since these pulse signals have a phase difference of 180 degrees as described above, the variation of the substrate back bias voltage VBB is suppressed and the operation of the dynamic RAM is further stabilized.

On the other hand, the oscillator circuit OSC2 has the same circuit configuration as the oscillator circuit OSC1, and is normally operated on the condition that the internal signal ICT is at a high level. In the movable operation state, the oscillator circuit OSC2 forms a pulse signal having a predetermined frequency and supplies it to the voltage generating circuit VG3.

The voltage generating circuit VG3 has the same circuit configuration as the voltage generating circuits VG1 and VG2, and forms the substrate back bias voltage VBB based on the pulse signal supplied from the oscillating circuit OSC2. It is designed to have a small current supply capability compared to the voltage generating circuits VG1 and VG2.

100, another embodiment of the present invention is shown. Before explaining this embodiment, a semiconductor device having a dynamic RAM devised by the inventors prior to the present invention will first be described according to FIG.

Consider a semiconductor device in which a dynamic memory cell region is disposed at both ends of a long side on a rectangular chip, and peripheral circuits are respectively disposed at the center thereof. An example of this semiconductor device is shown in FIG.

In the same drawing, reference numeral 1 denotes a rectangular chip, and dynamic memory cell regions D1 and D2 are formed at both ends in the longitudinal direction of the chip 1, and peripheral circuits C1 indicated by dashed lines are formed at the center thereof, respectively. The memory cells in the dynamic memory cell regions D1 and D2 are arranged in an array shape, and word lines (not shown) provided therein are arranged on the short sides (left and right directions in FIG. 105) of the chip 1. They are arranged so as to be balanced (the data lines are parallel to the long sides of the chip 1). (2) shows an I / O pad formed at both corners of one end of the long side direction of the chip 1 (up and down in Fig. 105), and (3) an address of an input formed at the corner of the other end. The pads are shown respectively, and the address pad 3 and the I / O pad 2 are connected by I / O lines 4 and 5, respectively. The I / O lines (4) and (5) are lines for passing data read from the memory cells in the memory cell areas D1 and D2, respectively, in the memory cell areas D1 and D2. It is provided in parallel with the word line formed.

As described above, in the semiconductor device shown in FIG. 105, the memory cells in the dynamic memory cell regions D1 and D2 are arranged so that the word lines disposed therein are parallel to the short sides of the chip 1, that is, horizontally.

However, the present inventors have found that the following problems exist in the 105th semiconductor device.

That is, in the case where the memory cells are arranged horizontally as described above, the I / O lines 4 and 5 passing through the memory cell regions D1 and D2 must be arranged along the word lines, and I Since the / O pads 2 and the address pads 3 are formed at both ends of the long side of the chip 1, the chips of the I / O lines 4 and 5, as shown in FIG. In the short side direction of (1), the length between both ends of the short side direction of the chip | tip 1 of the memory cell area | region D1 and D2 of both is required at least, and I / O line (4), At least one of (5) (the I / O line 5 in Fig. 105) needs to be disposed unnecessarily in the short-side direction of the chip 1, resulting in a delay in address access speed. .

So in this embodiment it is arranged as follows. That is, a dynamic memory cell region at each end of the long side of the rectangular chip has peripheral circuits formed at its center, respectively, and connects I / O pads and address pads formed at both ends of the long side of the chip, respectively. The dynamic memory cell region of the semiconductor device having an I / O line disposed in parallel with the word line formed in the dynamic memory cell region in the dynamic memory cell region is formed such that the word line is parallel with the long side of the chip.

As a result, the dynamic memory cell region is formed so that the word line is parallel to the long side of the chip, so that the I / O lines arranged parallel to the word line in the dynamic memory cell region are also arranged parallel to the long side of the chip in this region. By connecting the I / O lines in the memory cell area dividedly arranged at both ends in a straight line, the length in the long side direction of the chip of the I / O line is not different from that in FIG. The length of the I / O line is shorter than that of Fig. 105 by the effect that even if the length of the O line chip in the short side direction is longer than the length between the two ends of the chip in the memory cell region. This speeds up address access.

This embodiment will be described below with reference to FIG.

100 shows an embodiment of a semiconductor device according to the present invention. The outline is as follows.

In the same drawing, reference numeral (1) denotes a rectangular chip, and dynamic memory cell regions D3 and D4 are formed at both ends in the longitudinal direction of the chip 1, and peripheral circuits C2 represented by dashed lines are formed at the center thereof. The memory cells in the dynamic memory cell regions D3 and D4 are arranged in an array shape, and word lines (not shown in the drawing) are arranged inside the long side of the chip 1 (Fig. 100). (Data lines are parallel to the short sides of the needles 1). (2) are formed at both edges of one end in the long side direction of the chip 1, respectively. I / O pads (3) denote input address pads formed at the other end of the horn, respectively, and the address pad 3 and the I / O pad 2 are I / O lines. It is connected by 14 and 15, respectively.

The I / O lines 14 and 15 are lines for passing data read from the memory cells in the memory cell areas D3 and D4, respectively, in the memory cell areas D3 and D4. It is provided in parallel with the formed word line.

Thus, in this embodiment, the memory cells in the dynamic memory cell regions D3 and D4 are arranged vertically so that the word lines arranged therein are parallel to the long sides of the chip 1, that is, unlike the horizontal arrangement of FIG. I / O lines arranged in parallel with the word lines in the dynamic memory cell regions D3 and D4 are arranged in parallel with the long sides of the chip 1 in these regions D3 and D4. Since the I / O lines in the memory cell areas D3 and D4 dividedly arranged at both ends are connected in a straight line so as to have the shortest length, the I / O lines 14 and 15 are connected. The length of the chip 1 in the long side direction is the same as that of the I / O lines 4 and 5 in Fig. 105, but it is not increased but the length of the I / O lines 14 and 15 is As shown in FIG. 100, the length of the chip 1 in the short side direction is suppressed to be equal to or less than the length between both ends of the short side direction of the chip 1 in the memory cell regions D3 and D4. In particular, as can be seen from the drawing, the length in the short side direction of the chip 1 of the I / O line 14 is very short compared to that of the I / O lines 4 and 5 of FIG. As a result, the total lengths of the I / O lines 14 and 15 are much shorter than those of the I / O lines 4 and 5 in FIG. 105, and a high speed realization of address access is achieved.

FIG. 101 is a detailed view of the embodiment of FIG.

As shown in the same drawing, the vertically arranged dynamic memory cell regions D3 and D4 are divided into memory cells M, Y decoders 8 and X decoders 9 arranged in an array. The memory cells M and Y decoders 8 are partitioned by two common source lines L and L arranged in parallel with a word line (not shown), and the dynamic memory cell region D3 is provided in the common source lines L and L. FIG. And a sense amplifier (a flip-flop of the CMOS) are respectively connected in D4. Both ends of the common source lines L and L are connected to common source driving MISFETs Q1 and Q2 respectively disposed at ends parallel to the short sides of the chip 1 of the dynamic memory cell regions D3 and D4. The source driving MISFETs Q1 and Q2 are connected in series. The wirings connecting the common source driving MISFETs Q1 and Q2 to each other are connected to charge and discharge wirings 7 and 6 formed along the ends of the short side direction of the chip 1, respectively. The charging wiring 7 is connected to the supply power supply VCC, and the discharge wiring 6 is connected to the ground potential VSS, respectively. The sense amplifier is driven by controlling ON and OFF of the common source driving MISFETs Q1 and Q2.

In addition, in order to avoid the complexity of FIG. 101, the I / O lines are not shown, but the same I / O lines 14 and 15 as those shown in FIG. 100 are also arranged in FIG. .

As described above, the semiconductor device in FIG. 100 is constructed as shown in FIG.

The modification of FIG. 101 is again carried out in FIG.

This modification differs from the semiconductor device shown in FIG. 101 in that the common source driving MISFET for driving the sense amplifiers in the dynamic memory cell regions D13 and D14, which are arranged at both ends in the long direction on the rectangular chip 1, is identical. As shown in the figure, each of the ends of the long side of the chip 1 of the dynamic memory cell regions D13 and D14 is disposed, and the common source driving MISFETs QA and QB are linearly formed by the common source lines L1 and L2. The point is to connect. Here, the common source driving MISFET QAs and QBs are connected in series as shown in the same drawing, and the wirings 21 and 20 for connecting the common source driving MISFET QAs and QBs to each other are respectively connected in series. ) Are directly connected to the supply power supply VCC and the ground power supply VSS that are arranged in close proximity.

In addition, M1, (18) and (19) show memory cells, Y decoders and X decoders respectively formed in the dynamic memory cell areas D13 and D14. In FIG. 102, the I / O lines are not shown in FIG. 102 to avoid the complexity of the drawings, but in FIG. 102, the same I / O lines 14 and 15 as those shown in FIG. Of course, it is arranged.

As described above, the semiconductor device shown in FIG. 102 is constituted, that is, the common source driving MISFETs are arranged at the end portions of the long sides of the chips 1 of the dynamic memory cell regions D13 and D14, respectively, and the common sources at both ends thereof. Since the driving MISFETs QA and QB are connected in a straight line by the common source lines L1 and L2, they are disposed at the inner ends parallel to the short sides of the chips 1 of the dynamic memory cell regions D3 and D4 shown in FIG. The common source driving MISFET Q2 can be eliminated, so that the area in the long side direction of the chip 1 of the dynamic memory cell regions D13 and D14 can be taken larger than that shown in FIG. 101, and the driving circuit can be simplified. have. In addition, the above configuration eliminates the need for the charge / discharge wirings 7 and 6 shown in FIG. 101, so that the area in the short side direction of the chip 1 of the dynamic memory cell regions D13 and D14 is reduced to 101. FIG. It is possible to reduce the noise generated in the wiring while taking it larger than that in the figure.

Here, the common source lines L1 and L2 to which the sense amplifiers are connected are crossed in the vicinity of the peripheral circuit C1 disposed in the center, although not shown in the figure, and are so-called twisted sense wiring.

103 is a circuit diagram showing the principal part of the semiconductor device of FIG. 102 employing this twisted sense method.

As shown in the same figure, the common source driving MISFETs QA and QB of FIG. 102 are actually constituted by two common source driving MISFETs Q10 and Q20, Q30 and Q40, respectively. The common source line L2 connecting the common source driving MISFET Q10 and Q40 and the common source line L1 connecting the common source driving MISFET Q20 and Q30 cross each other as shown in the drawing in the vicinity of the peripheral circuit C12. The sense amplifier S1 is connected to the common source lines L1 and L2 in the memory cell region D13, and the sense amplifier S2 is connected to the common source lines L1 and L2 in the dynamic memory cell region D14, respectively. In addition, in FIG. 103, the drawing is complicated, and only one sense amplifier is shown in each of the regions D13 and D14, but in practice, multiple sense amplifiers are connected to the common source lines L1 and L2 in accordance with the common source lines L1 and L2. It is. The sense amplifiers S1 and S2 are also connected to a pair of data lines BL1 and BL2 arranged in an array, and each of the data lines BL1 and BL2 is composed of a switch MISFET Q5 and a capacitor C and connected to a word line W. One Y decoder 18 is connected. The power supply VCC is connected to the common source driving MISFETs Q10 and Q20, and the ground power supply VSS is connected to the common source driving MISFETs Q30 and Q40, respectively.

Therefore, when the common source driving MISFETs Q10 and Q30 are turned on, the sense amplifier S1 in the dynamic memory cell region D13 is turned on, and the sense amplifier S2 in the dynamic memory cell region D14 is turned off. On the other hand, when the common source driving MISFETs Q20 and Q40 are turned on, the sense amplifier S2 in the dynamic memory cell region D14 is operated, and the sense amplifier S1 in the dynamic memory cell region D13 is turned off.

Thus, since the semiconductor device shown in FIG. 103 adopts the twist sense method, only the sense amplifier of one dynamic memory cell area is always operated (it does not operate at the same time). Therefore, the amount of charges to be drawn out from the sense amplifier is reduced, and the speed is increased.

In the semiconductor device shown in FIG. 102, since the common source lines L1 and L2 pass through the upper portion of the peripheral circuit C12, the peripheral circuit C12 does not have to be separated by the common source lines L1 and L2. The advantage is that the whole can be used effectively.

That is, as shown in FIG. 104, this semiconductor device has a multilayer wiring structure (two layers in the present modification), and the diffusion layer is formed on the substrate 30 by using the first wiring layer 38 for the peripheral circuit C12. Part of the second wiring layer formed of aluminum is used as the common source lines L1 and L2, and the common source lines L1 and L2 are peripheral circuits. The entire area of the peripheral circuit C12 can be used effectively without removing C12. Where (31) and (32) are N wells and P wells respectively formed in the substrate 30, (35) is a field insulating film for separating elements, (37) is a gate electrode, and (36) is a gate An insulating film formed around the electrode 37, 39 is an interlayer insulating film formed on the upper and lower surfaces of the first wiring layer 38, and 41 is the same layer as the common source lines L1 and L2 (second layer). The wiring layer for the peripheral circuit C12 formed in Fig. 2) is indicated by reference numeral 42 in the passivation film formed on the upper surface of the second layer.

However, of course, this modification can also be applied to semiconductor devices having a one-layer structure. In such a case, circuit elements cannot be formed under the common source lines L1 and L2, so that the peripheral circuit C12 is separated by the common source lines L1 and L2, thereby reducing the utilization of the area of the peripheral circuit C12.

In addition, the semiconductor device shown in FIG. 102 has the following advantages.

That is, since the bonding pads 10 for the peripheral circuit C12 are disposed in the vicinity of both ends of the short side direction of the chip 1 of the peripheral circuit C12, the inner leads are disposed close to the center of the long side of the chip 1 ( The coupling between the bonding pad 10 and the bonding pad 10 becomes very good, and the distance between the inner lead and the bonding pad 10 becomes very short, thereby achieving high speed.

As described in the above examples, the following effects are obtained by applying the present invention to semiconductor memory devices such as dynamic RAMs.

(1) In a dynamic RAM having several package specifications and the like, a plurality of bonding pads disposed at optimum positions corresponding to each package type, several buffers provided corresponding to these bonding pads, and corresponding predetermined bonding processes are optional. In this way, a common semiconductor substrate having a plurality of folds, that is, a control bonding pad for selectively validating the plurality of bonding pads is prepared. As a result, since several package specifications can be realized based on one common semiconductor substrate, the effect of efficient development of varieties such as dynamic RAM having several package specifications can be obtained.

(2) The transfer delay of the input or output signal by placing each of the plurality of buffers in close proximity to the corresponding bonding pads, and output terminals of the corresponding buffers in the form of wiring logic, respectively. The effect is that the time can be shortened to speed up the operation of the dynamic RAM and the like.

(3) By operating the output terminal of each unit circuit of the X address buffer and the output terminal of the corresponding unit circuit of the playback counter in the form of wiring logic, the transmission delay time of the X address signal is reduced to operate the dimmable RAM or the like. The effect of speeding up is obtained.

(4) The address shifting circuit is constituted by a plurality of unit circuits provided corresponding to one or several address input pads arranged on the surface of the semiconductor substrate and a common circuit which receives output signals of these unit circuits. By arranging several unit circuits in close proximity to the corresponding address input pads and placing the common circuits in substantially the center of the semiconductor substrate surface, the delay time of the address signal can be reduced, thereby speeding up the operation of the address transition detection circuit. Effect is obtained.

(5) A memory array, such as a dynamic RAM, is divided into at least two by a center line parallel to the short side of the surface of the semiconductor substrate in a divided word line manner. And a portion of a peripheral circuit including a word line driver circuit is disposed along the center line, a memory array is sandwiched between a portion of the peripheral circuit, and the word line extends symmetrically toward each short side of the semiconductor substrate surface. This reduces the propagation delay time of the selection signal or the like in the X-based selection circuit, thereby achieving an effect of speeding up the access time of the dynamic RAM.

(6) The above-mentioned (5), wherein unit circuits, such as word line driving circuit, X predecoder and X redundant circuit, which constitute the X-based selection circuit, are placed with the center line parallel to the short side of the semiconductor substrate surface. By symmetrically arranging, the effect that the layout of the layout and the layout of peripheral circuits, such as dynamic RAM, can be made efficient can be obtained.

(7) The memory array is arranged in at least four divisions by two centerlines parallel to the short and long sides of the semiconductor substrate surface. A part of the peripheral circuit is arranged along the centerline parallel to the short side of the semiconductor path board, and another part of the peripheral circuit is arranged parallel to each short side of the semiconductor substrate surface on the outside of the memory array. And a first power supply line and a part or other part of the peripheral circuit and a first power supply line which are arranged along a center line parallel to the long side of the semiconductor substrate to supply the power voltage or the grounding level of the circuit to the peripheral circuit and the memory array. Are arranged according to a plurality of power supply lines which are respectively arranged in accordance with the first power supply line and are commonly coupled through the first power supply line. As a result, the overall impedance of the power supply line can be reduced, power supply noise can be suppressed, and the operation of the dynamic RAM and the like can be stabilized.

(8) In the above (7), a bonding pad for transferring the power supply voltage or the ground potential of the circuit to the power supply trunk is disposed near one end or the other end of the first power supply line. In addition, part or all of the first power supply line is composed of multiple metal wiring layers. As a result, the overall impedance of the power supply trunk can be further reduced, thereby obtaining the effect of further stabilizing the operation of the dynamic RAM.

(9) In the above (7) and (8), signal lines for coupling between a part of the peripheral circuit and another part are arranged along the first power supply line, and the input and output nodes related to these signal lines are arranged in the first line. Place it close to the power supply line. As a result, the effect of reducing the transmission delay time of the signal transmitted through the signal line and speeding up the operation of the dynamic RAM or the like is obtained.

(10) By shortening the transfer delay time of the corresponding address signal by arranging the unit circuit of the address buffer provided corresponding to each bit of the address signal close to the corresponding bonding pad to speed up the operation of the dynamic RAM or the like. The effect can be obtained.

(11) According to (10), the X address signal and the Y address signal are supplied time-divisionally, and each unit circuit of the Y address buffer is arranged closer to the corresponding bonding pad than the corresponding unit circuit of the X address buffer. As a result, the transfer delay time of the Y address signal which determines the cycle time of continuous operation in the static column mode or the like can be reduced, thereby achieving an effect of further speeding up the operation of the dynamic RAM and the like.

(12) A circuit element constituting a peripheral circuit is formed in an element region provided in a band shape at predetermined intervals on a semiconductor substrate surface, and signal lines for coupling between these circuit elements are formed in a wiring region provided between the element regions. By doing so, the effect that the layout of the peripheral circuit which has a random logic circuit as a basic structure can be made efficient is acquired.

(13) In the above (12), two metal wiring layers are provided in the wiring area, the double wiring metal wiring layer is arranged in parallel with the device area, and used as a main signal line for coupling between circuit elements. The lower metal wiring layer is used as an outgoing signal line for coupling the main signal line corresponding to the circuit element. As a result, the effect of suppressing the resistance value of the main signal lines arranged over a relatively long distance, reducing the signal propagation delay time, and speeding up the operation of the dynamic RAM or the like can be obtained.

(14) In a dynamic RAM or the like which can provide several varieties by changing part of a photomask of a common semiconductor substrate, a predetermined signal line is used as a signal line for a different purpose for each variety. As a result, the effect of reducing the number of signal lines arranged over a relatively long distance in a relatively narrow wiring area on the surface of the common semiconductor substrate can be achieved to improve the efficiency of layout such as a dynamic RAM.

(15) A control signal corresponding to a precharge control signal line or the like disposed on the surface of the semiconductor substrate over a relatively long distance and whose one end and the other end are respectively coupled to the output terminals of the two driving circuits is provided with the two driving circuits. Cut at a predetermined position according to the time difference until passing through one end and the other end via.

Thereby, the effect that the through-current which arises by the shift of the transmission time can be prevented.

(16) The column address strobe signal and the write enable signal are set to a low level before the low address strobe signal, and a predetermined high voltage exceeding the power supply voltage of the circuit is supplied to a predetermined external terminal at the falling edge of the low address strobe signal. The set cycle of the vendor test mode is determined under the condition that it is. Further, the specific contents of the vendor test are selectively designated by a combination of predetermined address signals supplied from the one edge of the low address strobe signal. As a result, after the package is sealed, various test operations such as a dynamic RAM and the like can be selectively performed by a combination of start control signals that cannot be performed in normal memory access.

(17) In the vendor test mode, for example, the operation of a voltage generating circuit or the like which forms an internal voltage is substantially stopped, wherein the value of the internal voltage is selectively changed in accordance with a test signal supplied through a predetermined external terminal, In addition, by making it possible to evaluate stepwise, for example, the effect that the memory cell test or the leak current test can be efficiently performed in a plate stress state or a standby current stop state is obtained.

(18) a common I / O line to which a designated data line is selectively connected, a static main main amplifier to which the common I / O line is selectively connected, and a common I / O to selectively connect the common I / O line and a main amplifier. In a dynamic RAM or the like having an O-line selection circuit, each of the complementary signal lines from the common I / O line to the output node of the main amplifier is selectively connected or disconnected at the front end or the rear end of the switch means or at a predetermined intermediate node. Equalize. As a result, an effect of speeding up the level change at each node and speeding up the write or read operation of the dynamic RAM or the like can be obtained.

(19) The memory array according to (18), wherein the so-called vertical array is arranged, and the common I / O line is arranged over two memory arrays arranged symmetrically, and a corresponding common is outside of one memory array. Combine with I / O line selection circuit. At this time, the common I / O line is equalized at each of the coupling node and the intermediate node of the corresponding two memory arrays. This achieves the effect of speeding up the equalization processing of the common I / O line and further speeding up the operation of the dynamic RAM and the like.

(20) The light pulses according to the above (18) and (19) are effectively formed by forming a light pulse for controlling the continuous write operation by the static column mode or the like based on a timing signal for controlling the equalization process. Since it can form, the effect that a continuous write operation in a static column mode, such as a dynamic RAM, etc. can be speeded up is acquired.

(21) A first voltage generation circuit for forming a substrate back bias voltage based on a predetermined pulse signal in a substrate back bias voltage generation circuit and a second voltage for forming the substrate back bias voltage based on an inverted signal of the pulse signal. Prepare a voltage generator circuit. As a result, it is possible to suppress the level fluctuation in synchronization with the pulse signal of the substrate back bias voltage and stabilize the operation of the dynamic RAM.

(22) An address match detection circuit and an address mismatch detection circuit are respectively provided for determining that the bad address assigned to the redundant word line corresponding to the X-based redundant circuit is identical or inconsistent with an externally designated address. By selectively validating the corresponding conditions, the transfer delay time of the redundant circuit serving as the critical path can be reduced, thereby achieving an effect of speeding up the operation of the dynamic RAM and the like.

(23) Selective drawing type in which the word line selection timing signal generation circuit, redundant word line selection timing signal generation circuit, and redundant X address decoder constituting the X-based selection circuit are selectively drawn out under the conditions corresponding to the precharged output node. By constructing the circuit and configuring the X address decoder as a selective charging circuit whose output node is selectively occupied under a predetermined condition, the operation can be speeded up while reducing the current consumption of the X-based selection circuit. Lose.

(24) The output signal of the X predecoder is selectively and alternatively valid when the dynamic RAM is selected, and the reset timing of each X address signal is changed according to its purpose. As a result, the sequence control can be executed in accordance with the internal address signal or the output signal of the X predecoder, so that the circuit configuration of the peripheral circuit can be simplified and the operation of the dynamic RAM can be speeded up.

(25) In the timing generating circuit, a monitor word line having substantially the same structure as a word line constituting a memory array and having equivalent electrical characteristics, and a word line selection signal selectively supplied to the word line is used for the monitor. By providing a word line monitor circuit for identifying that the far end of the word line has been reached, it is possible to accurately determine that the word line selection operation has ended, so that the operation of the timing generating circuit and the dynamic RAM, etc. can be stabilized. Is obtained.

(26) The second monitor word line is provided in (25), and the other end of one of the monitor word lines is coupled to an input terminal of a logic gate circuit having a relatively high logic threshold level. The other end of the word line for monitoring is coupled to an input terminal of a logic gate circuit having a relatively low logic threshold level, and the output signals of these logic gate circuits are selectively validated by, for example, laser trimming. . This obtains the effect of more accurately stabilizing the word line monitor circuit and making it possible to stabilize the operation of the dynamic RAM.

(27) A latch for receiving a complementary output signal outputted from a front end circuit and holding the data thrust buffer, a pair of NAND gate circuits for selectively transferring the complementary output signal of the latch, and a complement of the pair of NAND gate circuits. A pair of inverter circuits for inverting and transferring signals are provided in series between the power supply voltage and the ground potential of the circuit to receive the complementary output signals of the pair of inverter circuits at each gate. By configuring a pair of N-channel type output MISFETs coupled to the data output terminal or the data input / output terminal, the circuit configuration of the data output buffer can be optimized to speed up the output operation of the dynamic RAM.

(28) In (27), the non-inverting and inverting input / output nodes of the latch are temporarily equalized immediately before a new complementary output signal is transmitted from the front end circuit, and the output is temporarily placed in a high impedance state. As a result, the operation of the data output buffer can be speeded up, and a single read operation such as a dynamic RAM and the continuous read operation by the static column mode can be further accelerated.

(29) The source, gate and drain regions, and contacts of each pair of P-channel and N-channel MOSFETs constituting the sense amplifier are line-symmetric with a straight line perpendicular to the extension direction of the corresponding complementary data line. Lay out to be parallel to each of said straight lines. As a result, the parasitic capacitance generated in the non-inverted signal and the inverted signal of each complementary data line can be canceled by, for example, mask shift or the like, so that the read operation of the dynamic RAM or the like can be stabilized.

(30) An input diffusion layer coupled to a corresponding bonding pad through a metal wiring layer in the input protection circuit and second and third diffusion layers formed to face the input diffusion layer and coupled to a power supply voltage or ground potential of the circuit via a rapid wiring layer. Since the lateral bipolar transistors absorbing the spike noise at high speed can be formed between the pad and the power supply voltage and the ground potential of the circuit, the effect of improving the input protection characteristics of the dynamic RAM can be obtained.

(31) The input at the time of breakdown according to the above (30), in which a predetermined well region is formed around all of the input diffusion layer and the second and third diffusion layers, or around and below the front edge portion facing each other. The effect of preventing the breakdown of the diffusion layer and at the same time suppressing surge oddity for the semiconductor substrate can suppress variation in substrate potential.

(32) Protection resistance provided by using a well resistance formed by a pair of diffusion layers facing each other with a well region interposed therebetween as a protection resistor provided between an input or output terminal of an internal circuit and a corresponding bonding pad. It is possible to reduce the area of the chip, such as the dynamic RAM, by reducing the area required for the layout.

(33) The drain of the clamp MOSFET by coupling the drain of the clamp MOSFET provided in the input protection circuit to the input or output terminal of the internal circuit or the protective resistor via a metal wiring layer and several contacts formed over the almost entire upper layer thereof. The effect that the current distribution in the region can be made uniform can be stabilized.

(34) It is formed to surround a part of the input diffusion layer, and is formed to surround the second diffusion layer and another part of the input diffusion layer which are coupled to the power supply voltage of the circuit via the metal wiring layer, and also through the metal wiring layer. By providing a third diffusion layer coupled to the ground potential, the ON resistance of the lateral bipolar transistor formed equivalently between the input pad and the furnace power voltage or the ground potential can be reduced to improve the protection characteristics of the input protection circuit. Effect is obtained.

(35) The method according to the above (34), by forming a predetermined well region under the input diffusion layer and the metal wiring layer, i.e., a plurality of contacts for joining corresponding pads, between the input diffusion layer under the contact and the semiconductor substrate. An effect that the internal pressure can be increased is obtained.

(36) The metal wiring layer according to the above (34) and (35) is formed over the upper part of the part of the second and third diffusion layers for joining the pads corresponding to the input diffusion layer. A metal wiring layer for coupling the diffusion layer of 3 and the power supply voltage or the ground potential of the circuit is formed over a portion of the input diffusion layer. This makes it possible to equally form a bidirectional clamp MOSFET having a large threshold voltage between each pad and the power supply voltage and the ground potential of the circuit, so that the characteristics of the power supply voltage and the ground potential of the input protection circuit are the same. The effect that can be improved is obtained.

(37) A gate layer formed by polysilicon and the like and substantially fastening a gate layer acting as a gate electrode of a MOSFET and a fast wiring layer for transmitting an input signal to the gate layer through at least two contacts. By reducing the propagation delay time of the input signal, the effect of speeding up the operation of a peripheral circuit including a MOSFET, and moreover, a dynamic RAM can be obtained.

(38) The word lines W are formed so that the dynamic memory cell areas D3, D4, (D13, D14) are formed so as to be parallel to the long sides of the rectangular chip 1, so that the words in the dynamic memory cell areas D3, D4 (D13, D14) are formed. Memory cells D3, D4 (D13, D14) arranged in parallel with the long side of the chip 1 in the regions D3, D4 (D13, D14) arranged in parallel with the line W. By linearly connecting these 1/0 lines in), the length in the long side direction of the chip 1 of the 1/0 lines 14 and 15 is the same as that of FIG. Even if the length in the short side direction of the chip 1 of the / 0 line 14 and 15 is long, the degree between both ends of the short side direction of the chip 1 of the memory cell areas D3 and D4 (D13 and D14) The length of the I / O lines 14 and 15 is shorter than that shown in FIG. 105 due to the effect of being able to be suppressed to be less than or equal to that of FIG. 105, thereby speeding up address access.

As mentioned above, although the invention made by the present inventors was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

For example, the dynamic RAM may have package specifications other than DIP, SOJ, and ZIP, or may include a plurality of control bonding pads for switching the package specifications. In addition, various embodiments are considered as a specific method for switching the package specification. The number of bits of the X address signal and the Y address signal and the use of each bit are not limited by this embodiment, and the arrangement or combination of bonding pads corresponding to these address signals is also the same. The memory mat may be further divided into several memory mats, and each memory array may take a shared sense amplifier method, for example. In addition, any number of redundant word lines and redundant complementary data lines can be provided in each memory array, and the defective address ROM provided in each redundant circuit need not be particularly fuse means. The details of the test operation in the vendor test mode are considered various embodiments, and may have a dedicated reset cycle. Some embodiments shown as protective circuits can be applied in different combinations, and the shape of each diffusion layer or metal wiring layer is only one. The metal wiring layer prepared on the semiconductor substrate does not need to be aluminum or its alloy, and three or more metal wiring layers may be prepared. The specific circuit configuration shown in each circuit diagram, the specific layout of the layout shown in each layout diagram, the combination of the start control signal, the address signal, the difference signal, the logic level, and the like can take various embodiments.

In the semiconductor device shown in FIG. 100, the 1/0 pad 2 is formed at both edges of one end in the long side direction of the chip 1, and the address pad 3 of the input is at the corner of the other end. Although formed in the portion, the positions of the 1/0 pad 2 and the address pad 3 are not limited to this portion, and the 1 / O pad 2 and the address pad 3 are in the longitudinal direction of the chip 1. This can be applied to semiconductor devices that are disposed at both ends.

In the above description, the invention made mainly by the present inventors has been described in the case where the invention is applied to the dynamic RAM, which is the background of use, but is not limited thereto. For example, switching of the package specification by a bonding option, protection circuit and output The invention relating to a buffer or the like can be applied to various semiconductor integrated circuit devices, and other inventions can also be applied to various semiconductor memory devices such as a static RAM or a digital integrated circuit including these semiconductor memory devices. The present invention is widely applicable to semiconductor integrated circuit devices having at least several package specifications and having input / output bonding pads or output buffers, or semiconductor memory devices having several memory mats or internal voltage generation circuits.

The effect obtained by the representative of the invention disclosed herein will be briefly described as follows.

That is, in a dynamic RAM having a plurality of package specifications, a plurality of bonding pads disposed at optimum positions corresponding to each package type, a plurality of buffers provided corresponding to these bonding pads, and corresponding predetermined bonding processes are optional. By implementing a common semiconductor substrate having a plurality of buffers, that is, a control bonding pad for selectively validating the plurality of bonding pads, and share this in several package specifications.

Also, a memory array such as a dynamic RAM is divided into at least four quarters by two center lines parallel to the short side and the long side of the semiconductor substrate surface, and the X-based selection circuit is arranged along the middle wire parallel to the short side of the semiconductor substrate surface. Peripheral circuits, including the other portion of the peripheral circuit parallel to each short side of the semiconductor substrate surface on the outside of the memory array. At this time, the power supply line is connected by a plurality of power supply lines commonly coupled by a first power supply line arranged along a center line parallel to the long side of the semiconductor substrate surface and the first power supply line arranged along each peripheral circuit. Configure. As a result, the development of varieties of semiconductor memory devices such as dynamic RAMs with multiple package specifications can be made more efficient, and the dynamic RAM can be minimized by reducing power supply noise and reducing the area required for layout while reducing the signal transmission delay time. The operation and the like can be speeded up and stabilized. As a result, the performance and reliability of the dynamic RAM and the like can be improved and the cost can be reduced.

In addition, the peripheral circuits are formed at the centers of the dynamic memory cell regions at both ends in the long direction on the long-haired chip, and the I / O pads and the address pads formed at both ends in the long direction of the chip are connected to each other. The dynamic memory cell region of the semiconductor device having an I / O line arranged in parallel with a word line formed in the dynamic memory cell region in the dynamic memory cell region is formed such that the word line is parallel with the long side of the chip. The I / O lines arranged parallel to the word lines in the dynamic mecellel region are also arranged parallel to the long sides of the chip within this region, and the I / O lines in the merery cell region divided at both ends are connected linearly. Even if the length in the short direction of the chip of the I / O line is longer without lengthening the length in the long side direction of the chip of the I / O line The length of the chip between the two edges of the short side of the chip in the memory cell area can be suppressed. As a result, the length of the I / O line is shortened, so that address access can be speeded up.

Claims (5)

A memory array including a word line, a data line, and a memory cell, test means for testing the memory array, and a low address strobe ( ) First external terminal that receives a signal, column address strobe ( ) 2nd external terminal receiving a signal, light enable ( A third external terminal receiving a signal, a fourth external terminal receiving an external power supply voltage, a fifth external terminal receiving a predetermined voltage, and the first, second, third, fourth and fifth external terminals And mode setting means connected to the test means, wherein the mode setting means includes the voltage of the second external terminal and the third at a timing at which the voltage of the first external terminal changes from a high level to a low level. And the test means is set to the test mode by detecting that the voltages of the external terminals are all at a low level and that the fifth external terminal receives a voltage greater than the absolute value of the shunt voltage. The electronic device of claim 1, further comprising a sixth external terminal for receiving an address signal, wherein the sixth external terminal is connected to the mode setting means, and the voltage of the first external terminal is changed from a high level to a low level. The semiconductor memory device according to claim 6, wherein the type of the test mode is specified in accordance with the voltage level of the sixth external terminal at the timing. 3. The method of claim 2, wherein the timing at which the voltage of the first external terminal changes from a high level to a low level detects that the voltage of the second external terminal is low and the voltage of the third external terminal is high. A semiconductor memory device for canceling the test mode. 3. The method of claim 2, wherein the voltage of the second external terminal and the voltage of the third external terminal are both detected at a high level at a timing at which the voltage of the first external terminal changes from the bell to a low level. A semiconductor memory device for releasing the test cap. The semiconductor memory device according to claim 2, wherein the sixth external terminal is a terminal for outputting or inputting data.