JPH02248070A - Semiconductor device - Google Patents

Abstract

PURPOSE:To get access to addresses at a high speed by a method wherein a dynamic memory cell region is provided to both the lengthwise ends of a rectangular chip respectively, a peripheral circuit is formed on the center of the chip, and a word line is formed in parallel with the longer side of the chip. CONSTITUTION:Dynamic memory cell regions D3 and D4 are formed on the lengthwise ends of a chip 1 respectively, and a peripheral circuit C2 is formed on the center of the chip 1. The memory cells are arranged in array inside the regions D3 and D4, and word lines are arranged inside the regions D3 and D4 in parallel with the longer side of the chip 1. By this setup, I/O wires 14 and 15 can be shortened in length, so that the addresses can be accessed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology that is effective when applied to semiconductor devices, such as DRAM (Dynamic Rand
The present invention relates to a technique that is effective for use in a semiconductor device equipped with OM Access Me+aory).

[Prior Art] Recently, semiconductor devices have appeared in which dynamic memory cell regions are arranged at both ends of a rectangular chip in the longitudinal direction, and peripheral circuits are arranged at the center of the rectangular chip.

FIG. 6 shows an example of this semiconductor device.

In the figure, reference numeral 1 indicates a rectangular chip, and dynamic memory cell areas D1 and D2 are formed at both ends of the chip 1 in the longitudinal direction, and a peripheral circuit C1 shown by a dashed line is formed in the center of the chip. ing. The memory cells in the dynamic memory cell areas D1 and D2 are arranged in an array, and the word lines (not shown) arranged inside the memory cells are arranged along the short sides of the chip 1 (in the left-right direction in FIG. 6). They are arranged parallel to each other (the data lines are parallel to the long sides of the chip 1). Reference numeral 2 indicates an I/O pad formed at both corners of one end of the chip 1 in the long side direction (vertical direction in FIG. 6), and reference numeral 3 indicates an input address pad formed at the corner of the other end. This address pad 3 and the above-mentioned I/O pad 2 are respectively connected by an OvA4.5. This I
/O lines 4.5 are connected to memory cell areas D1. This is a line that passes the data read from the memory cells in D2,
It is arranged in the memory cell regions D1, D2 and parallel to the word lines formed in the memory cell regions D1, D2.

In this way, conventionally, the memory cells in the dynamic memory cell regions D1 and D2 are arranged so that the word lines arranged therein are parallel to the short sides of the chip 1, that is, arranged horizontally. Ta.

[Problems to be Solved by the Invention] However, the semiconductor device having the above configuration has the following problems.

That is, when the memory cells are placed horizontally as described above, the I/O lines 4.5 passing through the memory cell areas D1 and D2 must be arranged in parallel following the word lines. Moreover, I/O pad 2° and address pad 3 are chip 1.
As shown in FIG. 6, the length of the I/O line 4.5 in the short side direction of the chip 1 is the minimum memory The length between both ends of the cell regions D1 and D2 in the short side direction of the chip 1 is required, and at least one of the I/O lines 4.5 (I/O line 5 in FIG. 6) is required. This inevitably requires unnecessary routing in the short side direction of the chip 1, which poses a problem in that the speed of address access becomes slow.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of speeding up address access.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, dynamic memory cell areas are formed at both longitudinal ends of a rectangular chip, peripheral circuits are formed at the center thereof, and I/O pads and address pads formed at both longitudinal ends of the chip are connected. The dynamic memory cell region of the semiconductor device is also provided with an I/O line arranged in parallel to a word line formed in the dynamic memory cell region in the dynamic memory cell region. It is formed parallel to the long side.

[Operation] According to the above-described means, the dynamic memory cell area is formed so that the word line is parallel to the long side of the chip, so that the word line is arranged parallel to the word line in the dynamic memory cell area. I/O lines are also arranged parallel to the long sides of the chip within this area, and by linearly connecting these I/O lines in the memory cell area divided at both ends, I/O Even if the length of the I/O line in the short side direction of the chip is increased while the length of the line in the long side direction of the chip is unchanged from the conventional one, the length of the distance between both ends of the memory cell area in the short side direction of the chip will be increased. As a result, the length of the I/O line becomes shorter than that of the conventional one, and the above object of speeding up address access can be achieved.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a semiconductor device according to the present invention. The outline is as follows.

In the figure, reference numeral 1 indicates a rectangular chip, and dynamic memory cell areas D3 and D4 are formed at both ends of the chip 1 in the longitudinal direction, and a peripheral circuit C2 shown by a dashed-dotted line is formed in the center of the chip. ing. The memory cells in the dynamic memory cell areas D3 and D4 are arranged in an array, and the word lines (not shown to avoid complication) arranged inside the memory cells are connected to the long sides of the chip 1 (the first The data lines are arranged parallel to each other (in the vertical direction in the figure) (the data lines are parallel to the short sides of the chip 1). Reference numeral 2 indicates an I/O pad formed at both corners of one end of the chip 1 in the long side direction, and reference numeral 3 indicates an input address pad formed at the corner of the other end. The pad 3 and the I/O pad 2 are connected by I/O lines 14 and 15, respectively. These I/O lines 14 and 15 are connected to memory cell areas D3 and 15, respectively. This is a line through which data read from the memory cells in D4 passes, and is arranged in the memory cell regions D3 and D4 in parallel to the word lines formed in the memory cell regions D3 and D4.

As described above, in this embodiment, the memory cells in the dynamic memory cell regions D3 and D4 are arranged such that the word lines arranged therein are parallel to the long sides of the chip 1.
That is, unlike the conventional horizontal arrangement, the I/O lines arranged parallel to the word lines in the dynamic memory cell regions D3 and D4 are arranged vertically in the dynamic memory cell regions D3 and D4.
It is arranged parallel to the long side of the chip 1 within D4. The I/O lines in the memory cell areas D3 and D4, which are divided and arranged at both ends, are connected linearly to minimize the length (it is possible to connect them), so the I/O lines are connected in a straight line to minimize the length. The length of the O line 14.15 in the long side direction of the chip 1 is the same (does not increase) as that of the conventional I/O line 4.5, but the length of the I/O line 14.15 in the short side direction of the chip 1 is the same as that of the conventional I/O line 4.5. As shown in FIG. 1, the length is at most the memory cell area D3. The length can be suppressed to be equal to or less than the length between both ends of the chip 1 in the short side direction of D4. In particular, as is clear from the figure, the length of the I/O line 14 in the short side direction of the chip 1 is much shorter than that of the conventional I/O line 4.5. The total length of 14.15 lines is extremely shortened compared to that of the conventional I/O line 4.5 lines, thereby achieving high speed address access.

FIG. 2 is a detailed view of the embodiment of FIG.

As shown in the figure, the vertically arranged dynamic memory cell regions D3 and D4 are divided into a large number of memory cells M arranged in an array, a Y decoder 8, and an X decoder 9, respectively. The memory cell M and the Y decoder 8 are separated by two common source lines, L, which are arranged parallel to a word line (not shown). memory cell area D3,
Sense amplifiers (0MO3 flip-flops) are connected within D4. Both ends of this common source line L are dynamic memory cell areas D3 and D.
These common source drive MISFETs Ql and Q2 are respectively arranged at the ends parallel to the short side of the chip 1 of 4.
Ql and Q2 are connected in series.

These wirings connecting the common source driving MISFETs Qll and Q2 with the same amount are respectively connected to charging and discharging wirings 7 and 6 formed along the ends of the chip 1 in the short side direction. 7 is connected to the supply power supply Vcc, and the discharge wiring 6 is connected to the ground power supply Vss. The sense amplifier is driven by controlling on/off of the common source driving MISFETs Q1 and Q2.

Note that the I/O lines are not shown in Figure 2 to avoid complicating the diagram, but the I/O lines are not shown in Figure 2 as well.
I/O lines 14.15 similar to those shown in the figure are provided.

In this way, the semiconductor device in FIG. 1 is constructed as shown in detail in FIG. 2.

FIG. 3 shows a modification of FIG. 2.

The difference between this modified example and the semiconductor device shown in FIG. 2 is that
A common source driving MISFET for driving sense amplifiers in dynamic memory cell areas D13 and D14 dividedly arranged at both ends of the rectangular chip 1 in the longitudinal direction.
As shown in the figure, are arranged at the ends of the long sides of the chip 1 in the dynamic memory cell areas D13 and D14, respectively, and the common source driving MI
This is because SFETs QA and QB are linearly connected by common source lines L1 and L2. Here, as shown in the figure, the common source driving MISFETs QA and QB are connected in series, and these common source driving MISFETs QA and QB are connected between the same amount and the same amount. The wirings 21 and 20 are directly connected to a supply power source Vcc and a ground power source Vss, respectively, which are arranged in close proximity.

Note that the code M1.18.19 indicates the dynamic memory cell area, 013. A memory cell, a Y decoder, and an X decoder each formed in D14 are shown. Similarly to FIG. 2, I/O lines are not shown in FIG. 3 to avoid complication, but I/O lines similar to those shown in FIG. /O line 14.1
Of course, 5 is provided.

The semiconductor device shown in FIG. 3 is configured in this way. That is, the common source driving MISFETs are arranged at the ends of the long sides of the chip 1 in the dynamic memory cell areas D13 and D14, and Since the source driving MISFETs QA and QB are connected linearly by the common source lines L1 and L2, the dynamic memory cell area D3 shown in FIG.
, D4, the common source driving MISFET Q2 disposed at the inner end parallel to the short side of the chip 1 can be eliminated, and therefore the dynamic memory cell area D13.
The area of the D14 in the long side direction of the chip 1 can be made larger than that of FIG. 2, and the driving circuit can be simplified.

Furthermore, since the above configuration eliminates the need for the charging/discharging wiring 7.6 shown in FIG. It is also possible to increase the size and reduce noise generated in the wiring.

Here, common source line L1 to which the sense amplifier is connected
, L2 intersect, although not shown in the figure, near the peripheral circuit c1 located in the center, and are wired in a so-called twist sense system.

FIG. 4 is a circuit diagram showing a main part of the semiconductor device shown in FIG. 3 which employs this twist sense method.

As shown in the figure, the common source driving M
ISFETs QA and QB are actually two common source drive MISFETs QIO and Q20, QB0 and Q4
0 respectively. The common source line L2 that connects the common source driving MISFET Q/O and Q40 and the common source line L1 that connects the common source driving MISFET Q20 and QB0 are connected to the peripheral circuit C12.
The common source lines L1 and 2 in the dynamic memory cell area D13 intersect as shown in the figure.
A sense amplifier S1 is connected to L2, and a sense amplifier S2 is connected to common source lines L1 and L2 in the dynamic memory cell region D14. In addition, in FIG. 4, each area D13, D1 is
Although only one sense amplifier is shown in FIG. 4, a large number of sense amplifiers are actually connected to the common source lines L1 and L2 along the common source lines L1 and L2.
ing. These sense amplifiers S1 and S2 are also connected to a pair of data lines BLI and BL2 arranged in the array, and each data line BLI and BL2 is connected to a switch MISFE.
A memory cell M1 consisting of TQ5 and a capacitor C and connected to a word line W and the above-mentioned Y decoder 18 are connected. The above common source drive MISFET Q/
The supply voltage Vcc is applied to common source drive MISFET QB0.O, Q20. Q40 has a ground power supply Vss
are connected to each other.

Therefore, MISFET Q for common source IIHIII
When /O, Q30 is turned on, the sense amplifier Sl in the dynamic memory cell area D13 is activated, and the sense amplifier S2 in the dynamic memory cell area D14 is turned off. On the other hand, MISFE for common source drive
T Q20. When Q40 is turned on, the sense amplifier S2 in the dynamic memory cell area D14 is activated, and the sense amplifier S1 in the dynamic memory cell area D13 is turned off.

In this way, since the semiconductor device shown in FIG. 4 uses the twisted sense method, only the sense amplifiers in one side of the dynamic memory cell area always operate (they never operate at the same time). Therefore, the amount of charge to be extracted by the sense amplifier is reduced, and speeding up is achieved.

Further, in the semiconductor device shown in FIG. 3, since the common source lines L1 and L2 pass above one peripheral circuit C12, the peripheral circuit C12 is connected to the common source line L1. L2
There is an advantage that the entire area of the peripheral circuit C12 can be effectively used without having to be divided by the peripheral circuit C12.

That is, as shown in FIG. 5, the semiconductor device has a multilayer wiring structure (two layers in this modification),
The first wiring layer 38 is used for the peripheral circuit C12 on the substrate 3.
It is used as a dedicated wiring to contact the diffusion layers 33 and 34 formed in 0, and is made of aluminum.
Since a part of the Nth wiring layer is used as the common source lines L1 and L2, the common source lines L1 and L2 do not divide the peripheral circuit C12, and the entire area of the peripheral circuit C12 is effectively used. It is now possible to do so. Here, numerals 31 and 32 represent N formed on the substrate 30, respectively.
35 is a field insulating film for element isolation, 37 is a gate electrode, 36 is an insulating film formed around the gate electrode 37, and 39 is the upper surface of the first wiring layer 38. and an interlayer insulating film formed on the bottom surface of 4
1 is common source IIAL1, L2 and M (27th II
42 indicates a wiring layer for the peripheral circuit C12 formed in ), and 42 indicates a passivation film formed on the upper surface of the second layer.

However, it goes without saying that this modification is also applicable to a semiconductor device with a single layer structure.

In that case, since it is no longer possible to form a circuit element under the common source lines L1 and L2, the peripheral circuit C12 will be separated by the common source lines L1 and L2, and the utilization of the area of the peripheral circuit C12 will be reduced. This will result in a decline.

Furthermore, the semiconductor device shown in FIG. 3 has the following advantages.

In other words, the bonding pad /O for the peripheral circuit C12
are arranged near both ends of the chip 1 in the short side direction of the peripheral circuit C12, so that inner leads (not shown) arranged close to the center of the long side of the chip 1
The contact between the inner lead and the bonding pad/O is very good, and the distance between the inner lead and the bonding pad 1° is very short, so high speed is achieved.

According to the semiconductor device configured in this manner, the following main effects can be obtained.

That is, the dynamic memory cell areas D3 and D4 (D
13, D14), the I/O lines arranged parallel to the word line W in the dynamic memory cell areas D3, D4 (D13, D14) also form the area D.
3, D4 (D13, D14) This I/O line in memory cell areas D3, D4 (D13, D14) is now arranged parallel to the long side of the chip 1, and is divided at both ends. I/O line 14 by connecting it in a straight line
．． Even if the length of the I/O line 14.15 in the long side direction of the chip 1 is not changed from the conventional one, and the length of the I/O line 14.15 in the short side direction of the chip 1 is increased, the memory cell areas D3, D4 (D
13, D14), I/○
The lengths of lines 14 and 15 are shorter than in the past, and address access can be made faster.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the semiconductor device shown in FIG.
The O pad 2 is formed at both corners of one end in the long side direction of the chip 1, and the input address pad 3 is formed at the corner of the other end. The method is not limited to this portion, but can be applied to a semiconductor device in which the I/O pad 2 and the address pad 3 are respectively arranged at both ends of the chip 1 in the longitudinal direction.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, dynamic memory cell areas are formed at both longitudinal ends of a rectangular chip, peripheral circuits are formed at the center thereof, and I/O pads and address pads formed at both longitudinal ends of the chip are connected. The dynamic memory cell region of the semiconductor device is also provided with an I/O line arranged in parallel to a word line formed in the dynamic memory cell region in the dynamic memory cell region. Since it is formed parallel to the long side, I/Os arranged parallel to the word line in the dynamic memory cell area
The lines are also arranged parallel to the long sides of the chip within the area, and by linearly connecting the I/O lines in the memory cell area divided at both ends, the I/O lines of the chip can be While the length in the long side direction is unchanged from the conventional one, the length of the I/O line in the short side direction of the chip is kept to at most the distance between both ends of the chip in the short side direction of the memory cell area. You will be able to do this.

As a result, the length of the I/O line becomes shorter than in the past, making it possible to speed up address access.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of a semiconductor device according to the present invention, FIG. 2 is a detailed diagram of the same embodiment, FIG. 3 is a detailed diagram showing a modification of FIG. 2, and FIG. Circuit diagram of main parts in the figure. FIG. 5 is a cross-sectional view taken along the line AA in FIG. 3, and FIG. 6 is a schematic configuration diagram of a semiconductor device according to the prior art. 1... Rectangular chip, 2... I/O pad, 3
...Address pad, 14.15...I/O line. C2, C12...peripheral circuit, D3. D4. Di3,
D14...Dynamic memory cell area, W...
・Word line. Figure Figure

Claims (1)

[Claims] 1. Dynamic memory cell areas are formed at both ends of a rectangular chip in the longitudinal direction, peripheral circuits are formed in the center thereof, and I/O pads are formed at both ends of the chip in the longitudinal direction. In the semiconductor device, the semiconductor device includes an I/O line that connects the word line to an address pad and is arranged in the dynamic memory cell region in parallel to a word line formed in the dynamic memory cell region, wherein the word line is connected to the address pad of the chip. A semiconductor device characterized in that the dynamic memory cell region is formed parallel to a long side. 2. The common source driving MISFETs for driving the sense amplifiers in the dynamic memory cell area dividedly arranged at both ends are respectively arranged at the ends of the long side of the chip in the dynamic memory cell area, and 2. The semiconductor device according to claim 1, wherein the common source driving MISFETs are connected by a straight common source line. 3. The semiconductor device according to claim 2, wherein the common source line passes above the peripheral circuit.