JPH03214648A - Compaction treatment system - Google Patents

Abstract

PURPOSE:To enhance an integration density as desired by a compaction opera tion and to prevent that an interconnection resistance and a parasitic capacity are increased or become irregular by the compaction operation by a method wherein a pattern is compacted from the lower-rank side of a tree structure grasped from a slice structure and terminals of adjacent patterns are aligned. CONSTITUTION:Since a pattern is compacted from the lower-rank side of a tree structure grasped from a slice structure and terminals of adjacent patterns are aligned, a treatment on the upper-rank side acts in such a way that it does not affect a treatment which has been already completed on the lower-rank side. Consequently, adjacent cell blocks of the slice structure which can be expressed as the tree structure can be connected directly at terminals without a need for a special bent interconnection. Thereby, an integration density can be enhanced as desired by a compaction operation, and it is possible to prevent that an interconnection resistance and a parasitic capacity are increased or become irregular by the compaction operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the compaction of layout patterns, and relates to a technique that is effective when applied to compaction of semiconductor integrated circuits, for example.

[Conventional technology]

So-called CAD (computer aided design)
Alternatively, for layout patterns that are automatically placed and routed by DA (Design Automation), empty areas in the layout pattern may be eliminated to increase integration density, or miniaturized processes may be applied. A computer can perform compaction processing to compress the entire data in order to comply with the rules.

As described in Japanese Unexamined Patent Publication No. 61-224080, a conventional technology for such compaction processing involves first canceling the actual coupling relationship between the compressed area and the surrounding uncompressed area, and then changing the coupling relationship. into a virtual connection relationship,
A technique is provided in which the virtual connection relationship is verified to be a compressed connection relationship, and then a matching compression connection is performed to the compressed area, and a partial compaction of the compressed area is performed.

Examples of other documents describing compaction include: ■; Japanese Patent Application Laid-open No. 1983-78681; ■; I.E.E., Transaction on
Computer Aided Design of Integrated Circuits and Systems Volume 1 C
AD-2 [1983, pages 62 to 69 (IE
EE Trans. on Computer A
ided Design of Tntegra
ted Circujts and System
ms, Vol. ICAD-2 No. 2 pp62
-69 Apri1 1983) ■Advances in CAD for VLSI Volume 4 Chapter 6 Layout compaction (Advances in CAD for
VLSI Vol. 4 Chapter 6 L
ayout Compactlon).

[Problem to be solved by the invention]

By the way, when compacting a layout pattern made up of a set of multiple cell blocks, it is important to note that the positions of terminals to be connected to each other between the compressed cell blocks are connected in a straight line in the X or Y direction. It may not be possible. In such cases, conventional compaction processing technology
The connection had to be made using wiring that bent in the direction. For example, as shown in FIG. 9, when connecting terminals IA to ID of compacted cell block 1 and terminals 2A to 2D of compacted cell block 2, the positions of the respective terminals are shifted in the Y direction. Therefore, cell blocks 1 and 2 cannot be directly adjacent to each other and their terminals cannot be connected. Therefore, the wirings 3A to 3D that bend the corresponding terminals
Must be connected by. A contact hole or the like will actually be formed in the middle of these bent wiring lines 3A to 3D, and an area 3 dedicated to such wiring must be secured between cell blocks 1 and 2. No.

As a result of compaction, a special wiring area is required to connect between cell blocks, and compaction may not be able to increase the integration density as desired, and furthermore, wiring resistance and parasitic capacitance may increase or misalignment may occur. There was also a risk that the operating characteristics would deteriorate due to this.

An object of the present invention is to enable connections between cell blocks or connections between required cell blocks to be made between the terminals of the cell blocks when a layout pattern consisting of a set of a plurality of cell blocks is compacted. The purpose of the present invention is to provide a compaction processing method.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, when compacting a layout pattern composed of a set of multiple cell blocks,
A step of hierarchically slicing all or part of the layout pattern in the X direction and the Y direction to extract a slice structure that can be expressed in the form of a tree structure, and 171 slices of lower cell blocks of the extracted tree structure. The cell block is compressed in the slicing direction, and the compressed cell block is compressed or expanded so as to align the terminals to be connected between the compressed adjacent cell blocks. be.

At this time, if it is not possible to completely execute the terminal alignment step for all cell blocks due to layout rules, etc., the connections between specific compressed cell blocks may be partially Alternatively, bent wiring may be used.

When the layout structure of a plurality of cell blocks is composed of a set of those that adopt the slice structure and those that do not adopt the slice structure, each of the above steps is executed for the portion that adopts the slice structure, and the cell block that adopts the slice structure Flexible wiring can be partially used for interconnection between the wire and the wire that does not have to be used.

The above-mentioned compaction processing method can be applied not only to the layout pattern of the entire semiconductor integrated circuit, but also to the layout pattern of the macro cell-8 used in the standard cell method for configuring the semiconductor integrated circuit. It can also be applied to a layout pattern of a partial circuit block of a circuit.

[Operation] According to the above means, compression of patterns and terminal alignment of adjacent patterns are performed from the lower side of the tree structure understood from the slice structure, so that the processing on the upper side overlaps the already completed processing on the lower side. This enables adjacent cell blocks in a slice structure that can be expressed as a tree structure to be directly connected to each other with their terminals without the need for special bent wiring. . This makes it possible to improve the integration density as desired through compaction, and to prevent wiring resistance and parasitic capacitance from increasing or becoming uneven due to compaction.

[Embodiment 1] FIG. 1 shows a processing procedure of an embodiment of the compaction processing method according to the present invention.

One noise-out pattern targeted for compaction is, although not particularly limited, a layout pattern of the entire semiconductor integrated circuit that has already been designed for placement and wiring, and is stored as a layout library 10.

The layout patterns targeted for compaction are:
Although not particularly limited, it is constituted by a hierarchical set of a plurality of cell blocks and has a so-called slice structure. Here, the slice structure is a method for dividing the cell block area of a semiconductor integrated circuit, for example, by making the entire area into a rectangle and dividing it sequentially in the X and Y directions. Alternatively, the cell block area can be obtained. Regarding the slice structure itself, please refer to the 23rd DA Conference, 1
Pages 01 to 107 1987 (23rd DA
Conference PPIO1 ~ PP107
1986).

An example of the slice structure of the layout pattern is shown in FIG. 3A. The layout pattern shown in the figure is cut in two places in the Y direction and cut in one place in the X direction, and is divided into four cell blocks 11 to 14.

For example, when compacting a layout pattern as shown in FIG. 3A, the slice structure of the layout pattern is recognized based on the layout pattern information and expressed as a tree structure (step Sl).
. Figure 3B represents the slice structure grasped from the layout 1 pattern shown in Figure 3A as a tree structure.
As shown in the figure. The nodes of this tree structure can be cut in the Y direction or
It means a directional cut, and a branch from a node represents a cell block separated by the slice state meant by the node.

When such a tree structure is recognized, the cell blocks are compressed in the slice direction starting from the lower cell blocks of the tree structure, and the positions of the terminals to be connected between the compressed adjacent cell blocks are aligned. The corresponding cell block is compressed or expanded as follows (step 82).
. This process is repeated through step S3 until the branch of the highest node in the tree structure is reached. At this time, necessary layout rules, compaction rules, etc. are given from the LSI structure library 15.

An example of the compaction and terminal alignment step (step S2) is shown in FIGS. 4A to 4G.

In FIG. 4A, ' indicates the relative positional relationship between cell blocks 11 and 12 located at the lowest level of the tree structure in FIG. 3B. For example, in the cell block 11, terminals 16 and 17 are typically shown.
There are terminals 18 and 19 representatively shown in the cell block 12. And cell block 11
．． Terminals 17 and 18 actually exist at the same coordinate position on the boundary side of 12. Note that in this specification, the terminals of the cell block do not particularly mean only the external terminals and electrode pads of the circuit, but can also be understood as specific coordinate positions on the wiring.

The cell blocks 11 and 12 in FIG. 4A are subjected to the required compaction in the Y direction, which is the slicing direction between them, and the compacted state 12 is shown in FIG. 4B. In the figure, lla is a cell block formed by compressing the cell block 11, and 12a is a cell block formed by compressing the cell block 12. As is clear from the figure, the Y coordinate positions of the terminals 1-7 and 19 are different due to the difference in compaction ratio in the Y direction. If the compaction for the cell blocks 11 and 12 is completed in this state, special bending wiring will be required to connect the terminals 17 and 19 at mutually different coordinate positions.

Therefore, in FIG. 4B, terminals 1 with different Y coordinate positions
In order to perform the alignment of 7.19, for example, the cell block 12a is expanded in the Y direction. If necessary for terminal alignment, compression of the cell block lla may also be used. A state in which the terminals 17 and 19 are aligned in this manner is shown in FIG. 4C. In Figure 4C, 11. b,1
2b is the cell block after terminal alignment is completed.

As a result, the positions of the terminals 17 and 19 to be connected between adjacent cell blocks llb and 121) are located at the same coordinates, so that no special bent wiring is required to connect the terminals 17 and 19. no longer needed.

FIG. 4D shows the relative positional relationship of cell blocks 11b, 12b, and 13 that exist below the second node from the bottom of the tree structure shown in FIG. 3B. The cell block 13 has a terminal 20 to be connected to the terminal 16 and a terminal 21 to be connected to the terminal 18. In addition, at the stage of FIG. 4D when compaction in the X direction is not performed, the coordinate positions of terminals 16 and 20 match, and similarly
The 1st coordinate positions match.

Cell blocks llb, 12b, 13 shown in FIG. 4D
, the required compaction is performed in the X direction, which is the slicing direction between them, and the compacted state is shown in FIG. 4E.

In the figure, "-10 is cell block 1". b to X
12C is a cell block formed by compressing cell block 12b in the X direction, 13a is a cell block formed by compressing cell block 12b in the X direction.
is a cell block formed by compressing the cell block 13 in the X direction. Note that each compression rate is individually determined according to compaction rules or layout rules.

As is clear from the figure, due to the difference in the compaction ratio in the X direction for each cell block, the terminals 16 and 20
The X coordinate positions of the terminals 18 and 21 are different. If the X-direction compaction for the cell block is completed in this state, special bent wiring will be required to connect the terminals 16 and 20 and the terminals 18 and 21, which have different coordinate positions.

Therefore, in FIG. 4E, terminals 1 with different X coordinate positions
In order to align terminals 6 and 20 and terminals 18 and 21, for example, cell blocks llc and 12c are stretched in the X direction. Cell block 13a if necessary for terminal alignment
Compression may also be used. The state in which the terminals 16 and 20 and the terminals 18 and 21 are aligned in this manner is shown in FIG. 4F. 1.1d, 12 in Figure 4F
d13b is each cell 1 after terminal alignment is completed.
There are 5 blocks. As a result, the positions of the terminals 16 and 20 and the terminals 18 and 21 to be connected between the adjacent cell block 13 cut in the X direction and the lid, 12d exist on the same coordinates, and the terminals No special bent wiring is required for the connection. Since no compression/expansion in the Y direction is performed in this second layer processing, the results of the first layer processing will not be changed by the second layer processing.

Finally, processing of the third hierarchy is performed, focusing on the topmost node position of the tree structure in FIG. 3B. This process is the same as the first layer, and cell blocks lid, 12d, 13
b, 14 is compacted in the Y direction. At this time,
The compactimine ratios for the cell blocks 11d and 12d are the same. In this process, if the positions of the terminals 22 and 23 and the terminals 24 and 25 are shifted, terminal alignment is performed. The final compaction result is the fourth
This is shown in Figure G. In the same figure, lle, 12e, 13e
, 14e is the finally obtained cell block 16. The layout 1-pattern obtained through this process is stored in the compaction result file 27.

FIG. 2 shows an example of a system configuration applied to the above-mentioned compaction process.

The system shown in the figure is a computer system positioned as a CAD or engineering workstation that can be used for automatic placement and wiring, etc.
30, a main memory 31 such as a RAM (random access memory), an auxiliary storage device 32 such as a disk device, an operation console 33 including a display, a keyboard, etc., and other input/output circuits 34 are commonly connected to a bus 35. connected layout library] ○,
The LSI structure library 15 and the compaction result file 27 are configured by an auxiliary storage device 32. Then, the operation program for compaction is supplied from the main memory 31 or the input/output circuit 34 to the CPU 30, whereby the compaction process is performed according to the procedure shown in FIG.

According to the above embodiment, the following effects are obtained.

(1) Compaction target I - By compressing the pattern from the lower side of the tree structure understood from the slice structure of the pattern and aligning the terminals of adjacent patterns, the processing on the upper layer side is already completed on the lower layer side. While ensuring that the processing performed is not affected in any way,
To achieve that adjacent cell blocks of a slice structure that can be expressed as a tree structure can be directly connected between terminals without requiring special bent wiring.

(2) Due to the effects mentioned above, there is no need for a special bending wiring formation area to connect the terminals of the cell block as in the past, and the integration density can be increased as desired by compaction. .

(3) It is also possible to prevent increases in wiring resistance and parasitic capacitance, as well as their misalignment.

[Example 2] In the above-mentioned Example 1, compaction and terminal alignment were performed for all cell blocks, but as shown in FIG. 5, terminal alignment was performed for some cell blocks 40. You can prevent it from happening. For example, in a tree structure, the terminals 41 and 42 of the cell block 40 sliced at the top layer, the terminal 44 of the cell block 43, and the terminal 46 of the cell block 45 are connected by bent wiring 47, 48.
It will be held in This method is effective in cases where terminal alignment cannot be performed for all cell blocks due to layout rules and the like. In this case, Example 1 is also applied to cell blocks 40, 43, 45, and 49.
has the same effect.

[Embodiment 3] The present invention can also be applied to a semiconductor integrated circuit in which all cell blocks do not have a completely sliced structure.

For example, as shown in FIG. 6A, when the layout structure of a plurality of cell blocks 51 to 55 is composed of a set of cells that adopt the slice structure and cells that do not adopt the slice structure, a slice structure 19 is adopted. The steps shown in FIG. 1 are executed for the cell blocks 51 to 54 to perform compaction and terminal alignment, and only the compaction is performed for the cell block 55 which does not have a slice structure. The cell blocks reduced by compaction are shown as 51a-55a in FIG. 6B. Interconnection between the cell block 55a corresponding to the cell block 55 that does not adopt the slice structure and other cell blocks is performed by bent wires 56 to 58, as shown in FIG. 6B. This embodiment also has the same effect as the first embodiment for the cell blocks 51 to 54 having a slice structure.

[Embodiment 4] In the above embodiment, the case where the layout pattern of the entire semiconductor integrated circuit is subjected to compaction processing has been explained. The present invention can also be applied to compaction processing of layout patterns of partial circuit blocks of semiconductor integrated circuits.

For example, FIG. 7 shows an example of a schematic layout pattern of a RAM. In the figure, 60 is a memory cell, 61 is a memory cell array formed by arranging memory cells in a matrix, 62 is a row address decoder made up of a set of logic gates 63, and 64 is a column address made up of a set of logic gates 65. It is a decoder. In this way, a memory such as a RAM has a slice structure in which a large number of basic unit circuits such as memory cells 60 and logic gates 63 and 65 are repeatedly arranged. In the case of this RAM, although not particularly limited, the compaction process is performed by understanding the memory cells 60, logic gates 63, 65, etc. as cell blocks.

FIG. 8 shows a schematic layout pattern of arithmetic units included in a CPU or the like. In the figure, 70 is a driver, 71 to 73 are I-no registers, and 74 is an arithmetic and logic unit. This arithmetic unit 1. has a slice structure in which unit circuit blocks each having an individual function are arranged. In the case of this arithmetic unit, although not particularly limited, the compaction process is performed by understanding each unit circuit block as a cell block.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, the cell blocks targeted for compaction can be arbitrarily set from basic cells to macro cells depending on the scale of compaction, the hierarchical processing method of compaction, and the like. In addition, the above-mentioned compaction process can be used to eliminate empty areas of a layout pattern that has been automatically placed and routed in order to increase the integration density, or to reduce the size of an LSI in order to comply with miniaturized process rules. It is used when compressing the entire circuit block or a required circuit block.

In the above description, the invention made by the present inventor was mainly applied to compaction of layout patterns of semiconductor integrated circuits, which is the background field of application of the invention, but the present invention is not limited thereto. It can be widely applied to the compaction of various layout patterns such as wiring patterns.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, by compressing patterns and aligning the terminals of adjacent patterns from the lower side of the tree structure ascertained from the slice structure of the layout pattern to be compacted, the processing on the upper layer side will not interfere with the processing that has already been completed on the lower layer side. While ensuring that there is no impact on
Adjacent cell blocks in a slice structure that can be expressed as a tree structure can be directly connected to each other through terminals without the need for special bent wiring.

This makes it possible to improve the integration density as desired through compaction, and to prevent wiring resistance and parasitic capacitance from increasing or becoming uneven due to compaction.

By partially connecting compressed specific cell blocks with bent wiring, it is possible to completely perform the terminal alignment step for all cell blocks in relation to layout 1 rules, etc. We can also handle cases where this is not possible.

The layout structure of multiple cell blocks can be created by executing each of the above steps for sections that adopt a slice structure, and by partially using bent wiring for interconnection between sections that adopt a slice structure and those that do not. It is also possible to deal with the case where the data is composed of a set of those that adopt the above-mentioned slice structure and those that do not.

[Brief explanation of drawings]

-24 Fig. 1 is a procedure explanatory diagram of a compaction processing method according to an embodiment of the present invention, Fig. 2 is a block diagram of an example of a system configuration for performing the compaction processing method, and Fig. 3A is an example of a compaction target layout pattern. Explanatory diagram, Figure 3B is a tree structure diagram expressing the slice structure extracted from the layout pattern of Figure 3A, and Figures 4A to 4
Figure G is an explanatory diagram of the processing state according to the process flow of compacting the layout pattern of Figure 3A, Figure 5 is an explanatory diagram of the processing results when compaction and alignment are not performed for some cell blocks, 6A and 6B are explanatory diagrams of processing states when all cell blocks do not have a slice structure. FIG. 7 is an explanatory diagram of a schematic layout pattern of a RAM to which the method of the present invention is applied. FIG. 9 is an explanatory diagram of a schematic layout pattern of an arithmetic unit to which the invention method is applied. FIG. 9 is an explanatory diagram showing a connection state between cell blocks according to a conventional method. 11-14... Cell block, 16-25... Terminal, 30... CPU, 31... Main memory, 32...
Auxiliary storage device, 40... Cell block, 46.47.
・Bending wiring, 51-55...Cell block, 56-5
8... Bent wiring, 61... Memory cell array, 62
Row address decoder, 64... Column address decoder, 70... Driver, 71-73 Register, 74
Arithmetic logic unit. \r ba) ``)

Claims (1)

[Claims] 1. In a method of compacting a layout pattern constituted by a set of a plurality of cell blocks, all or part of the layout pattern is hierarchically sliced in the X direction and the Y direction to form a tree structure. A step of extracting a slice structure that can be expressed in the form of , compressing the cell blocks in the slice direction starting from the lower cell block of the extracted tree structure, and compressing the compressed adjacent cell blocks to be combined. A compaction processing method comprising the step of compressing or expanding a corresponding cell block so as to align terminal positions. 2. Compressing a predetermined cell block in the slicing direction, and wiring to bend the terminals of the cell block whose terminals have not been aligned in the above step and the terminals of the cell block to be connected adjacent thereto. 2. The compaction processing method according to claim 1, further comprising the step of connecting with. 3. The layout structure of a plurality of cell blocks is hierarchically sliced in the X and Y directions and can be expressed in the form of a tree structure. A layout pattern is created by a set of slice structures that have a slice structure and those that do not. In the compaction method, there is a step of extracting a slice structure that can be expressed as a tree structure from the layout pattern, and compressing the cell blocks in the slice direction in order from the lower cell blocks of the extracted tree structure. Compressing or expanding the corresponding cell blocks so as to align terminals to be connected between adjacent cell blocks; compressing cell blocks that do not have a slice structure in the slice direction; and compressing the compressed slice structure cell blocks. A compaction processing method comprising the steps of: connecting a terminal of a compressed uncompressed slice structure cell block to a terminal of the compressed uncompressed slice structure cell block with a bending wiring; 4. The compaction processing method according to claim 1, wherein the layout pattern to be compacted is a layout pattern of a macro cell used in a standard cell method for configuring a semiconductor integrated circuit.