JPH03211914A - Variable delay circuit and timing generating device using its circuit - Google Patents

Abstract

PURPOSE:To diagnose the fault of a delay element of a delay circuit by only a simple logical test, and to easily detect the fault of the delay circuit caused by a faulty delay element of the delay circuit by providing a selecting circuit for selecting an output of an input capacitance control differential gate. CONSTITUTION:An input differential gate 10a for inputting an input signal, an output differential gate 10b connected to an output terminal of the input differential gate 10a, input capacitance control differential gates 11a-11c, 12a-12c which are connected to the output point of the input differential gate 10a and can control the input capacitance, and a selecting circuit 13 for selecting outputs of the input capacitance control differential gates 11a-11c, 12a-12c are provided, and by executing the turn-on/turn-off control of a current source of the input capacitance control differential gates 11a-11c, 12a-12c being delay elements, the parasitic capacitance of an output end of the input differential gate 10a is varied, the propagation time of a signal is varied, and its output is observed by the selecting circuit 13. In such a way, an output of arbitrary input capacitance control differential gates 11a-11c, 12a-12c can be selected, a fault of the respective input capacity control differential gates 11a-11c, 12a-12c can be diagnosed, and this circuit can be used for a timing generating device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a delay circuit and a device thereof, and particularly relates to a delay circuit and a circuit thereof that are easy to diagnose failures of and suitable for LSI integration. The present invention relates to the timing generator used.

[Conventional technology]

Conventional variable delay circuits are
&D, Voor 311. Nan/(-5, (19)
89) Paragraphs 537 to 546 (NTTR&D Vo
l, 5B No. 5 (1989) PP557-54
As described in 6), a differential pair of transistors inputs the digital input signal, a load resistor provided on the collector side of the transistor pair, an emitter follower that outputs the voltage fluctuation of this load resistor, and an emitter 7 follower. It consists of a transistor junction capacitance added to the emitter. A desired delay time can be obtained by arbitrarily selecting a delay circuit in which the transistor junction capacitance serving as a delay element is weighted. In this delay circuit, the delay element is a transistor junction capacitance, and in order to detect an M delay error due to a failure of this transistor, it is necessary to actually operate the delay circuit and accurately measure the amount of change in delay time.

[Problem to be solved by the invention]

In the above conventional technology, since the delay element is a transistor junction capacitance, it is difficult to judge whether the delay i element is formed normally. Therefore, it is necessary to measure the amount of change in delay time at all set values of the delay circuit. Generally, the amount of change in delay time is measured by
The time difference with the reference signal is measured using an interval counter, but it takes a long time to measure because the measured value is obtained by taking the average of several measurements. Commercially available testers have low timing resolution and have the drawback of not being able to accurately select non-defective ICs (ICs) that incorporate this delay circuit.

An object of the present invention is to construct a delay element of a variable delay circuit by an input capacitance controlled differential gate, and to provide a means for mIMing the output of the input capacitance controlled differential gate. A variable delay circuit that can easily detect failures in delay circuits due to element defects without measuring delay time, and
An object of the present invention is to provide a timing generation device using the circuit.

(Means for Solving Problem 1m) In order to achieve the above object, in the present invention, an input signal is input to an input differential gate, and one or more input capacitance controlled differential gates are connected to both the positive and negative outputs of the input differential gate. The signal propagation time is controlled by controlling the current source of the input capacitance control differential gate, which is a delay element, on and off to change the parasitic capacitance at the output terminal of the input differential gate. In the delay circuit that can change the input capacitance control differential gate, the output of the input capacitance control differential gate is input to the selection circuit and the output is observed, thereby detecting a failure of the input capacitance control differential gate. shall be.

[Effect]

The output of the input capacitance controlled differential gate of the Kaminori delay circuit is input to the selection circuit, and by switching the selection signal of the selection circuit, the output of any input capacitance controlled differential gate can be selected. Therefore, it is possible to diagnose the failure of each input capacitance controlled differential gate, and this variable delay circuit can be used in a timing generator.

【Example〕

Examples of the present invention are shown below. ! This will be explained with reference to Figure 4.

The first factor is a block diagram of an embodiment of a variable delay circuit provided with a diagnostic function according to the present invention. In Figure 1, the variable delay circuit is an input differential circuit that receives inputs M 1a and lb.
10m and the output signal 2a* of the input differential gate 10a
An output differential goo zob inputs 2b and outputs an output signal 5ae3b.

Input capacitance control differential gates 11a to 11o, 12mwo which input the output signal 2m+2b of the input differential gate 10a and are controlled by the control signal 4.5.

Input capacitance control differential gate output ff4f6o, 70.8
The selection circuit 15 outputs 0.

The operation of the delay circuit in FIG. 1 will be explained using FIG. 2. a + 1) e O in Figure 2 is the input signal 1a, 1b in Figure 1 and the output signal 2m of the input differential gate 10a.
+2b and the output signal 3m of the output differential gate 10b
, 5b is a dynamic waveform diagram of FIG.

First, when the control signals 4 and 5 are set to ``L'' level, the input signal 1m has a waveform shown by aK in FIG.

1b is input to the input differential gate 10m, the output signal 2m $ 2b of the input differential gate 10a becomes bo! in FIG. j! The waveform is shown as a line. This output signal 2a, 2
b is input to the output differential gate 10b, and oo in the #I2 diagram
An output signal S a ebb having a waveform indicated by a solid line is obtained.

Next, when the control signal 4 is at H'' level, the input capacitance control differential gate lla.

The capacity of the 12m input end increases. Therefore, the input differential gate 10aO output M 2a, 2b (D waveform is indicated by the broken line b in Fig. 2 because the input capacitance of the input capacitance control differential gates 11m, 12m increases and is charged and discharged nine times more. This output signal 2a*2b is input to the output differential gate 10bK, and an output signal 5a*3b having the waveform shown by the broken line 00 in FIG. 2 is obtained.In this way, the input differential gate The waveforms of the output signal 2 a h 2 b of the 10 m and the output signals 3 m and 5 b of the output differential gate 10 b are the input capacitance controlled differential gates. Faith f2a
, 2b, and 5m, 5b waveforms are shifted in time, so the output signal 5a a is changed from the input signals 1a and 1b.
Even if the propagation time up to 5b changes, the delay time can be controlled.

Next, a method for diagnosing the failure of the input capacitance controlled differential gate serving as a delay element will be described. Here, the selection circuit 13 is
According to the selection signal 9, the input gN numbers 6a and 6b, 7a and 7b,
It is assumed that 8a and 8b are selected as diagnostic output signals 6o, 7o, and 8o, respectively.

First, input capacitance control differential controllers 11a and 11b.

11o, by controlling the selection signal 9, the input capacitance control differential group) 11a, 11b.

11o output value f6 m + 7 a * 8 a,
The diagnostic output signals 6o, 7o, and 8o are respectively output. The input signal 1a is set to the "H" level so that the output value f2b of the input differential control signal 10a is set to the "L" level, and the control signal 9 is set to the "H" level.
4.5 to the "L" level. At this time, confirm that the diagnostic output signals fPI numbers 6o, 7o, and 8° of the iN selection circuit 15 are at the "L" level. If the diagnostic output signals 6c,
If 7o and 8o are at llH'' level, the input capacitance control differential gates 11a and 11b.

It can be seen that 11o is a fixed output "H" failure.

Similarly, input capacitance control differential) 11a-am12a=
The output value of 10a is 92 a
v 2 b and control @f4.5 are opened to perform fault diagnosis.

FIG. 3 is a block diagram showing another embodiment of diagnosis of an input capacitance controlled differential gate. In FIG. 5, the variable delay circuit has an input differential gate 10a which inputs an input signal 1a*1b, and output signals 2a, 2 of the input differential gate 10a.
b is input and output signal 3 a a S b is output (output differential goo) 10b, and input differential goo) 10a output signal 2 a + 2 b is input and controlled by control signal 4.5. Input capacitance control differential goo) 11 a-c,
12 Hatake wo and input capacitance control differential goo F 11 a
-or 12 a~0 output signals 6a and 6b +
Input 7a and 7b, 8a and 8b, 1 diagnostic output value number 6
It is composed of logical sum (G)14axc which outputs o+7c+8o. Input capacitance control differential goo) 11a in Fig. 3,
12aC) Explain the diagnostic method. First, control signal J
When ij4 is set to ``L level, input differential gate 1
1m output signal 2, 2b is "H" level or H"l,
”No matter which level, input capacitance control differential goo)
11a.

The output signals 6m and 6b of 12a both become "L" level, and the diagnostic output signal 6ct of 14m is logically summed! It becomes "L" level. Here, in Ka9, Kugata capacitance control differential gate 11
If the output signal 6a has an output "H#" level failure, the output signal 6a of the input capacitance control differential controller 11a will be at the "H" level, and the diagnostic output signal 6o will also be at the "H" level. In other words, the logic output for the input of the input capacitance controlled differential gate is incorrect.C,! I can see that i4 is working. Therefore,
# By observing the disconnected output signal 6o, it can be confirmed that one or both of the input capacitance control differential gates 11a and 12a has a fixed output 'H' level failure.

If both of the input capacitance control differential groups F 11 a # 12 a are fixed at “H” level, the delay time cannot be controlled by the control signal 4. Also, one or the other”
If it is an H" level failure, only one of the output signals 2am 2b of the input differential gate 10a will be delayed, and normal operation will not occur.

Next, when the control signal 4 is set to the "H" level and the input signal 1at of the input differential gate 10m is set to the "H" level, the output signal 2a of the input differential gate 10a is "a""" Level shift, input capacitance control differential control) 12m output signal 6b
becomes "H" level.

Further, at this time, since the output value t2b of the input differential goo) 10m of the input differential goo) 10m is at the 1L" level, the output signal 6a of the input capacitance control differential gate 11& becomes the "L level. Therefore, the diagnostic output signal 6o of the OR gate 114a becomes "H" level. Here, assuming that the input capacitance control differential gate 12a has a fixed failure at the output ``L'' level, the diagnostic output 6c of the OR gate 14a is l'
Since the level is L'', the input capacitance control differential gate 12a
A fixed output "L" level failure can be determined. Similarly, the control@signal 4 is set to llH" level, and the input differential gate 10a
When the input signal 1a of the input capacitance control differential gate 11a is set to the "L" level, it can be determined that the output of the input capacitance control differential gate 11a is fixed at the "L" level.

In the above embodiment, the input capacitance control differential (G) Ha~0.
Although the description has been made using a pair of positive and negative electrodes of 12a''o, the present invention is not limited by the number of positive and negative electrodes, and fault diagnosis of a variable delay circuit using a plurality of input capacitance controlled differential gates is possible.

FIG. 4 is a block diagram showing an embodiment of a timing generation device using a variable delay circuit according to the present invention. In FIG. 4, the timing generation device includes a synthesizer 15 that generates a reference clock 15a, a counter 16.17 that counts the reference clock 15a of the synthesizer 150, and counters 16a and 17a that are used to complete counting of the counter 16.17, respectively. , delay circuits 18 and 19 that analog-delay within one period of the reference clock, and a selection circuit 20 that selects the input capacitance control differential gate output signals 18c and 19c in the delay circuit. With this configuration, the reference clock 15& generated by the synthesizer 15 is counted by the counters 1B and 19, and the number-of-lights end signals 16a and 17a are output. Variable delay circuit 1B.

19 is the counter 16. t7 counting completed 1g issue 16a17
A signal analog-delayed by one cycle of the reference clock 15a is output as a timing signal 18m+19m according to the setting signals 18b and 19b. According to this embodiment, since the input capacitance controlled differential gate is used as a delay element of the variable delay circuit and its output is observed, delay time errors due to failure of the delay element can be corrected by accurately determining the delay time Klf.
It can be detected without determining fIJ.

〔Effect of the invention〕

According to the present invention, a failure in a delay element of a delay circuit can be detected with only a simple logic test, so a failure in a delay circuit due to a defective delay element in a delay circuit can be easily detected.

[Brief explanation of drawings]

w, Figure 1 is a block diagram of one embodiment of a variable delay circuit equipped with a fault diagnosis circuit according to the present invention, Figure 2 is an operation waveform diagram showing changes in delay time according to Figure 1, and Figure 5 is another embodiment. FIG. 4 is a block diagram of a variable delay circuit according to an example fault diagnosis, and FIG. 4 is a block diagram of a timing generator according to the invention. 10a... Input differential gate, 10b... Output differential gate, 11a-o, 12a"o... Input tea tray control differential gate, 13... Selection circuit, 14a"o... Logical OR Gate, 15...Synthesizer, 16.17...Counter, 18.19...Variable delay circuit, 20...Selection circuit

Claims (1)

[Claims] 1. An input differential gate that receives an input signal, an output differential gate that connects to the output of the input differential gate, and an input capacitance that connects to the output of the input differential gate can be controlled. A variable delay circuit comprising an input capacitance controlled differential gate and a selection circuit for selecting an output of the input capacitance controlled differential gate. 2. The variable delay circuit according to claim 1, wherein the outputs of the input capacitance controlled differential gates are ORed. 3. A timing generator comprising a counter connected to the input of the variable delay circuit according to claim 1.