JP2023527258A - Timing event detector, microelectronic circuit, and timing event detection method - Google Patents

Abstract

In microelectronic circuits, digital values (D) are temporarily stored in register circuits 101 . With respect to the permissible time limit defined by the trigger signal (CKP), the corresponding instantaneous values of the digital value (D) are stored in differential form including the instantaneous value (A) and its complement (B). During the timing event detection window, the stored instantaneous value (A) is toggled only in response to the observation of a change in one direction of the digital value (D), and its stored complement value (B) is changed to the digital value (D Either the stored instantaneous value (A) or its stored complement value (B) is toggled so that it is toggled only in response to observation of a change in the opposite direction of (A). The stored instantaneous value (A) is compared to its stored complement value (B) and the timing event observation signal (TEO) is the stored instantaneous value (A) and its stored complement value (B). are output 105 in response to said comparison indicating that are equal. [Selection drawing] Fig. 1

Description

The present invention relates to the art of microelectronic circuits that include internal monitors that detect timing events. In particular, the present invention relates to an advantageous circuit element level implementation of a timing event detection circuit.

Time borrowing in microelectronic circuits means that a circuit element can temporarily borrow time from a subsequent stage, i.e. the data being processed by a subsequent circuit element in the same processing path. If the digital value can be handled without corrupting the , it means that the circuit element changes the digital value slower than expected. Time borrowing may be combined, for example, with Advanced Voltage Scaling (AVS), whereby the occurrence of time borrowing is detected as a timing event, and as the number of detected timing events increases, The operating voltage increases and vice versa. The number of timing events detected also triggers other compensatory actions, typically prompting changes in the value of other operating parameters of the circuit such as the clock frequency or temporarily changing the clock waveform. can be made

The processing path of the microelectronic circuit passes through the logic unit and the register circuit, and the register circuit detects the rising edge or falling edge of the trigger signal (if the register circuit is a flip-flop) or the high level of the trigger signal. or low (if the register circuit is a latch) to store the output value of the previous logic unit. A trigger edge of a trigger signal or other control event defines an allowable time limit before which a digital value can appear at the data input of the register circuit before it can be properly stored. The allowable time limit is defined in some relation to the allowable time limit, not necessarily the exact instant of the trigger edge, but physical influences such as the finite speed at which the voltage level can change. A logic unit may be referred to as an element of combinatorial logic.

A monitor circuit is used to detect timing events. It may alternatively be referred to as a timing event detection circuit, although the term monitor circuit is shorter and more practical. A monitoring circuit is typically added to or associated with the register circuit to generate a timing event observation (TEO) signal as a response to changes in the input digital value occurring later than the allowable time limit. A configured circuit element or function. In addition to the actual monitoring circuitry, microelectronic circuits must include OR trees and/or other structures that collect, process, and analyze the TEO signals from the monitoring circuitry. The monitoring circuit may be used as a stand-alone device for other applications, such as edge detectors in digital phase-locked loops.

The main drawback of monitoring circuits is that they consume circuit area and operating power. Many known monitoring circuit implementations also involve performance compromises.

Testability requirements further complicate the task of designing microelectronic circuits. The concept of DFT (Designed For Testability, or Design-For-Test) has become a de facto industry standard defining specific procedures for testing microelectronic circuits. there is As an example, a register circuit contained in a microelectronic circuit could be selectively coupled into a long chain that essentially acts as a shift register into which a series of digital values can be input at one end and read from the other end. . Passing a known test pattern to a chain of such register circuits and checking the format of the test pattern at the output will determine whether all register circuits in the chain change their state as desired, or to a certain value. It is possible to know whether there is a register circuit that is stuck in (stuck-at fault test). Full-speed fault testing involves slowly entering a test pattern at a low clock speed, then applying one or more clock pulses at full operating speed so that the test pattern steps at the functional logic speed for as many steps as there are clock pulses. Let it progress in the chain and finally clock out the test pattern again at a lower clock speed. A speed test can give information about register circuits that are slower than intended. If supervisory circuits and time-borrowing capabilities are included, these must also be testable.

The present invention is a timing event detector, a microelectronic circuit, and a microelectronic circuit that requires limited silicon area and consumes a limited amount of power while allowing monitoring for timing events. The goal is to provide a way to make it work. It is a further object to enable detection of timing events in a reliable manner even at very low operating voltage levels. It is a further object to conform the monitoring of timing events to the DFT standard method.

It is an object of the present invention to use a monitoring device based on parallel one-way latches to compare the outputs of such latches and monitor comparators that can selectively freeze the results of such comparisons with an external control signal. This is achieved by equipping the device.

In a first aspect, a timing event observation signal is provided as a response to a digital value change at the input of an associated register circuit that occurs later than the allowable time limit defined by the trigger signal. A timing event detector circuit for generating is provided. The timing event detection circuit has a data input configured to receive the digital value, a clock signal input configured to receive the trigger signal, and a timing event observation signal to output. and a configured timing event observation output. The timing event detection circuit is configured to store corresponding instantaneous values of the digital values with respect to the allowable time limits in differential form including the instantaneous values and their complements. The timing event detection circuit is configured such that, during a timing event detection window following the allowable time limit, each of the stored instantaneous values or their stored complements is observed to change in a respective one direction of the digital value. It is configured to toggle one of said stored instantaneous value or its stored complement value in response to an observed change in said digital value, such that it is toggled only in response. The timing event detection circuit compares the stored instantaneous value with its stored complement value during the timing event detection window, wherein the stored instantaneous value equals its stored complement value. is configured to output the timing event observation signal in response to the comparison indicative of a.

In a second aspect, a timing event detection circuit that produces a timing event observation signal in response to a digital value change at an input of an associated register circuit that occurs later than the allowable time limit defined by the trigger signal. I will provide a. The timing event detection circuit has a data input configured to receive the digital value, a clock signal input configured to receive the trigger signal, and a timing event observation signal to output. and a configured timing event observation output. The timing event detection circuit is configured to store corresponding instantaneous values of the digital value with respect to the allowable time limit in a parallel double form comprising two copies of the instantaneous value. The timing event detection circuit is configured such that during a timing event detection window following the allowable time limit, a first copy is toggled only in response to observation of a change in one direction of the digital value and a second copy is toggled to the digital value. configured to toggle one of the stored copies of said instantaneous value in response to an observed change in said digital value, such that it toggles only in response to an observed change in said value in the opposite direction. be. The timing event detection circuit compares stored copies of the instantaneous values during the timing event detection window and, in response to the comparison indicating that the stored copies of the instantaneous values are unequal, the timing event detection circuit. configured to output an event observation signal;

In one embodiment, the timing event detection circuit includes a respective latch data input each coupled to the data input, a respective output, and a respective latch clock input coupled to the clock signal input. a first unidirectional latch circuit and a second unidirectional latch circuit having ends. A unidirectional latch circuit of this kind stores its input data at the beginning of an enable pulse of said trigger signal and only if the value of its input data changes in a predetermined direction during said enable pulse of said trigger signal. A circuit element configured to toggle its output. This has the advantage of providing a particularly simple implementation with only a limited number of transistors.

In one embodiment, both the first unidirectional latch circuit and the second unidirectional latch circuit change in a direction such that the value of the corresponding input data is the same for both of the unidirectional latch circuits. and the timing event detection circuit is configured to toggle their outputs only when the timing event detection circuit is connected to the data input and one of the first unidirectional latch circuit and the second unidirectional latch circuit. between, storing the corresponding instantaneous value of said digital value in said differential form including said instantaneous value in one unidirectional latch circuit and said complement value in the other unidirectional latch circuit. This has the advantage that identical circuit elements can be used as both of the two one-way latch circuits, simplifying the design.

In one embodiment, storing corresponding instantaneous values of said digital values in differential form, including said instantaneous values and their complements, is implemented in voltage mode CMOS logic. This has the advantage that floating nodes and other drawbacks of current mode logic are avoided.

In one embodiment,
- each of said first one-way latch circuit and said second one-way latch circuit comprises a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third transistor, respectively; 7 transistors and an eighth transistor, wherein the first transistor, the fourth transistor, the fifth transistor and the seventh transistor are PMOS transistors; and the eighth transistor are NMOS transistors,
- said timing event detection circuit comprises an upper voltage rail and a lower voltage rail, with its source coupled to said lower voltage rail and its gate coupled to said clock signal input; a coupled NMOS type enabler transistor;
- in each of said first one-way latch circuit and said second one-way latch circuit,
- the source of the first transistor is coupled to the upper voltage rail;
- the drain of the first transistor is coupled to the source of the fourth transistor;
- the drain of the fourth transistor is coupled to the drain of the second transistor;
- the source of the second transistor is coupled to the drain of the enabler transistor;
- the gate of the first transistor and the gate of the second transistor are coupled together and constitute latch data inputs of the respective one-way latch circuits;
- the source of the fifth transistor is coupled to the upper voltage rail;
- the drain of the fifth transistor is coupled to the drain of the sixth transistor;
- the source of the sixth transistor is coupled to the drain of the enabler transistor;
- the gate of the fifth transistor and the gate of the third transistor are coupled together and constitute latch clock inputs of the respective one-way latch circuits;
- the gate of the fourth transistor and the gate of the sixth transistor are coupled together;
- the source of the seventh transistor is coupled to the upper voltage rail;
- the drain of the seventh transistor is coupled to the drain of the eighth transistor;
- the source of the eighth transistor is coupled to the lower voltage rail;
- the gate of the seventh transistor and the gate of the eighth transistor are coupled together;
- a point between the drain of the seventh transistor and the drain of the eighth transistor is coupled to the gate of the fourth transistor and the gate of the sixth transistor;
- the output of each said one-way latch circuit is connected to the gate of the seventh transistor and the gate of the eighth transistor, the drain of the fifth transistor and the drain of the fourth transistor, and the sixth transistor; It consists of the junction of the drain of a transistor and the drain of said second transistor.

This has the advantage that the timing event detection circuit can be implemented with relatively few transistors, saving silicon area and lowering power consumption.

In one embodiment, the timing event detection circuit includes a control signal input and resets the timing event observation signal at a predetermined instant during each pulse cycle of the trigger signal, thereby resetting the first detection signal at the control signal input. said second control signal value at said control signal input by maintaining said timing event observation signal during the period in which said second control signal value appears at said control signal input in response to a control signal value of one; configured to respond to This has the advantage that the timing event detection circuit can be DFT compliant.

In one embodiment, the timing event detection circuit is configured to reset the stored value to a fixed default value at the end of a detection window, the end of the detection window being defined with respect to the trigger signal and the permissible Done after a time limit. This comes with the advantage that the monitoring cycle can be easily restarted at each instant that a timing event may occur.

A processing path according to a third aspect, comprising a logic unit and a register circuit, wherein the register circuit is configured to temporarily store the output value of the logic unit in synchronization with a trigger signal. A microelectronic circuit comprising: The microelectronic circuit includes at least one timing event detection circuit of the type described above, the timing event detection circuit being associated with one of the register circuits to detect a timing event observation signal defined by the trigger signal. configured to be generated as a response to a digital value change at the input of the associated register circuit that occurs later than the permissible time limit.

In a fourth aspect, a method of operating a microelectronic circuit is provided. The method includes:
- temporarily storing the digital value in a register circuit synchronously with the trigger signal;
- with respect to the permissible time limit defined by the trigger signal, storing corresponding instantaneous values of said digital values in differential form comprising said instantaneous values and their complements;
- during a timing event detection window following said allowable time limit, each of said stored instantaneous values or their stored complement values is toggled only in response to observation of a change in said respective one direction of said digital value; toggling either the stored instantaneous value or its stored complement value as
- comparing the stored instantaneous value with its stored complement value during the timing event detection window;
- outputting a timing event observation signal in response to said comparison indicating that said stored instantaneous value and its stored complement value are equal.

In a fifth aspect, a method of operating a microelectronic circuit is provided. The method includes:
- temporarily storing the digital value in a register circuit synchronously with the trigger signal;
- storing in two copies the corresponding instantaneous values of said digital value with respect to the permissible time limit defined by said trigger signal;
- during a timing event detection window following said allowable time limit, toggle either of said two copies such that each copy is only toggled in response to an observation of a change in said digital value in its respective one direction; and
- comparing the two copies during the timing event detection window;
- outputting a timing event observation signal in response to said comparison indicating that said two copies are different.

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 shows a monitoring circuit associated with a register circuit. FIG. 2 shows a monitoring circuit associated with the register circuit. FIG. 3 shows a logic gate level implementation of an exemplary monitoring circuit. FIG. 4 shows a state diagram of the monitoring circuit. FIG. 5 shows a timing diagram of the signals in the monitoring circuit. FIG. 6 shows a timing diagram of the signals in the monitoring circuit. FIG. 7 shows a transistor-level implementation of the monitoring circuit. FIG. 8 shows a prior art implementation of a monitoring circuit. FIG. 9 shows the method. FIG. 10 shows the method.

Microelectronic circuits and methods for their design and operation are described below. A typical microelectronic circuit includes multiple logic units and register circuits arranged in multiple processing paths. A processing path is a series of circuit elements through which digital data is processed in logic units and temporarily stored in register circuits located between successive logic units in the processing path. The software that the microelectronic circuit runs defines how and which processing paths are used at any given time.

FIG. 1 shows register circuit 101 and associated monitor circuit 102 . The data input of register circuit 101 is marked with the letter D and the data output of register circuit 101 is marked with the letter Q. FIG. The register circuit 101 and its associated monitor circuit 102 may be part of a processing path in the microelectronic circuit whereby previous elements in the processing path produced the digital value appearing at the data input D. , subsequent elements in the processing path receive the digital value appearing at the data output Q. Temporary storage of data in the register circuit 101 is performed in synchronization with a clock pulse signal CKP, which may be abbreviated as a clock signal. A clock signal may be referred to as a trigger signal because it can be said to trigger the temporary storage of data. Monitoring circuit 102 may alternatively be referred to as a timing event detector circuit.

In order to ensure correct operation of the microelectronic circuit, any change in the digital value temporarily stored in the register circuit 101 was defined by the clock signal CKP (or more generally by a suitable trigger before the respective allowable time limit (defined by the signal). For example, it is common to think of the rising and/or falling edges of the clock signal CKP as permissible time limits, but for example the finite time it takes for a semiconductor switch to change from a non-conducting state to a conducting state and vice versa. Due to time, the actual allowable time limit may not exactly match such an edge. For the purposes of this discussion, it is sufficient to assume that there is a known relationship between the type of trigger signal and the occurrence of permissible time limits.

The purpose of the monitoring circuit 102 is to detect the timing event observation signal TEO at the input of the associated register circuit 101 that occurred later than the allowable time limit defined by the trigger signal (clock signal) CKP. generated as a response to changes in the digital value in D. To this end, the monitoring circuit 102 includes a data input 103 arranged to receive the digital value D, a clock signal input 104 arranged to receive the trigger signal CKP, and a timing event observation signal. and a timing event observation output 105 configured to output TEO.

The monitoring circuit 102 is arranged to store corresponding instantaneous values of the digital value D in differential form with respect to the allowable time limit. This means that the monitoring circuit 102 is arranged to store both the instantaneous value of the digital value D and its complement. On the monitoring circuit 102 side, the actual instantaneous value is marked as D and the complement value is marked as ~D (tilde D). To generate the complement values ˜D, the monitoring circuit 102 of FIG. 1 is shown schematically to include an inverter 106 coupled to the data input 103 .

The two parallel circuit elements 107 and 108 used to temporarily store the data value D and its complement ˜D are referred to in FIG. 1 as a unidirectional latch circuit. For the purposes of this description, a one-way latch circuit stores its input data at the beginning of the enabling pulse of the trigger signal and changes the value of its input data in a given direction during the enabling pulse of the trigger signal. A circuit element configured to toggle its output only when it changes. The output signals from unidirectional latch circuits 107 and 108 are marked as A and B respectively. For simplicity, it may now be assumed that A and B are directly the digital values last stored in the respective one-way latch circuits 107 and 108 .

In the exemplary embodiment of FIG. 1, clock signal CKP acts as a trigger signal for both unidirectional latch circuits 107 and 108 . As an example, assume that an enable pulse of the type described above is an active pulse of clock signal CKP (ie, CKP=1). In addition, the unidirectional latch circuits 107 and 108 respond only to changes in their input data from 0 to 1 (“0 to 1” stands for “0 to 1”), ie they are in the rising direction. is unidirectional to . If the digital value D is 0 at the rising edge of the clock signal CKP, the first unidirectional latch circuit 107 stores D=0 and the second unidirectional latch circuit 108 stores ˜D=1. . The stored values are visible at their outputs, ie A=0 and B=1. Now, when the digital value D changes from 0 to 1 while the clock signal CKP remains high, the upper one-way latch circuit 107 detects a 0->1 change in its input data and thus its stored value. Toggle the value Conversely, the lower one-way latch circuit 108 does not toggle its stored value because it detects a 1->0 change in its input data. As a result, after a 0->1 transition of digital value D occurring during the enable pulse of clock signal CKP, the outputs of unidirectional latch circuits 107 and 108 are A=1 and B=1.

As another example, all other assumptions above can be maintained, except that digital value D is 1 on rising edges of clock signal CKP and falls to 0 during active clock pulses. Thus, the first unidirectional latch circuit 107 initially stored D=1 and the second unidirectional latch circuit 108 stored ˜D=0. The stored values are again visible at their outputs, ie A=1 and B=0. When the digital value D changes from 1 to 0 while the clock signal CKP remains high, the upper one-way latch circuit 107 senses a 1->0 change in its input data, so that its stored value do not toggle. The lower one-way latch circuit 108 toggles its stored value to detect a 0->1 change in its input data. As a result, after the 1->0 transition of digital value D occurring during the enable pulse of clock signal CKP, the outputs of unidirectional latch circuits 107 and 108 are again A=1 and B=1.

Summarizing the above, the monitoring circuit 102, during the timing event detection window following the allowable time limit, responds to an observed change in the digital value D by determining one of the stored instantaneous values or its stored complement values. can be said to be configured to toggle the The toggling is conditional such that during the timing event detection window, each of the stored instantaneous values or their stored complement values is responsive to observation of a change in the respective one direction of the digital value D. only toggled, i.e. one of the stored values is toggled if the digital value D changes in a first direction and the other of the stored values is toggled if the digital value changes in a second opposite direction is toggled to

Comparator 109 in the monitoring circuit represents the ability to compare the stored instantaneous value with its stored complement value during the timing event detection window. As explained above, the instantaneous value and one of its complement values can be toggled during the timing event detection window when there is a corresponding change in the digital value D during the timing event detection window. The output TEO is from comparator 109 which produces a timing event observation signal in response to a comparison indicating that the stored instantaneous value and its stored complement value are equal.

The operation of monitor circuit 102 is also essentially in another example where unidirectional latch circuits 107 and 108 respond only to 1->0 transitions in their input data, i.e. they are unidirectional in the falling direction. follow the same line to In this case, when the digital value D is 0 at the rising edge of the clock signal CKP, the first unidirectional latch circuit 107 again stores D=0 and the second unidirectional latch circuit 108 stores D=0. To store 1, initially A=0 and B=1. Now, when the digital value D changes from 0 to 1 while the clock signal CKP remains high, the upper one-way latch circuit 107 detects a 0->1 change in its input data and thus its stored value. do not toggle the value. Conversely, the lower one-way latch circuit 108 toggles its stored value to detect a 1->0 change in its input data. As a result, after a 0->1 transition of digital value D occurring during the enable pulse of clock signal CKP, the outputs of unidirectional latch circuits 107 and 108 are A=0 and B=0. It is briefly shown how to achieve the same result if the digital value D is 1 on the rising edge of the clock signal CKP and then changes to 0 during the timing event detection window.

FIG. 2 shows another example that shares many features with FIG. However, the use of the tilde (~) in the second unidirectional latch circuit 208 is omitted because unidirectional latch circuits 207 and 208 respond to changes in their input data in different directions. There is no inverter between data input 103 and either input of unidirectional latch circuits 207 and 208 . Accordingly, the monitoring circuit 202 of FIG. 2 is arranged to store the corresponding instantaneous value of the digital value D in parallel duplex form with two copies of the instantaneous value, one copy being the second copy, with respect to the allowed time limit. 1 in one unidirectional latch circuit 207 and the other copy in a second unidirectional latch circuit 208 .

Due to the inverse reaction capability of one-way latch circuits 207 and 208, monitor circuit 202 detects the stored moment in response to an observed change in digital value D during the timing event detection window following the allowable time limit. It is arranged to toggle one of the above copies of the value. The first copy stored in the first unidirectional latch circuit 207 is toggled only in response to observation of a change in the digital value D in one direction. The second copy stored in the second unidirectional latch circuit 208 is toggled only in response to observation of a change in the opposite direction of the digital value.

As an example, assume that digital value D is D=0 at the rising edge of clock signal CKP. At the beginning of the timing event detection window, this same value is stored in both unidirectional latch circuits 207 and 208 and appears at their outputs, ie A=B=0. If the first unidirectional latch circuit 207 is responsive to 0->1 changes in its input data, and one change occurs during the timing event detection window, the result is A=1 and B=0. becomes. If the digital value D is D=1 at the rising edge of the clock signal CKP, first A=B=1 and then a 1->0 transition of the digital value D occurs during the timing event detection window. , resulting in A=1 and B=0. Since the arrangement is symmetrical with respect to the inputs, it is easy to think of further examples in which the direction of response of unidirectional latch circuits 207 and 208 is switched.

In the embodiment of FIG. 2, monitoring circuit 202 is configured to compare copies of the stored instantaneous values during the timing event detection window using comparator 209 . It is arranged to output a timing event observation signal TEO in response to a comparison indicating that the copies of the stored instantaneous values are no longer equal.

The functions described above may actually be implemented in circuit elements other than the one-way latch circuits 107, 108, 207 and 208, as is common in digital circuits, and after teaching the required functions, For example, it is within the ability of a person skilled in the art to present several alternative implementations that differ in terms of signal polarity, the resulting inverters, the need to use appropriately selected logic gates and other circuit elements. can be within

Figures 1 and 2 show the possibility of using a trigger signal (ie the clock signal CKP) or some derivative thereof and part of the monitoring circuit that performs the comparison. This provides the advantage, for example, of ensuring tight synchronization of the comparison operation with known characteristics of the timing event detection signal. As an example, a copy of the digital value and possible temporary storage of the complement value (and possible toggle depending on the selected reaction direction) in circuit elements such as one-way latch circuits 107, 108, 207 and 208 are clocked. It may be advantageous to construct a separate and slightly shorter clock pulse for comparison, even though it is done over the entire duration of the active pulse of signal CKP. This allows the actual generation of the timing event observation signal to be concentrated on only a fraction of the active pulses of the clock signal. In other words, the actual timing event detection window can be delimited differently than the active pulses of the clock signal CKP.

Figures 1 and 2 also show the possibility of directing other kinds of control signals to the monitoring circuit, in particular the part of the monitoring circuit that performs the comparison and generates the timing event observation signal. Control signal input 110 may be used for such other types of control signals. Examples of such other types of control signals and their use are described in detail later in this text.

FIG. 3 shows an example of a monitoring circuit, also called a timing event detection circuit, in which both the first unidirectional latch circuit 107 and the second unidirectional latch circuit 108 indicate that the value of the corresponding input data is the value of the unidirectional latch circuit. They are configured to toggle their outputs only if they change in the same direction for both. The monitoring circuit of FIG. 3 includes an inverter 106 between data input 103 and one of first unidirectional latch circuit 107 and second unidirectional latch circuit 108 . Therefore, the monitoring circuit of FIG. 3 implements similar functionality as described above with reference to FIG. It is stored in differential form including its complement value ˜D in the second one-way latch circuit 108 .

The detailed structure chosen for the first unidirectional latch circuit 107 and the second unidirectional latch circuit 108 is such that the input of the unidirectional latch circuit becomes one input of an OR gate. The output of the OR gate becomes one input of the NAND gate, the other input of which is from the clock signal CKP. The output of the NAND gate constitutes the output of the unidirectional latch circuit. The other input of the OR gate is its inverted version. This type of unidirectional latch circuit only reacts to 0->1 transitions on its input. Note that the output of this type of unidirectional latch circuit is actually the reciprocal of the digital value it read in on the rising edge of the clock signal CKP, but this is not meaningful for the discussion here. rather, the comparison below is only sensitive to whether the two compared values are the same in any case.

FIG. 4 illustrates in state diagram form the operation of the monitoring circuit of FIG. Prior to the rising edge of clock pulse CKP, the circuit is in the leftmost state 401, where A=1, B=1 and TEO=0. A clock pulse (CKP) going active causes a transition to state 402 or state 403 depending on the value of digital signal D, a value of D=0 (marked ~D) causing a transition to state 402. A value of D=1 (marked as D) causes a transition to state 403 . As explained above, the particular structure chosen for the unidirectional latch circuits 107 and 108 of FIG. B=0 and TEO=0 and in state 403 A=0, B=1 and TEO=0.

A further transition to state 404 is now made when the digital value D changes while the clock signal CKP is still active. Since the upper middle state 402 was the result of the digital signal being D=0 at the beginning of the active clock pulse, a change of the digital value D to 1 while CKP=1 would cause the rightmost state from state 402 to A transition to 404 occurs. Similarly, the lower intermediate state 403 was the result of the digital signal being D=1 at the beginning of the active clock pulse, so when the digital value D changes to 0 while CKP=1, state 403 A transition to the rightmost state 404 occurs. In any case, in state 404, A=B=0, so that comparator 109 sets TEO=1.

The line labeled TMTEOH (Test Mode; Timing Event Observation; High) in FIG. 3 is an example of a control signal of the type briefly described above for its possible presence. be. It is also a representation that the circuit of FIG. 3 is DFT compliant. If the value of TMTEOH is low, the TEO signal is reset to TEO=0 on the falling edge of each clock pulse. However, if the value of TMTEOH is high, the TEO signal once set to TEO=1 will remain so until the control signal TMTEOH goes low at the same time as the clock signal CKP goes low. Both of these possibilities are illustrated in FIG. 4 from state 404 to initial state 401, which takes place under the condition of ~CKP&~TMTEOH (which means that CKP=0 and TMTEOH=0 occur simultaneously). is represented by the transition of

The dependence on the value of TMTEOH can be generalized so that the monitoring circuit resets the timing event observation signal at a predetermined instant during each pulse cycle of the trigger signal, thereby resetting the first It is configured to respond to a control signal value of one. The monitor circuit is also configured to respond to the second control signal value at the control signal input by maintaining the timing event observation signal during the period in which the second control signal value appears at the control signal input. be.

5 and 6 show examples of signal timing in one case, assuming that the monitoring circuit is of the type shown in FIG. 3 above.

In FIG. 5, the digital value D changed in a timely manner after the active clock pulses starting at instants 501 and 502, so that the unequal A and B values are maintained throughout the duration of each active clock pulse. . At instant 503 another clock pulse starts, but the change in digital signal D occurs slightly later at instant 504 . Since the change in digital signal D is 0->1, the first unidirectional latch circuit toggles, but the second unidirectional latch circuit does not, so that A=B=0 and then TEO signal goes high. Since there is no TMTEOH signal in FIG. 5, the TEO signal is reset to TEO=0 on each falling edge of clock signal CKP. A similar event cycle occurs at instants 505 and 505, except that the first unidirectional latch circuit does not toggle, but the second unidirectional latch circuit does toggle because the late attaining change in digital value D is 1->0. Continue to 506. The result, of course, is again A=B=0 and then the TEO signal goes high.

The event cycles at instants 601, 602, 603 and 604 of FIG. 6 are similar to those at instants 503, 504, 505 and 506 of FIG. It is the same. Prior to instant 605, the TMTEOH signal goes high. When the slow change of digital value D is reached at instant 606, the first result is A=0, B=0 and TEO=1 as at instant 602. FIG. However, it really does not matter whether the timing event also occurs at instant 608, as any further change in the TEO signal is prevented as long as the high value of TMTEOH is in effect. In the example of FIG. 6, the TMTEOH signal finally goes low before the falling edge of the clock signal CKP at instant 609, thereby resetting the TEO signal at instant 609. In the example of FIG.

Using a so-called standard cell implementation, one can build a transistor-level implementation of any microelectronic circuit, carefully following the presentation of its functionality as a combination of ordinary logic gates. A standard cell is a group of transistors and interconnect structures that provide a Boolean logic function (eg, AND, OR, XOR, XNOR, inverter) or storage function (flip-flop or latch). More complex cells such as various adders, multiplexed flip-flops, etc. can be used, but the simplest cells are direct representations of the basic NAND, NOR and XOR Boolean functions.

FIG. 7 shows an example of how functionality similar to that described above with reference to FIGS. 1 and 3-6 can be implemented in practice without the implementation of standard cells. For comparison, a widely used standard cell CMOS implementation of a logic gate as shown in FIG. may include Using such a standard cell implementation, the circuit of FIG. 3 would require the use of 40 transistors. The implementation of FIG. 7 includes only 27 transistors.

Two transistors M9 and M10 between the upper voltage rail VDD and the lower voltage rail VSS in FIG. 7 form an inverter 106 that produces the complement of the digital value D˜D. Therefore, this configuration requires only two transistors anyway, according to what is a CMOS implementation of the standard cell of the inverter.

Noting that transistor M3 is common to both unidirectional latch circuits 107 and 108, the transistor level implementation of unidirectional latch circuits 107 and 108 is the same in FIG. Transistor M3, with its source coupled to the lower voltage rail VSS, is called an enabler transistor because a high value of clock signal CKP at its gate enables active operation of unidirectional latch circuits 107 and 108. may be Similarly, transistor M5 in the first unidirectional latch circuit 107 and transistor M15 in the second unidirectional latch circuit 108 are such that a low value of the clock signal CKP at their gates causes their respective outputs (first unidirectional A in the second unidirectional latch circuit 107 and B in the second unidirectional latch circuit 108) is directly connected to the high voltage rail VDD and each unidirectional latch circuit is activated by conducting transistor M8 or M18, respectively. Because it is disabled, it may be called a disabler or reset transistor. For completeness, the illustrated CMOS implementation of the unidirectional latch circuit is described below with reference to the first unidirectional latch circuit 107 of FIG.

The source of PMOS M1 is coupled to the high voltage rail VDD. The drain of M1 is coupled to the source of PMOS M4, the drain of PMOS M4 is coupled to the drain of NMOS M2, and the source of NMOS M2 is coupled to the drain of enabler NMOS M3. The gates of M1 and M2 are coupled together to form the data input of the unidirectional latch circuit. The source of PMOS M5 is coupled to VDD. The drain of M5 is coupled to the drain of NMOS M6, and the source of NMOS M6 is coupled to the drain of enabler NMOS M3. The gates of M5 and M3 are coupled together to form the clock input of the one-way latch circuit. The gates of M4 and M6 are tied together. The source of PMOS M7 is coupled to VDD. The drain of M7 is coupled to the drain of NMOS M8 and the source of NMOS M8 is coupled to VSS. The gates of M7 and M8 are tied together. A point between the drains of M7 and M8 is coupled to the gates of M4 and M6. The output of the unidirectional latch circuit is formed by the combination of the gates of M7 and M8, the drains of M5 and M4, and the drains of M6 and M2.

For completeness, the illustrated CMOS implementation of comparator 109 is described below. The sources of PMOS M21, M22, M25 and M28 are coupled to VDD. The sources of NMOS M24 and M27 are coupled to VSS. The gates of M21 and M24 are coupled together to form the TMTEOH control input of comparator 109 . The drains of M21 and M22 are respectively coupled to the gates of M25 and M27 and coupled to the drain of NMOS M23. The gates of M22 and M23 are coupled together. The source of M23 is coupled to the drain of M24. The drain of M25 is coupled to the drain of NMOS M26. The drain of M28 is coupled to the source of PMOS M29. The drain of M29 is coupled to the drain of NMOS M30. The source of M26 and the source of M30 are coupled to the drain of M27. The gates of M28 and M26 are coupled together and constitute the first data input A of comparator 109. FIG. The gates of M29 and M30 are coupled together and constitute the second data input B of comparator 109. FIG. The TEO output of comparator 109 is formed by connecting the drains of M29 and M25, the drains of M30 and M26, and the gates of M22 and M23.

Storing the digital value D in differential form, including the instantaneous value and its complement, is implemented in voltage-mode CMOS logic in FIG. For comparison, FIG. 8 is from a previous patent application no. 1 shows a known type of supervisory circuit; Also, in the prior art implementation of FIG. 8, neither the stored instantaneous value nor its complement value can change ("toggle") during the active pulse of the clock signal CLK; , with the fundamental difference that both remain constant until the end of the active pulse of the clock signal CLK. The actual detection of the timing event during the active pulse of the clock signal CLK is done in an XNOR gate 801 which compares the stored complement value VC2 with the actual digital value D at the input of the monitoring circuit. If the two are equal, it means that the actual digital value D has changed since the beginning of the active clock pulse, indicating a timing event.

The voltage-mode logic used in FIG. 7 is inherently more reliable than the current-mode logic of FIG. 8 because the latter includes floating nodes and in FIG. 8 the clock signal CLK is low. , nodes 802 and 803 float independently of the digital value D. Node 802 floats when both CLK and D are high, and node 803 floats when CLK is high and D is low. Especially when trying to operate at very low voltages, floating nodes can lead to undesirable logic states due to leakage.

If a one-way latch circuit is used that stores the instantaneous value of D and its complement, the implementation of FIG. 7 requires fewer transistors than if a standard latch circuit were used. For example, considering the first unidirectional latch circuit 107, it does not have a pull-up network connection from the output of the inverter formed by transistors M1, M2 and M3 to the output A, compared to the standard latch circuit. Also, the unidirectional feature of the latch circuit reduces the total number of transistors in the circuit tasked with asserting the TEO signal in the event of a detected timing event. For comparison, in total 11 transistors are required for a CMOS implementation of an XOR or XNOR gate (e.g., in Texas Instruments' widely used logic circuits CD4070B and CD4077B), compared to a CMOS implementation of a 2-input AND gate. 8 requires 12 transistors (for example, in the Texas Instruments circuit CD4081B) and 2 transistors for the inverter, the implementation of the circuit of FIG. 8 requires as many as 49 transistors. do. This is more than the standard cell implementation of the function of FIG. 3, which is calculated to be 40 transistors before this text. Of course, the 27-transistor implementation of FIG. 7 is more efficient in terms of transistor count.

FIG. 9 illustrates a method embodiment corresponding to the description given above with reference to FIGS. 1 and 3-7. As a starting point for the method, FIG. 9 shows opening a detection window at step 901 . The detection window is associated with the task of monitoring timing events and then temporarily storing digital values in register circuits in synchronization with the trigger signal. Temporary storage of digital values should be done before opening the detection window in step 901 . A change in the digital value after the detection window is opened, ie while the detection window is open, represents a timing event. Strictly speaking, a timing event is a digital value change that is slower than the permissible time limit defined by the trigger signal.

As indicated by steps 902 and 903, the method determines the corresponding instantaneous value of the digital value, including the instantaneous value (step 902) and its complement value (step 903), with respect to the allowable time limit defined by the trigger signal. Including storing in differential form. The checks at steps 904 and 905 involve monitoring changes in a given direction. Only if one is detected, the corresponding stored value is correspondingly toggled in either step 906 or step 907 . This portion of the method is such that, during a timing event detection window following an allowable time limit, each of the stored instantaneous values or their stored complement values is responsive to observation of changes in the respective one direction of the digital value. can be characterized by toggling either the stored instantaneous value or its stored complement value, such that only the toggle is toggled.

Still during the timing event detection window, the stored instantaneous value is compared to the stored complement value, as represented by step 908 . If no timing event has occurred so far during this detection window, but the detection window is still open, a transition occurs via step 910 to monitoring steps 904 and 905 . A positive result at step 908 means that only one of the stored values is toggled and the values are equal. As represented by step 909, the method includes outputting a timing event observation signal in response to the comparison of step 908 indicating that the stored instantaneous value and its stored complement value are equal.

The method of FIG. 9 can be implemented any time after enabling the TEO signal in step 909 or when the detection window closes in step 911 because the end of the detection window was found as a positive conclusion of step 910 . finish. As a possible addition, as shown in FIG. 9, step 912 checks whether a control signal (herein referred to as the TMTEOH signal) is active. If the control signal is not active, the TEO signal is reset at step 913 before returning to step 901 at the start of the next detection window. If the control signal is active, return to step 901 without resetting the TEO signal.

FIG. 10 illustrates a method embodiment corresponding to the description given above with reference to FIG. The method of FIG. 10 is similar in many respects to the method of FIG. 9, but there are differences regarding the storage and comparison stages. Storing steps 1002 and 1003 comprise storing two copies of the corresponding instantaneous value of the digital value with respect to the permissible time limit defined by the trigger signal. Monitoring steps 1004 and 1005 are complementary in the sense that one monitors changes in one direction and the other monitors changes in the opposite direction of the other. These monitoring steps and their associated toggling steps 906 and 907 are designed so that each copy is toggled only in response to observation of a change in the digital value in each one direction during the timed event detection window following the allowable time limit. can be characterized by toggling either of the two copies. Steps 1008 and 909 compare the two copies during the timing event detection window and generate a timing event observation signal in response to said comparison indicating that the stored instantaneous value and its stored complement value are different. and outputting.

It is obvious to a person skilled in the art that as technology advances, the basic idea of the invention can be implemented in various ways. A typical feature of logic circuits is the ability to replace logic functions with structurally different but operationally equivalent functions, taking into account the possible inversions and logic transformations required. The invention and its embodiments are thus not limited to the examples described above, but instead may vary within the scope of the claims.

Claims (11)

A timing event observation signal (TEO) as a response to a change in the digital value (D) at the input of the associated register circuit (101) that occurs later than the allowable time limit defined by the trigger signal (CKP). a timing event detection circuit (102) for generating
- a data input (103) adapted to receive said digital value (D);
- a clock signal input (104) adapted to receive said trigger signal (CKP);
- a timing event detection circuit (102), comprising a timing event observation output (105) configured to output said timing event observation signal (TEO),
- said timing event detection circuit (102) stores the corresponding instantaneous value of said digital value (D) with respect to said allowed time limit in a differential form comprising said instantaneous value (A) and its complement (B); configured as
- said timing event detection circuit (102) is configured such that, during a timing event detection window following said allowed time limit, each of said stored instantaneous value (A) or its stored complement value (B) is said digital value; said instantaneous value (A) stored in response to an observed change in said digital value (D), or a stored configured to toggle one of its complement values (B) obtained by
- said timing event detection circuit (102) compares said stored instantaneous value (A) with its stored complement value (B) during said timing event detection window, and compares said stored instantaneous value (A ) and its stored complement value (B) are equal to each other;
A timing event detection circuit (102), characterized in that: A timing event observation signal (TEO) as a response to a change in the digital value (D) at the input of the associated register circuit (101) that occurs later than the allowable time limit defined by the trigger signal (CKP). a timing event detection circuit (202) that generates
- a data input (103) adapted to receive said digital value (D);
- a clock signal input (104) adapted to receive said trigger signal (CKP);
- a timing event detection circuit (102), comprising a timing event observation output (105) configured to output said timing event observation signal (TEO),
- said timing event detection circuit (202) stores the corresponding instantaneous value of said digital value (D) with respect to said allowed time limit in a parallel duplex format comprising two copies (A, B) of said instantaneous value; is configured to
- said timing event detection circuit (202), during a timing event detection window following said allowed time limit, the first copy (A) toggles only in response to observation of a change in one direction of the digital value (D); and stored in response to an observed change in said digital value (D) such that the second copy (B) is only toggled in response to observation of a change in said digital value (D) in the opposite direction. configured to toggle one of the copies (A, B) of said instantaneous value obtained;
- said timing event detection circuit (202) compares said stored copy of said instantaneous value (A, B) during said timing event detection window, and said stored copy of said instantaneous value (A, B) is configured to output the timing event observation signal (TEO) in response to the comparison indicating inequality;
A timing event detection circuit (202), characterized in that: including a first unidirectional latch circuit (107, 207) and a second unidirectional latch circuit (108, 208), said first unidirectional latch circuit (107, 207) and said second unidirectional latch circuit (107, 207) (108, 208) each have a respective latch data input coupled to said data input (103), a respective output and a respective latch clock coupled to said clock signal input (104). and a one-way latch circuit,
- storing its input data at the beginning of an enable pulse of said trigger signal (CKP);
- toggles its output only if the value of its input data (D, ~D) changes in a predetermined direction during said enable pulse of said trigger signal (CKP);
3. A timing event detection circuit (102, 202) according to any one of claims 1 or 2, being a circuit element configured to: - both said first unidirectional latch circuit (107) and said second unidirectional latch circuit (108) are such that the value of said corresponding input data (D, ~D) is in both said unidirectional latch circuits; configured to toggle their outputs only when they change in the same direction as
- said timing event detection circuit (102) is located between said data input (103) and one of said first unidirectional latch circuit (107) and said second unidirectional latch circuit (108); , the corresponding instantaneous value of said digital value in said differential form including said instantaneous value (A) in one unidirectional latch circuit (107) and said complement value (B) in the other unidirectional latch circuit (108) an inverter (106) for storing;
The timing event detection circuit (102) of claim 3 when dependent on claim 1. Storing corresponding instantaneous values of said digital values (D) in differential form comprising said instantaneous values (A) and their complements (B) is implemented in voltage-mode CMOS logic, according to claims 1-4. A timing event detection circuit (102, 202) according to any one of the preceding claims. - each of said first one-way latch circuit (107) and said second one-way latch circuit (108) comprises, respectively, a first transistor (M1, M11), a second transistor (M2, M12), 4th transistors (M4, M14), 5th transistors (M5, M15), 6th transistors (M6, M16), 7th transistors (M7, M17) and 8th transistors (M8, M18) wherein the first transistors (M1, M11), the fourth transistors (M4, M14), the fifth transistors (M5, M15) and the seventh transistors (M7, M17) are PMOS transistors. wherein the second transistors (M2, M12), the sixth transistors (M6, M16) and the eighth transistors (M8, M18) are NMOS transistors;
- said timing event detection circuit comprises an upper voltage rail (VDD), a lower voltage rail (VSS) and a source coupled to said lower voltage rail (VSS) and a gate coupled to said clock signal input; an enabled NMOS type enabler transistor (M3);
- in each of said first one-way latch circuit (107) and said second one-way latch circuit (108),
- the sources of said first transistors (M1, M11) are coupled to said upper voltage rail (VDD);
- the drains of said first transistors (M1, M11) are coupled to the sources of said fourth transistors (M4, M14),
- the drain of said fourth transistor (M4, M14) is coupled to the drain of said second transistor (M2, M12);
- the sources of said second transistors (M2, M12) are coupled to the drains of said enabler transistors (M3);
- the gates of the first transistors (M1, M11) and the gates of the second transistors (M2, M12) are coupled together and form latch data inputs of the respective one-way latch circuits;
- the sources of said fifth transistors (M5, M15) are coupled to said upper voltage rail (VDD);
- the drain of said fifth transistor (M5, M15) is coupled to the drain of said sixth transistor (M6, M16),
- the source of said sixth transistor (M6, M16) is coupled to the drain of said enabler transistor (M3);
- the gates of the fifth transistors (M5, M15) and the gates of the third transistors (M3, M13) are coupled together and form latch clock inputs of the respective one-way latch circuits;
- the gate of the fourth transistor (M4, M14) and the gate of the sixth transistor (M6, M16) are coupled together;
- the sources of said seventh transistors (M7, M17) are coupled to said upper voltage rail (VDD);
- the drain of said seventh transistor (M7, M17) is coupled to the drain of said eighth transistor (M8, M18),
- the sources of said eighth transistors (M8, M18) are coupled to said lower voltage rail (VSS);
- the gate of the seventh transistor (M7, M17) and the gate of the eighth transistor (M8, M18) are coupled together;
- the point between the drain of said seventh transistor (M7, M17) and the drain of said eighth transistor (M8, M18) is the gate of said fourth transistor (M4, M14) and said sixth transistor (M4, M14); coupled to the gates of transistors (M6, M16);
- the output of each said one-way latch circuit is connected to the gate of said seventh transistor (M7, M17) and the gate of said eighth transistor (M8, M18), the gate of said fifth transistor (M5, M15); 4. Constructed by the coupling of the drain and the drain of said fourth transistor (M4, M14) and the drain of said sixth transistor (M6, M16) and the drain of said second transistor (M2, M12). 6. The timing event detection circuit according to 5. including a control signal input (110);
- in response to a first control signal value at said control signal input (110) by resetting said timing event observation signal (TEO) at a predetermined moment during each pulse cycle of said trigger signal (CKP);
- said second control signal at said control signal input (110) by maintaining said timing event observation signal (TEO) during the period when a second control signal value appears at said control signal input (110); respond to the value,
A timing event detection circuit according to any one of claims 1 to 6, configured to: configured to reset said values (A, B) stored at the end of a detection window to a fixed default value, said end of detection window being defined with respect to said trigger signal (CKP), after said permissible time limit. A timing event detection circuit according to any one of claims 1 to 7, performed. - a processing path comprising a logic unit and a register circuit (101), said register circuit (101) being adapted to temporarily store the output value (D) of said logic unit in synchronization with a trigger signal (CKP); A microelectronic circuit comprising a processing path, comprising:
The microelectronic circuit comprises at least one timing event detection circuit (102, 202) according to any one of claims 1 to 8, said timing event detection circuit (102, 202) comprising said register circuit. (101) and a timing event observation signal (TEO) made later than the permissible time limit defined by said trigger signal (CKP) to the input of said associated register circuit (101). configured to generate as a response to a change in the digital value (D) at the edge,
A microelectronic circuit characterized by: A method of operating a microelectronic circuit comprising:
- temporarily storing the digital value (D) in the register circuit (101) in synchronization with the trigger signal (CKP);
- with respect to the permissible time limit defined by said trigger signal (CKP), storing the corresponding instantaneous value of said digital value (D) in differential form comprising said instantaneous value (A) and its complement (B); 902, 903) and
- during a timing event detection window following said allowed time limit, each of said stored instantaneous value (A) or its stored complement value (B) changes in one direction respectively of said digital value (D). toggling (906, 907) either the stored instantaneous value (A) or its stored complement (B) such that it is toggled only in response to the observation (904, 905) of ,
- comparing (908) the stored instantaneous value (A) with its stored complement value (B) during the timing event detection window;
- outputting (909) a timing event observation signal (TEO) in response to said comparison indicating that said stored instantaneous value (A) and its stored complement value (B) are equal;
A method, including A method of operating a microelectronic circuit comprising:
- temporarily storing the digital value (D) in the register circuit (101) in synchronization with the trigger signal (CKP);
- storing (1002, 1003) the corresponding instantaneous values of said digital value in two copies (A, B) with respect to the permissible time limit defined by said trigger signal (CKP);
- during a timing event detection window following said allowed time limit, said two copies ( A, B) toggling (906, 907);
- comparing (1008) the two copies (A, B) during the timing event detection window;
- outputting (909) a timing event observation signal (TEO) in response to said comparison indicating that said stored instantaneous value (A) and its stored complement value (B) are different;
A method, including

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