JPH03211743A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03211743A JPH03211743A JP2006862A JP686290A JPH03211743A JP H03211743 A JPH03211743 A JP H03211743A JP 2006862 A JP2006862 A JP 2006862A JP 686290 A JP686290 A JP 686290A JP H03211743 A JPH03211743 A JP H03211743A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor chip
- leads
- semiconductor device
- electrode extraction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000000605 extraction Methods 0.000 claims description 22
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 239000003566 sealing material Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 17
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 239000004020 conductor Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- MBGCACIOPCILDG-UHFFFAOYSA-N [Ni].[Ge].[Au] Chemical compound [Ni].[Ge].[Au] MBGCACIOPCILDG-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910002058 ternary alloy Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002500 effect on skin Effects 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- WABPQHHGFIMREM-OIOBTWANSA-N lead-204 Chemical compound [204Pb] WABPQHHGFIMREM-OIOBTWANSA-N 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 206010041235 Snoring Diseases 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置の構造、例えば半導体チップとリ
ードの一部とが封止される半導体装置の構造に関し、特
にマイクロ波集積回路に適用して有効な半導体装置の構
造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a structure of a semiconductor device, for example, a structure of a semiconductor device in which a semiconductor chip and a part of a lead are sealed, and is particularly applicable to a microwave integrated circuit. The present invention relates to a structure of a semiconductor device that is effective as a semiconductor device.
［従来の技術］
従来用いられてきた半導体装置２は、第３図に示すよう
に、半導体チップ２ｏがカソードリード２１及びアノー
ドリード２２と電気的に接続され、半導体チップ２０の
周辺部が樹脂２５により封止された構造となっている。[Prior Art] As shown in FIG. 3, in a conventionally used semiconductor device 2, a semiconductor chip 2o is electrically connected to a cathode lead 21 and an anode lead 22, and a peripheral portion of the semiconductor chip 20 is covered with a resin 25. It has a sealed structure.
この半導体チップ２゜について詳述すれば、半導体チッ
プ２ｏには例えば、第４図に示すように、ガリウム砒素
ショットキーバリアダイオードが形成されている。この
ガリウム砒素ショットキーバリアダイオードにおいては
、ｎ領域２０１及びｎ０領域２０２が形成されたガリウ
ム砒素半導体のｎ領域２０１側の面上に酸化シリコン膜
２０５が形成され、その酸化シリコン膜２０５に開けら
れた窓穴にｎ領域２０１に接するように電極取出部２０
３が形成されてぃる。この電極取出部２０３はチタン、
白金、金の３層より構成され、このうちチタンとｎ領域
２゜ｌとの接合面において電位障壁、即ちショットキー
障壁が形成されている。一方、ガリウム砒素半導体の下
面にはｎ１領域２０２に接するように電極取出部２０４
が設けられている。この電極取出部２０４は金−ゲルマ
ニウム−ニッケルの３元合金、パラジウム、金の３層よ
り構成されている。More specifically, the semiconductor chip 2o has a gallium arsenide Schottky barrier diode formed thereon, as shown in FIG. 4, for example. In this gallium arsenide Schottky barrier diode, a silicon oxide film 205 is formed on the surface of the gallium arsenide semiconductor on the n region 201 side in which an n region 201 and an n0 region 202 are formed, and an opening is formed in the silicon oxide film 205. Electrode extraction portion 20 is placed in the window hole so as to be in contact with n region 201.
3 is formed. This electrode extraction part 203 is made of titanium,
It is composed of three layers of platinum and gold, of which a potential barrier, ie, a Schottky barrier, is formed at the junction between titanium and the n-region 2°l. On the other hand, an electrode extraction portion 204 is provided on the lower surface of the gallium arsenide semiconductor so as to be in contact with the n1 region 202.
is provided. This electrode extraction portion 204 is composed of three layers of a ternary alloy of gold-germanium-nickel, palladium, and gold.
そして、この電極取出部２０４の金−ゲルマニウム−ニ
ッケルの３元合金とｎ＋領域２０２とはオーミック接合
をなしている。The gold-germanium-nickel ternary alloy of this electrode extraction portion 204 and the n+ region 202 form an ohmic contact.
上記ガリウム砒素ショットキーバリアダイオードの電極
取出部２０４が銀ペースト（又は金錫ロウ材）２４を介
してカソードリード２１に載設され、一方電極取出部２
０３が金属線２３例えば金線を介してアノードリード２
２に接続されている。The electrode lead 204 of the gallium arsenide Schottky barrier diode is mounted on the cathode lead 21 via a silver paste (or gold-tin brazing material) 24, and the electrode lead 204 of the gallium arsenide Schottky barrier diode is
03 is a metal wire 23, for example, an anode lead 2 via a gold wire.
Connected to 2.
上記構造の半導体装置２は例えば第３図に示すように、
マイクロストリップ線路３に半田４を介して設置されて
使用される。この場合、マイクロストリップ線路３の表
面配線導体３１より半田４を経てアノードリード２２に
達した高周波の信号電流は表皮効果によりマイクロスト
リップ線路３の裏面接地導体３２と向かい合う面、即ち
アノードリード２２の下面に沿って流れる。そして、金
線２３がボンディングされている箇所（アノードリード
２２の上面）の路下に該当する所から金線２３がボンデ
ィングされている箇所に向かって、アノードリード２２
の表面に沿って縦方向に信号電流は流れる。さらに、信
号電流は金線２３及び半導体チップ２０及び銀ペースト
（又は金錫ロウ材）２４を経てタブ部２１ａの下面に向
かってタブ部２１ａの表面に沿って縦方向に流れる。タ
ブ部２１ａの下面に達した信号電流はカソードリード２
１の下面に沿って流れて半田４を経てマイクロストリッ
プ線路３の表面配線導体３１へ達する。The semiconductor device 2 having the above structure has, for example, as shown in FIG.
It is used by being installed on the microstrip line 3 via solder 4. In this case, the high frequency signal current that reaches the anode lead 22 from the surface wiring conductor 31 of the microstrip line 3 via the solder 4 is transferred to the surface facing the back ground conductor 32 of the microstrip line 3, that is, the lower surface of the anode lead 22 due to the skin effect. flows along. Then, the anode lead 22 is moved from a location below the location where the gold wire 23 is bonded (the upper surface of the anode lead 22) toward a location where the gold wire 23 is bonded.
The signal current flows vertically along the surface of the Furthermore, the signal current flows vertically along the surface of the tab portion 21a toward the lower surface of the tab portion 21a via the gold wire 23, the semiconductor chip 20, and the silver paste (or gold-tin brazing material) 24. The signal current that has reached the bottom surface of the tab portion 21a is connected to the cathode lead 2.
1 and reaches the surface wiring conductor 31 of the microstrip line 3 via the solder 4.
［発明が解決しようとする課題］
このため、従来の半導体装置２の構造では信号電流の流
れる経路が長く寄生インダクタンスが大きい、という問
題がある。具体的には、アノードリード２２の下面から
アノードリード２２の上面（金線２３がボンディングさ
れている箇所）への経路の長さと、金線２３の経路にお
いて半導体チップ２０の厚さに相当する長さと、半導体
チップ２０中を流れる経路の長さ即ち半導体チップ２０
の厚さと、カソードリード２１の上面からカソードリー
ド２１の下面への経路の長さを足した分だけ、最短経路
に比べて信号電流の流れる経路が長くなる。そのため、
寄生インダクタンスが大きい、という問題がある。[Problems to be Solved by the Invention] Therefore, the structure of the conventional semiconductor device 2 has a problem in that the path through which the signal current flows is long and the parasitic inductance is large. Specifically, the length of the path from the bottom surface of the anode lead 22 to the top surface of the anode lead 22 (where the gold wire 23 is bonded) and the length of the path of the gold wire 23 corresponding to the thickness of the semiconductor chip 20 are determined. and the length of the path flowing through the semiconductor chip 20, that is, the length of the path flowing through the semiconductor chip 20.
, and the length of the path from the top surface of the cathode lead 21 to the bottom surface of the cathode lead 21, making the path through which the signal current flows longer than the shortest path. Therefore,
The problem is that the parasitic inductance is large.
また、カソードリード２１の基端部分がタブ部２１ａを
兼ねているため、カソードリード２１とアノードリード
２２とが接近して配されることとなり、カソードリード
２１とアノードリード２２との間に発生する寄生容量が
大きい、という問題がある。In addition, since the base end portion of the cathode lead 21 also serves as the tab portion 21a, the cathode lead 21 and the anode lead 22 are arranged close to each other, so that problems occur between the cathode lead 21 and the anode lead 22. The problem is that the parasitic capacitance is large.
このように寄生インダクタンスと寄生容量とが大きいと
、半導体装置のインピーダンスと適合するように外部回
路のインピーダンスを調整する際に、調整困難となり、
ひいては調整不可能となる場合も生ずる。また、マイク
ロ波集積回路の使用周波数帯域が狭められることにもな
る。従って、寄生インダクタンスと寄生容量を小さくし
なければならない。If the parasitic inductance and parasitic capacitance are large in this way, it becomes difficult to adjust the impedance of the external circuit to match the impedance of the semiconductor device.
As a result, there may be cases where adjustment becomes impossible. Furthermore, the frequency band used by the microwave integrated circuit will be narrowed. Therefore, parasitic inductance and parasitic capacitance must be reduced.
また、第５図（第３図のＶ−■における断面図）に示す
ように、信号電流が上述した経路で流れる際に、その信
号電流の経路とマイクロストリップ線路３の裏面接地導
体３２との間に生じる電気力線は、裏面接地導体３２と
向かい合う側において高密度となっている。上述したよ
うに、半導体チップ２０がカソードリード２１上に載設
され、その上に金線２３がボンディングされているため
、この高密度部を通過する電気力線のうち、半導体チッ
プ２０及び金線２３を流れる信号電流により生じる電気
力線の樹脂２５中における経路が長くなる。このため、
樹脂２５による誘電損失が大きくなる、という問題があ
る。Further, as shown in FIG. 5 (cross-sectional view at V-■ in FIG. 3), when the signal current flows through the above-mentioned path, the path of the signal current and the back ground conductor 32 of the microstrip line 3 are connected. The electric lines of force generated therebetween have a high density on the side facing the back ground conductor 32. As described above, since the semiconductor chip 20 is mounted on the cathode lead 21 and the gold wire 23 is bonded thereon, among the lines of electric force passing through this high-density area, the semiconductor chip 20 and the gold wire are The path of the electric lines of force generated by the signal current flowing through the resin 25 becomes longer. For this reason,
There is a problem in that the dielectric loss due to the resin 25 increases.
変換損失の小さい、換言すれば利得の大きい半導体装置
を得るためには、樹脂による誘電損失を小さく抑える必
要があり、そのためには、樹脂２５中における電気力線
の経路を短くしなければならない。In order to obtain a semiconductor device with low conversion loss, in other words, with high gain, it is necessary to suppress the dielectric loss due to the resin, and for this purpose, the path of the electric lines of force in the resin 25 must be shortened.
本発明は係る要望に基づいてなされたもので、寄生イン
ダクタンス及び寄生容量が小さく、かつ変換損失の小さ
いマイクロ波集積回路用の半導体装置を提供することに
ある。The present invention has been made based on such a need, and it is an object of the present invention to provide a semiconductor device for a microwave integrated circuit with small parasitic inductance and capacitance, and low conversion loss.
この発明の前記ならびにそのほかの目的と新規な特徴に
ついては、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［課題を解決するための手段］
本願において開示される発明のうち代表的なものの概要
を説明すれば、下記のとおりである。[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.
請求項１記載の発明は、マイクロ波集積回路に用いられ
る半導体チップと複数のリードとが電気的に接続され、
該半導体チップと該リードの一部とが封止される半導体
装置において、前記半導体チップには一主面のみに電極
取出部が設けられ、前記゛ト導体チップにおける該電極
取出部側の面と前記リードの下面とが面一となるように
半導体チップが配され、前記電極取出部と前記リードの
下面とが金属線によって電気的に接続され、しかもタブ
レス構造となっているものである。The invention according to claim 1 is characterized in that a semiconductor chip used in a microwave integrated circuit and a plurality of leads are electrically connected,
In a semiconductor device in which the semiconductor chip and a portion of the lead are sealed, the semiconductor chip is provided with an electrode extraction portion only on one main surface, and the electrode extraction portion side of the conductor chip and the electrode extraction portion are provided on only one main surface of the semiconductor chip. A semiconductor chip is arranged so that the lower surface of the lead is flush with the lower surface of the lead, and the electrode lead-out portion and the lower surface of the lead are electrically connected by a metal wire, and has a tableless structure.
請求項２記載の発明は、前記半導体チップとしてガリウ
ム砒素ショットキーバリアダイオードが形成された半導
体チップを請求項１記載の発明のように封止するように
したものである。According to a second aspect of the invention, a semiconductor chip in which a gallium arsenide Schottky barrier diode is formed as the semiconductor chip is sealed as in the first aspect of the invention.
請求項３記載の発明は、請求項１又は２記載の発明にお
いて封止材料として樹脂を用いるものである。The invention according to claim 3 uses a resin as the sealing material in the invention according to claim 1 or 2.
［作用］
請求項１乃至３記載の発明によれば、−主面のみに電極
取出部が設けられた半導体チップを該電極取出部側の面
とリードの下面とが而−となるように配し、前記電極取
出部と前記リードの下面とを金属線によって電気的に接
続することにより、高周波の信号電流は前記リードの下
面に沿って横方向に流れ不要な縦方向に流れる経路がな
いため、最短経路で流れる。従って、寄生インダクタン
スが小さくなる。[Function] According to the invention described in claims 1 to 3, - a semiconductor chip having an electrode extraction portion only on its main surface is arranged such that the surface on the electrode extraction portion side is the same as the lower surface of the lead. However, by electrically connecting the electrode extraction portion and the lower surface of the lead with a metal wire, the high-frequency signal current flows horizontally along the lower surface of the lead, and there is no unnecessary vertical path. , flows along the shortest path. Therefore, parasitic inductance is reduced.
また、タブレス構造によりタブ部を兼ねているカソード
リードの基端部分が不必要となり、その分力ソードリー
ドとアノードリードとの間の距離を大きくできるため、
両リード間に発生する寄生容量が小さくなる。In addition, the tableless structure eliminates the need for the proximal end of the cathode lead, which also serves as a tab, and the distance between the sword lead and anode lead can be increased accordingly.
Parasitic capacitance generated between both leads is reduced.
さらに、高周波の信号電流はカソードリード、半導体チ
ップ及びアノードリードの下面に沿って横方向に流れる
ため、高密度部を通過する電気力線のうち、樹脂中にお
ける経路が長くなるものは生じない。このため、樹脂に
よる誘電損失を小さくすることができ、変換損失が小さ
くなる。Furthermore, since the high-frequency signal current flows laterally along the lower surfaces of the cathode lead, the semiconductor chip, and the anode lead, among the lines of electric force passing through the high-density portion, no lines of electric force have long paths in the resin. Therefore, dielectric loss caused by the resin can be reduced, and conversion loss can be reduced.
［実施例］
本発明の一実施例を第１図及び第２図に基づいて説明す
る。[Example] An example of the present invention will be described based on FIGS. 1 and 2.
第１図はマイクロ波集積回路において、本実施例の半導
体装置がマイクロストリップ線路に実装された状態を示
す概略図である。FIG. 1 is a schematic diagram showing a semiconductor device of this embodiment mounted on a microstrip line in a microwave integrated circuit.
符号ｌは半導体装置であり、この半導体装ｆｆｌは、半
導体チップＩＯがカソードリード１１及びアノードリー
ド１２と電気的に接続され、半導体チップ１０の周辺部
が樹脂１５により封止された構造となっている。ここで
、半導体チップ１０について第２図を用いて詳述すれば
、本実施例の半導体チップｌＯには例えばガリウム砒素
ショットキーバリアダイオードが形成されている。この
ガリウム砒素ショットキーバリアダイオードにおいては
、半絶縁性のガリウム砒素半導体基板１０５の一主面側
の一部にｎ１領域１０２が埋設されている。そのｎ＋領
域１０２上の一部に０１領域ｌＯ２と接するようにｎ領
域１０１が形成されている。そして、ｎ領域１０１と接
するように電極取出部１０３が、また０４領域１０２と
接するように電極取出部１０４がそれぞれ形成されてい
る。Reference numeral l denotes a semiconductor device, and this semiconductor device ffl has a structure in which a semiconductor chip IO is electrically connected to a cathode lead 11 and an anode lead 12, and the peripheral part of the semiconductor chip 10 is sealed with a resin 15. There is. Here, the semiconductor chip 10 will be described in detail with reference to FIG. 2. The semiconductor chip 10 of this embodiment has, for example, a gallium arsenide Schottky barrier diode formed therein. In this gallium arsenide Schottky barrier diode, an n1 region 102 is buried in a portion of one main surface side of a semi-insulating gallium arsenide semiconductor substrate 105. An n region 101 is formed on a portion of the n+ region 102 so as to be in contact with the 01 region IO2. An electrode lead-out portion 103 is formed in contact with the n region 101, and an electrode lead-out portion 104 is formed in contact with the 04 region 102.
つまり、電極取出部１０３及び１０４は共にガリウム砒
素ショットキーバリアダイオードの一主面に設けられて
いる構成となっている。なお、電極取出部１０３はチタ
ン、白金、金の３層より構成され、ｎ領域１０１と接す
るチタンとｎ領域１０１との接合面において電位障壁、
即ちショットキー障壁が形成されている。一方、電極取
出部１０４は金−ゲルマニウム−ニッケルの３元合金、
パラジウム、金の３層より構成され、ｎ＋領域１０２と
接する金−ゲルマニウム−ニッケルの３元合金と０１領
域１０２との接合はオーミック接合をなしている。In other words, the electrode extraction parts 103 and 104 are both provided on one main surface of the gallium arsenide Schottky barrier diode. Note that the electrode extraction portion 103 is composed of three layers of titanium, platinum, and gold, and has a potential barrier and a
That is, a Schottky barrier is formed. On the other hand, the electrode extraction part 104 is made of a ternary alloy of gold-germanium-nickel.
It is composed of three layers of palladium and gold, and the junction between the 01 region 102 and the gold-germanium-nickel ternary alloy in contact with the n+ region 102 forms an ohmic junction.
本実施例では、上記半導体チップｌＯは向かい合うカソ
ードリード１１とアノードリード１２との間にタブレス
構造にて配される。また、このガリウム砒素ショットキ
ーバリアダイオードにおける電極取出部側のｉ？ｉｉと
Ｍ？ｊ記カツカソードリード１１アノードリード１２の
下面とがｉ／ｉｊ−となるように前記半導体チップ１０
が配される。このような構造は、例えば、前記電極取出
部側の而と前記カソードリード１１及びアノードリード
１２の下面とを而−にするために、半導体チップ１０の
厚さをカソードリード１１及びアノードリード１２の厚
さと同一になるようにするとともに、前記カソードリー
ド１１及びアノードリード１２の上面とに亘って、絶縁
性の支持材例えばポリイミドフィルム等を貼着し、半導
体チップ１０における電極取出部１０３．１０４の設け
られていない側の而をその支持材に貼着することによっ
て容易に得られる。In this embodiment, the semiconductor chip IO is arranged in a tableless structure between a cathode lead 11 and an anode lead 12 that face each other. Also, i? on the electrode extraction part side of this gallium arsenide Schottky barrier diode? ii and M? The semiconductor chip 10 is placed so that the bottom surface of the cathode lead 11 and the anode lead 12 are i/ij-.
will be arranged. In such a structure, for example, the thickness of the semiconductor chip 10 is reduced to the thickness of the cathode lead 11 and the anode lead 12 in order to make the bottom surface of the cathode lead 11 and the anode lead 12 the same as the bottom surface of the cathode lead 11 and the anode lead 12. At the same time, an insulating support material such as a polyimide film is pasted over the upper surfaces of the cathode lead 11 and the anode lead 12, and the electrode lead-out portions 103 and 104 of the semiconductor chip 10 are made to have the same thickness. This can be easily obtained by attaching the unprovided side to the supporting material.
また、本実施例ではガリウム砒素ショットキーバリアダ
イオードの電極取出部１０４がカソードリード１１の下
面に、電極取出部］、 ０３がアノードリード１２の下
面にそれぞれ金属線１３例えば金線を介して接続されて
いる。Further, in this embodiment, the electrode lead-out portion 104 of the gallium arsenide Schottky barrier diode is connected to the lower surface of the cathode lead 11, and the electrode lead-out portion 03 is connected to the lower surface of the anode lead 12 via a metal wire 13, for example, a gold wire. ing.
高周波で用いられるマイクロ波集積回路において、上記
構造の半導体装置ｌを流れる信号電流は以下の経路で流
れる。前記マイクロストリップ線路３の表面配線導体３
１より半田４を経て半導体装置ｌのアノードリード１２
に達し、表皮効果によりアノードリード１２の下面に沿
って流れる。In a microwave integrated circuit used at high frequencies, a signal current flows through the semiconductor device I having the above structure through the following path. Surface wiring conductor 3 of the microstrip line 3
1 to the anode lead 12 of the semiconductor device l via the solder 4
and flows along the lower surface of the anode lead 12 due to the skin effect.
そして、金線１３を経て半導体チップ１ｏに達した後、
半導体チップ１０の表層を流れてもう一方の金線Ｉ３を
経てカソードリード１１の下面に達する。ここでも表皮
効果によりカソードリードｌｌの下面に沿って流れ、半
田４を経てマイクロストリップ線路３の表面配線導体３
１へ達する。従って、信号電流は必要以上の迂回経路を
経ずに最短経路で流れる。After reaching the semiconductor chip 1o via the gold wire 13,
It flows through the surface layer of the semiconductor chip 10 and reaches the lower surface of the cathode lead 11 via the other gold wire I3. Here again, due to the skin effect, it flows along the lower surface of the cathode lead 11, passes through the solder 4, and then passes through the surface wiring conductor 3 of the microstrip line 3.
Reach 1. Therefore, the signal current flows through the shortest route without taking unnecessary detours.
本発明の構成による半導体装置を高周波に用いられるマ
イクロ波集積回路に適用すれば、半導体装置内における
信号電流の流れる経路が最短になるため半導体装置内の
寄生インダクタンスを最小にすることができ、また、カ
ソードリードとアノードリードとの間の距離を大きくで
きるため、両リード間に発生する寄生容量を低減するこ
とができる、という効果がある。これら寄生インダクタ
ンスと寄生容量とが低減されることにより、半導体装置
のインピーダンスと適合するように行う外部回路のイン
ピーダンスの調整が容易になり、また、マイクロ波集積
回路の使用周波数帯域も広くなる。If the semiconductor device having the structure of the present invention is applied to a microwave integrated circuit used for high frequencies, the path through which the signal current flows within the semiconductor device will be the shortest, so that the parasitic inductance within the semiconductor device can be minimized. Since the distance between the cathode lead and the anode lead can be increased, the parasitic capacitance generated between the two leads can be reduced. By reducing these parasitic inductances and parasitic capacitances, it becomes easier to adjust the impedance of an external circuit to match the impedance of the semiconductor device, and the frequency band used by the microwave integrated circuit also becomes wider.
また、信号電流はカソードリード、半導体チップ及びア
ノードリードの下面に沿って横方向に流れるので、高密
度部を通過する電気力線のうち、樹脂中における経路が
長くなるものが生じないため樹脂による誘電損失を小さ
くすることができ、変換損失が小さくなる、という効果
がある。In addition, since the signal current flows laterally along the bottom surfaces of the cathode lead, semiconductor chip, and anode lead, among the lines of electric force that pass through high-density areas, there are no lines of electric force that have long paths in the resin. This has the effect of reducing dielectric loss and conversion loss.
さらにまた、半導体チップは向かい合うカソードリード
とアノードリードとの間にタブレス構造にて配されるた
め、従来よりも樹脂の厚さを小さくすることができ、変
換損失をさらに小さく抑えることができる、即ち高利得
化が図れる、という効果がある。Furthermore, since the semiconductor chip is arranged in a tableless structure between the cathode lead and the anode lead facing each other, the thickness of the resin can be made smaller than before, making it possible to further suppress conversion loss. This has the effect of increasing the gain.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
なお、封止に用いる材料は樹脂に限らず、セラミック等
でも良い。Note that the material used for sealing is not limited to resin, and may be ceramic or the like.
また、半導体チップとしてダイオードが形成された半導
体チップに限らず、マイクロ波集積回路に用いられる半
導体チップにおいて電極取出部がその一主面のみに設け
られていれば何でも良い。Further, the semiconductor chip is not limited to a semiconductor chip on which a diode is formed, but any semiconductor chip used in a microwave integrated circuit may be used as long as the electrode extraction portion is provided only on one main surface thereof.
さらに、マイクロ波集積回路に用いられる半導体チップ
に限らず、電極取出部がその一主面のみに設けられてい
れば如何なる半導体チップにも適用することができる。Furthermore, the present invention is not limited to semiconductor chips used in microwave integrated circuits, but can be applied to any semiconductor chip as long as the electrode extraction portion is provided only on one principal surface.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるマイクロ波集積回路
に適用する半導体装置について説明したが、それに限定
されるものではない。Although the above explanation has mainly been about a semiconductor device applied to a microwave integrated circuit, which is the field of application to which the invention made by the present inventor is based, the present invention is not limited thereto.
［発明の効果コ
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.
請求項１乃至３記載の発明によれば、マイクロ波集積回
路に用いられる半導体チップと複数のリードとが電気的
に接続され、該゛ｒ導体チップと該リードの一部とが封
止される半導体装置において、前記半導体チップには一
十面のみに電極取出部が設けられ、前記半導体チップに
おける該電極取出部側の面と前記リードの下面とが面一
となるように半導体チップが配され、前記電極取出部と
前記リードの下面とが金属線によって電気的に接続され
、しかもタブレス構造となるように構成されているので
、半導体装置内の寄生インダクタンスと寄生容量とが低
減され、かつ、変換損失が低減される、という効果があ
る。According to the invention described in claims 1 to 3, a semiconductor chip used in a microwave integrated circuit and a plurality of leads are electrically connected, and the conductor chip and a part of the leads are sealed. In the semiconductor device, the semiconductor chip is provided with an electrode lead-out portion on only ten sides, and the semiconductor chip is arranged such that the surface of the semiconductor chip on the side of the electrode lead-out portion and the lower surface of the lead are flush with each other. , since the electrode extraction portion and the lower surface of the lead are electrically connected by a metal wire and configured to have a tableless structure, parasitic inductance and parasitic capacitance within the semiconductor device are reduced; This has the effect of reducing conversion loss.
第１図は本発明の半導体装置がマイクロストリップ線路
に実装された状態を示す概略図、第２図は本発明の半導
体装置に用いられる半導体チップの断面図、
第３図は従来の半導体装置がマイクロストリップ線路に
実装された状態を示す概略図、第４図は従来の半導体装
置に用いられる半導体チップの断面図、
第５図は第３図の■−■における断面図である。
１・・・・半導体装置、１０・・・・半導体チップ、ｌ
ｌ・・・・カソードリード（リード）、１２・・・・ア
ノードリード（リード）、１３・・・・金線（金属線）
、１５・・・・樹脂、１０３．１０４・・・・電極取出
部。
第
面
１（キ鼾憧１）
１′
１３（金虚）
！
第
図
第３
図
第
図FIG. 1 is a schematic diagram showing a semiconductor device of the present invention mounted on a microstrip line, FIG. 2 is a cross-sectional view of a semiconductor chip used in the semiconductor device of the present invention, and FIG. 3 is a diagram showing a conventional semiconductor device. FIG. 4 is a sectional view of a semiconductor chip used in a conventional semiconductor device, and FIG. 5 is a sectional view taken along line 1--2 in FIG. 3. 1... Semiconductor device, 10... Semiconductor chip, l
l...Cathode lead (lead), 12...Anode lead (lead), 13...Gold wire (metal wire)
, 15...Resin, 103.104... Electrode extraction part. 1st side (Ki snoring yearning 1) 1' 13 (Kinko)! Figure 3 Figure 3
Claims (1)
数のリードとが電気的に接続され、該半導体チップと該
リードの一部とが封止される半導体装置において、前記
半導体チップには一主面のみに電極取出部が設けられ、
前記半導体チップにおける該電極取出部側の面と前記リ
ードの下面とが面一となるように半導体チップが配され
、前記電極取出部と前記リードの下面とが金属線によっ
て電気的に接続され、しかもタブレス構造となっている
ことを特徴とする半導体装置。 ２、前記半導体チップにはガリウム砒素ショットキーバ
リアダイオードが形成されていることを特徴とする請求
項１記載の半導体装置。 ３、封止材料として樹脂を用いることを特徴とする請求
項１又は２記載の半導体装置。[Scope of Claims] 1. A semiconductor device in which a semiconductor chip used in a microwave integrated circuit and a plurality of leads are electrically connected, and the semiconductor chip and a portion of the leads are sealed, The chip has an electrode extraction part on only one main surface,
The semiconductor chip is arranged so that the surface of the semiconductor chip on the electrode extraction portion side and the lower surface of the lead are flush with each other, and the electrode extraction portion and the lower surface of the lead are electrically connected by a metal wire; Moreover, the semiconductor device is characterized by having a tableless structure. 2. The semiconductor device according to claim 1, wherein a gallium arsenide Schottky barrier diode is formed in the semiconductor chip. 3. The semiconductor device according to claim 1 or 2, wherein a resin is used as the sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006862A JP2789484B2 (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006862A JP2789484B2 (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03211743A true JPH03211743A (en) | 1991-09-17 |
| JP2789484B2 JP2789484B2 (en) | 1998-08-20 |
Family
ID=11650054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006862A Expired - Fee Related JP2789484B2 (en) | 1990-01-16 | 1990-01-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2789484B2 (en) |
-
1990
- 1990-01-16 JP JP2006862A patent/JP2789484B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2789484B2 (en) | 1998-08-20 |
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