JPH0321033A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent generation of side gate effect so as to get high performance and stable characteristics excellently in reproducibility by providing an InGaP high resistance layer between a semiconductor substrate and a channel layer and a carrier supply layer, and forming an element isolating region in the channel layer and the carrier supply layer. CONSTITUTION:This has an InGaP high resistance layer 6, which is doped with transition metal on the semiconductor substrate 2, a channel layer 8, a carrier supply layer 10, which is hetero-junctioned on the channel layer 8 and produces secondary carrier gas near the hetero junction interface, and an element isolating region 20, Which is formed in the channel layer 8 and the carrier supply layer 10 and isolates the element region. That is, the InGaP high resistance layer 6, wherein InGaP relatively small in parent-child affinity is doped with transition metal to become a deep acceptor, is formed between the semiconductor substrate 2 and the channel layer 8, so a path, along which currents flow between adjacent elements passing through the semiconductor substrate 2, is interrupted. Hereby, generation of the side gate effect being electrical interference phenomena between elements is prevented, and high performance of and stable characteristics can be gotten excellently in reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a compound semiconductor device that uses a two-dimensional carrier gas generated at a heterojunction interface as a carrier.

[Prior Art] As a typical compound semiconductor device that uses a two-dimensional carrier gas generated at a heterojunction interface as a carrier, HEM'T' (High
h Elecoton Hobility Trans
istor; high electron mobility transistor).

That is, a non-doped GaAs channel layer 8 and an N-type A. QGaAs electron supply layers 10 are stacked one after another in a heterojunction. And this N type AJG
On the aAs electron supply layer 10, n-type GaAs-'? A source electrode 14 and a drain electrode 16 are formed which are electrically connected through the YAP layer 12. Further, a Schottky-junction gate voltage tff118 is provided on the N-type AjGaAs electron supply layer 10 sandwiched between the source voltage [14 and the drain voltage &16].

And GaAs channel layer 8 and N type AJIGa
For example, oxygen is injected into a predetermined location of the As electron supply layer 10 to form an element isolation region 20. This device isolation region 20 isolates a transistor having a source electrode 14, a drain electrode 16, and a gate electrode 18 from an adjacent transistor having a side gate electrode 22 ohmically connected to the n-type GaAs cap layer 12. has been done.

In such a HEM T, a GaAs channel layer 8 and an N-type A. A two-dimensional electron gas is generated on the GaAs channel layer 8 side near the heterojunction interface with the QGaAs electron supply layer 10. By using this two-dimensional electron gas as a carrier, it is possible to obtain a mobility close to the electron mobility within the GaAs channel layer 8, thereby realizing high-speed transistor operation.

However, in such a HEMT, when a negative side gate voltage is applied to the side gate electrode 22 adjacent to a certain transistor, the voltage across that transistor changes as shown by the broken line in the graph of FIG. A so-called side gate effect occurs, which is an electrical interference phenomenon between elements that occurs. Moreover, this side gate effect is
This phenomenon becomes more noticeable as the distance between each electrode becomes narrower as MTs become more integrated, and thus becomes a major obstacle in constructing integrated circuits.

The cause of this side gate effect is, as shown by the dashed line with an arrow in FIG. Ga
As electron supply layer 10, GaAs channel layer 8 and GaA
It is considered that there is a path for electrons to flow through the s-buffer layer 4, further through the GaAs substrate 2, and reach the adjacent transistor.

Therefore, in order to prevent the side gate effect, it is thought that it is sufficient to block this current path, and as shown in Fig. 5,
Attempts have been made to insert an i-type AJGaAs high resistance layer 36 between the GaAs channel layer 8 and the GaAs substrate 2. And this i-type AjGaAs high resistance layer 36
can be grown in a lattice-matched manner with the GaAs substrate 2, and since it has a smaller electron affinity than GaAs, it can play the role of a barrier.

However, the present inventor has proposed MOCVD (HetaOr
Ganic Che■ical Vapor Depo
According to the experience of forming the i-type AJGaAs high-resistance layer 36 using the i-type A. GGaAs
The high-resistance layer 36 has problems in that the reproducibility of its resistance value is poor and the optimum conditions for growth vary greatly depending on the growth furnace, resulting in instability.

Also, when forming a high resistance layer by doping AJGaAs with oxygen instead of i-type AJIGaAs,
Reproducibility (A. The OGaAs high-resistance layer is not fully formed, and the problem arises that the oxygen introduced into the growth reactor remains in the growth reactor and adversely affects the crystallinity of the semiconductor layer grown afterwards. Ta.

Bow 6 [Problem to be solved by the invention] As described above, in a compound semiconductor device that uses a two-dimensional carrier gas as a carrier, which is present at the conventional hederojunction interface, it is difficult to integrate the device. A side gate effect occurs, which causes electrical interference between elements, and to prevent this, Aj is placed between the channel layer and the GaAs substrate.
Attempts have been made to provide a GaAs high resistance layer, but it has been difficult to form an AjGaAs high resistance layer having a stable resistance value with good reproducibility.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can achieve high integration by preventing the occurrence of side gate effects, and can realize higher performance and stable characteristics with good reproducibility.

[Means for solving the problem] The above problem consists of a semiconductor substrate and an I layer formed on the semiconductor substrate and doped with a transition metal to serve as a deep acceptor.
An nGaP high resistance layer, a channel layer formed on the nGaP high resistance layer, and a heterojunction formed on the channel layer to generate a two-dimensional carrier gas near the heterojunction interface of the channel layer. This is achieved by a semiconductor device comprising a carrier supply layer and an element isolation region formed in the channel layer and the carrier supply layer to isolate element regions.

[Function] That is, the present invention is directed to I n having a relatively small electron affinity.
GaP doped with a transition metal that becomes a deep acceptor
The nGaP high-resistance layer is formed between the semiconductor substrate and the channel layer, thereby blocking the current path that passes through the semiconductor substrate and flowing between adjacent devices. It is possible to prevent the gate effect from occurring.

This high resistance InGaP layer doped with a transition metal serving as a deep acceptor can provide a stable high resistance value with good reproducibility.

The reason for this is that while AjGaAs, which has the same low electron affinity, exhibits n-type or p-type conductivity under certain long conditions or non-doped conditions in a Kaicho reactor, the InGaP layer has a certain long It has a tendency to become n-type under non-doping conditions without being too dependent on conditions, and for this reason, by doping the n-type InGaP layer with a transition metal that serves as a deep acceptor, InGaP has a stable high resistance value.
It is believed that the GaP layer can be formed with good reproducibility.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

MOC is formed on the GaAs substrate 2 via a non-doped GaAs buffer layer 4 with a thickness of 500 mm.
In 1-x G a x P (x-0 .
5 2) A high resistance layer 6 is formed. And G a
This I has a smaller electron affinity than the A s buffer layer 4.
The nGaP high resistance layer 6 is doped with Fe (iron) as a transition metal serving as a deep acceptor in a doping amount of 5×10”cm−
'It's been doped up to a certain degree.

Further, on this InGaP high resistance layer 6, a layer with a thickness of 400 mm is formed.
A non-doped Ga As channel layer 8 and a 370-thick N-type A.S. l! ,-eGag
As (x=0.25) and an electron supply layer 1o are laminated in this order. The GaAs channel layer 8 and the N-type AJI GaAs electron supply layer 1o are in a heterojunction. A two-dimensional electron gas is generated on the GaAs channel layer 8 side near the heterojunction interface with the II GaAs electron supply layer 10.

In addition, this N type A. ．． On the QGaAs electron supply layer 1o,
Doping amount 1. 5 x 1018c m-' of Si
A, uG. e
A source electrode 14 and a drain electrode f216 each made of a 910/A u electrode are formed. Furthermore, an N-type AjGaA layer sandwiched between these source electrodes 14 and train electrode #116
On the s-electron supply layer 10, a gate electrode (Fil 18) consisting of an A1 electrode connected to a Schottky junction is provided.

Furthermore, the GaAs channel layer 8 and the N-type A. For example, oxygen is implanted into a predetermined location of the QGaAs electron supply layer 10 to form an element isolation region 20.
is formed. The element isolation region 20 isolates a transistor having a source electrode 14, a drain electrode 16, and a gate electrode 18 from adjacent transistors 1 to 1. And the n-type Ga of the adjacent transistor
The distance between the side gate electrode 22 ohmically connected to the source electrode 14 or the train electrode 16 on the As-'F layer 12 is approximately 3
μm apart.

Next, the Zydoge-1 effect of the semiconductor device shown in FIG. 1 will be explained using FIG. 2.

11 FIG. 2 is a graph obtained by applying a negative voltage to the adjacent Zyde gate voltage f222 and measuring the variation in the dark value voltage of the transistor. As is clear from the solid line shown in this graph, the threshold voltage of the transistor is 0.2 V until the side gate voltage applied to the side gate electrode 22 reaches -6V.
It remained constant around 5V and no fluctuations were observed.

This means that in the conventional example in which a high resistance layer such as the InGaP high resistance layer 6 is not provided between the GaAs substrate 2 and the GaAs channel layer 8, as shown by the broken line in FIG.
Compared to the fact that the dark value voltage of the transistor fluctuates greatly with a side gate voltage of about -1.5V, this example can be said to show that the occurrence of the side gate effect is prevented.

Next, the InGaP high resistance layer 6 used in this example was evaluated using an apparatus as shown in FIG.

On the n+ type GaAs substrate 24, using the MOCVD method,
12 undoped GaAs buffer layer 4 with the same thickness as shown in FIG. 1 and doping amount 5X1
2000 mm thick Fe doped I
The nGaP high resistance layer 6 is formed in order, and this InGaP
An n-type GaAs contact layer 26 is grown on the high resistance R6. In this way, Ga A on the n+ type GaAS substrate 24
An InGaP high resistance layer 6 is sandwiched between the s-buffer layer 4 and the n-type GaAs contact layer 26.

Then, on the back surface of the n+ type G a A s substrate 24 and the n type G
Ohmic electrodes 2 are placed on the aAs cap layers 1 and 2, respectively.
8.30 and connect it to the constant current source 32 and voltmeter 34. Then, a constant current (2) is caused to flow between the ohmic electrodes 28 and 30, and the voltage (2) is measured.

The resistance value of the InGaP high resistance layer 6 obtained from this current-voltage characteristic showed a very high value of 10l1Ω1c'm. And this resistance value is the same as that of conventional AJ)GaAs.
The resistance value is equivalent to that obtained by a high-resistance layer formed by doping oxygen.

As described above, according to this embodiment, Fe-doped I
An nGaP high resistance layer 6 is provided, and the current path passing through the GaAs substrate 2 and flowing between adjacent elements can be blocked by this InGaP high resistance layer 6 and the element isolation region 20. As a result, it is possible to prevent the occurrence of side gate effect, which is an electrical interference phenomenon between elements, and therefore it is possible to increase the degree of integration of transistors having a HEMT structure.

In addition, as a high resistance layer to prevent the side gate effect, Fe was used instead of the conventional AjGaAs high resistance layer.
By using the InGaP high resistance layer 6 doped with , a stable high resistance value can be obtained with good reproducibility.

Note that in the above embodiment, the InGaP high resistance layer 6
Fe as a transition metal that becomes a deep acceptor doped into
was used, but for example, Cr (chromium) and ■ (vanadium)
etc. may be used.

Moreover, instead of this InGaP high resistance layer 6, In
A high resistance layer using GaP may be used.

In this case, the InAJI GaP high resistance layer is also made of GaAs
It can be grown in a lattice-matched manner on a 1 3 1 4 substrate or a GaAs buffer layer.

Further, the element isolation region 20 may be formed by implanting oxygen, or may be formed by using a trench formed by etching, for example, without being limited thereto.

Furthermore, instead of the AfJGaAs electron supply layer 10, I
Even with the nGaP electron supply layer, and instead of the GaAs channel layer 8, an I no2G layer with a thickness of about 150 nm is used.
ao. Even if the sAs channel layer is used, the effect on the side gate effect is similar.

[Effects of the Invention] As described above, according to the present invention, an InGaP high resistance layer doped with a transition metal serving as a deep acceptor is provided between the semiconductor substrate and the channel layer and the carrier supply layer,
Furthermore, by forming element isolation regions in the channel layer and the carrier supply layer, the current path passing through the semiconductor substrate is blocked, thereby preventing the occurrence of the side gate effect, which is an electrical interference phenomenon between elements. I can do it. InGaP doped with a transition metal that becomes this deep acceptor
The high resistance layer can provide a stable high resistance value with good reproducibility.

As a result, the degree of integration of the semiconductor device can be increased, and higher performance and stable characteristics can be realized with good reproducibility.

[Brief explanation of the drawing]

1 is a sectional view showing a semiconductor device according to an embodiment of the present invention; FIG. 2 is a graph showing characteristics of the semiconductor device shown in FIG. 1; FIG. 3 is an illustration of the semiconductor device shown in FIG. 1. 4 and 5 are cross-sectional views showing conventional semiconductor devices, respectively. In the figure, 2...GaAs substrate, l6 4...GaAs buffer layer, 6...
...InGaP high resistance layer, 8...GaAs channel layer, 10...N type A. G GaAs electron supply layer, 1
2...n-type GaAs cap layer, 14...
... Source electrode, 16 ... Drain electrode, 16 ... Gate electrode, 20 ... Element isolation region, 22 ... Side gate electrode, 24 ... ...n+ type GaAs substrate, 26...
...N-type GaAs contact layer, 28.30...
...Ohmic electrode, 32... Constant current source, 34... Voltmeter, 36... i-type AJI GaAs high resistance layer. Narrow

Claims (1)

[Scope of Claims] A semiconductor substrate, an InGaP high resistance layer formed on this semiconductor substrate and doped with a transition metal serving as a deep acceptor, a channel layer formed on this InGaP high resistance layer, and this channel. a carrier supply layer formed in a heterojunction on the channel layer and generating a two-dimensional carrier gas near the heterojunction interface of the channel layer; formed on the channel layer and the carrier supply layer;
A semiconductor device characterized by having an element isolation region that isolates an element region.