JPH03208409A - Self-hold type semiconductor device and self-hold type semiconductor relay - Google Patents

Abstract

PURPOSE:To obtain a self-hold function without a peripheral circuit by providing a 1st electrode forming a floating gate provided on a 1st insulation film, a 2nd insulation film coating the 1st electrode and a 2nd electrode forming a control gate injecting electrons to the 1st electrode provided on the 2nd insulation film. CONSTITUTION:When a positive high voltage (e.g. +10-50V) is applied to a polycrystalline silicon film (2nd electrode) 6 being a control gate, electrons are injected from a substrate through a silicon oxide film (1st insulation film) 3 and stored in a poly crystal silicon film (1st electrode) 4 being a floating gate. On the other hand, when ultraviolet rays irradiate the film 6, the electrons having injected in the polycrystalline silicon film 4 being the floating gate are emitted, a threshold voltage is shifted negatively and the transistor(TR) is in the normally-on state. The control of the threshold voltage causing normally-off and normally-on state through the injection and emission of electrons is easily implemented by making the surface impurity concentration of a p-channel region 7 proper.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor device, and more particularly to an insulated gate semiconductor device having a self-holding relay function and a semiconductor relay device using the same.

(b) Conventional technology Vertical structure semiconductor devices have been known as insulated gate semiconductor devices for large current or low on-resistance, and these semiconductor devices have also been applied to semiconductor relays. It is being said.

As a typical example of such a conventional vertical structure semiconductor device, FIG. 5 shows a vertical insulated gate transistor (MrS-FE).
T) and an insulated gate type hyperpolar transistor (IGBT) are shown in FIG.

In the MrS-FET shown in FIG. 5, 1 is a high concentration n-type silicon silicon substrate, 2 is an n-type single crystal silicon film, 7 is a p-type region, and 8 is a high concentration n! M@ area, 9°27 are each oxidized silicon film,! 0 indicates a source electrode, 11 a surface protective film, 12 a drain electrode, and 28 a gate electrode, and a channel is formed at the end of the P-type head region 7 located below the gate electrode. On the other hand, in the rGBT shown in FIG. 6, the substrate is a high-concentration p-type nested crystal substrate 13, an emitter electrode 14 is provided on the front side of the substrate, and a collector electrode 15 is provided on the back side. The configuration is similar to that shown in Figure 5.

(c) Problems to be Solved by the Invention However, when a semiconductor relay is constructed using the conventional vertically structured insulated gate type semiconductor devices as described above, these semiconductor devices themselves cannot maintain themselves as a relay. Since it does not have a function (relay signal storage function), the following problems have arisen. In other words, since there is no self-holding function, a certain voltage is always applied to the gate by the peripheral circuit to keep it in the on or off state, or
Since it is necessary to maintain the device at the ground level, the present invention has been made to solve this problem, and its purpose is to provide a semiconductor device and a semiconductor relay device that have a self-holding function without a peripheral circuit. It is to be.

(d) Means for Solving the Problems Thus, according to the present invention, the insulated gate portion of the vertically structured insulated gate transistor is provided on the first insulating film and the first insulating film constituting the gate insulating film. A first electrode constituting a floating gate, a second insulating film covering the first electrode, and a 21st! A self-holding semiconductor device comprising a pole, and a semiconductor relay device using the self-holding semiconductor device as a relay element are provided.

The present invention is applicable to MIS/PET and t-shirts used in semiconductor relays.
By making the insulated gate part of the GBT have a two-layer gate structure consisting of a floating gate and a control gate, it is possible for these elements themselves to have a self-holding function, and by using this element, This makes it possible to provide a self-holding function to a semiconductor relay.

In the insulated gate portion of the present invention, an insulating film having the same thickness and material as those used in conventional vertical insulated gate transistors can be used, for example, a film with a thickness of about 5 to 5 Qnm. A silicon oxide, silicon nitride, or aluminum oxide film is preferably used. As the first electrode constituting the floating gate and the 2111ffi constituting the control gate, a conductive material similar to that used in non-volatile memory with a so-called floating gate structure can be used, and the thickness is approximately 20 mm.
It is preferable to set it as 0-2000 nm. Moreover, as the second insulating film that isolates the first electrode and the second electrode, the first!
! The same film as the edge film can be applied, but it is suitable to use a film thicker than the first insulating film, and usually about 100 to IO
A suitable value is 00 nm. In particular, the gate structure, kidney material, and film thickness of these devices allow electrons to be efficiently accumulated from the substrate to the first electrode when a positive voltage is applied to the second electrode, and these electrons can be accumulated by ultraviolet irradiation. Preferably, it is optimized for efficient release.

(e) When a high positive voltage is applied to the working second electrode (control gate), electrons are transferred from the substrate through the first insulating film to the first t's
(floating gate) and accumulates in the second
This accumulation state is maintained even if the voltage application to the electrodes is stopped. On the other hand, when the gate portion is irradiated with ultraviolet rays, the accumulated electrons are released.

By controlling the electron accumulation and electron emission states, it becomes possible to perform ON10FF control of a vertically structured insulated gate semiconductor device, particularly of a relay element, in a self-maintaining manner.

(f) Example The present invention will be explained below based on examples.

FIG. 1 shows the manufacturing process of a MIS-FET with a self-holding function, which is an embodiment of the present invention. First, n-type impurities are doped at a high concentration and an n-type nested crystalline silicon film 2 is formed on the f-wheel crystal silicon substrate l to a thickness necessary for a desired breakdown voltage (for example, about 10 μm thick when the breakdown voltage is 100V). Evitakinoyaru, grow up! Next, a 20 nm thick silicon oxide film (first insulating film) 3 was formed on the entire surface, a 500 nm thick phosphorus-doped polycrystalline silicon film (first insulating film) 4 that would become a floating gate, a 500 nm thick oxidized silicon film (second insulating film) 5, After forming a 500-nm thick phosphorus-doped polycrystalline silicon film (second electrode) 6 that will serve as a control gate, a polycrystalline silicon film 6 and a silicon oxide film are formed using a normal battering process as shown in FIG. 1(a). The film 5, polycrystalline silicon film 4, and silicon oxide film 3 are patterned into desired shapes. Using this patterned polycrystalline Noricon film 6 as a mask, boron ions are implanted in a self-aligned manner to form a 91M region 7, as shown in FIG. 1(b). Next, using the polycrystalline silicon film 6 and a resist (not shown) as masks, phosphorus is ion-implanted in a partially self-aligned manner to form a heavily doped n-type region 8, as shown in FIG. 1(c). After forming a silicon oxide film 9 on the entire surface and performing heat treatment at 1100°C for 125 hours, the n-type region 7 spreads more than the high concentration n-type region 8 due to the difference in diffusion coefficients of poron and phosphorus, and the spread The difference is the channel length. Next, the silicon oxide film 9 is opened so that the surface of the n-type region 7 sandwiched between the high-concentration n-type region 8 and the surface of the high-concentration n-type region 8 are partially exposed, and then the source electrode The Mis-FET of the present invention can be obtained by forming and patterning an aluminum film IO, forming a surface protection film 11, and forming a gold film 12, which will become a drain electrode, on the back surface.

FIG. 2 shows the manufacturing process of an l GBT having a self-holding function, which is another embodiment of the present invention.

The difference from FIG. 1 is that a single crystal silicon substrate 13 heavily doped with p-type impurities is used as the substrate. The same numbers are used for parts corresponding to those in FIG.

The rest is manufactured according to the steps shown in FIG. 2 in the same manner as in FIG. 1, except that the aluminum film 14 on the front side is used as an emitter electrode, and the gold film 15 on the back side is used as a collector electrode.

In the embodiments shown in FIGS. 1 and 2, an oxidized film was used as the insulating film of the gate portion, but it is also possible to use a similar insulating film such as a silicon nitride film or an aluminum oxide film.

The operating principle of the device shown in FIGS. 1 and 2 is based on a nonvolatile memory (e.g., EPROM) with a floating gate structure that can be written electrically and erased by ultraviolet irradiation.
It is similar to That is, a high positive voltage (for example +
When 10 to 50 cm) is applied, electrons are injected from the substrate through the silicon oxide film (first insulating film) 3 and accumulated in the polycrystalline silicon film (first electrode) 4 which is a floating gate. At this time, the threshold voltage of the transistor shifts in the positive direction, and the transistor becomes normally off. On the other hand, when ultraviolet rays are irradiated, the electrons injected into the polycrystalline silicon film 4 serving as the floating gate are released, the threshold voltage shifts in the negative direction, and the transistor enters a normally-on state. The threshold voltage can be easily controlled so as to be normally off or normally on by injection and emission of electrons by optimizing the variation of the surface impurity a of the n-type region 7. Whatever you do,
After these electrons are injected and emitted, these states do not change even if no voltage is applied to the control gate, and have a self-holding function.

Although an n-channel device is shown in the embodiment, it can be realized by reversing the polarity of impurities in a p-channel device.

However, in this case, it is necessary to perform heat treatment to expand the n-type region by diffusion between the formation of the n-type region and the formation of the high concentration p-type region.

FIG. 3 is a circuit diagram showing a semiconductor relay device having a self-holding function, which is another embodiment of the present invention. In this semiconductor relay device, MI 5-FET with a self-holding function 16. l 7 is sauce'gti
are connected in anti-series with each MIS-F in common.
The drain electrode of ET is taken out as a drain terminal is, 19. The commonly connected source electrodes are taken out as a source terminal 20, and the control gate N pole (second N[i) is also commonly connected and taken out as one gate terminal 21. In such a semiconductor relay device, a high positive voltage is applied to the gate terminal 21 of the Mis-FET 16°17 which has a self-holding function, and electrons are transferred from the substrate to the polycrystalline silicon film (electrode 2) 4, which is a floating gate. Once injected and placed in a normally off state, this semiconductor relay remains open even when voltage application to the gate terminal 2I is stopped. On the other hand, M with self-retention function
When the IS-FET 16.17 is irradiated with ultraviolet rays, the electrons injected into the polycrystalline silicon film (first electrode) 4, which is the floating gate, are released and the state is normally on, that is, the drain terminals 18 and 19 are in a conductive state. Therefore, this semiconductor relay remains closed. The reason why two M[5-FETs having a self-holding function are connected in anti-series is to enable not only direct current but also alternating current to be applied between the drain terminals 18 and 19. Note that between the drain terminal 18 and the source terminal 20, or between the drain terminal 19 and the source terminal 20
Only a DC load can be applied between them.

FIG. 4 is a circuit diagram showing a semiconductor relay device having a self-holding function, which is an embodiment of the present invention.

In this semiconductor relay device, IGBTs 22 and 23 having a self-holding function are connected in antiparallel, and terminals 24.2 and 23 are connected in antiparallel.
5 has been taken out. Control gate electrode (second
electrodes) are connected in common and taken out as one gate terminal 26. In this device, rG with self-holding function
By applying a high positive voltage to the gate terminal 26 of BT22.23, the floating gate of the polycrystalline silicon film (
If electrons are injected into the first electrode 4 from the substrate and the state is set in a normally-off state, this semiconductor relay will remain open after the voltage application to the gate terminal 26 is stopped, while the self-holding function will be activated. When the IGBT 22 and 23 held in the hand are irradiated with ultraviolet rays, the electrons injected into the polycrystalline silicon film 4, which is the floating gate, are released and the normally-on state is established, that is, the terminals 24 and 25 are in a conductive state, and this semiconductor relay is closed. maintain condition. Here, IGB with self-holding function
Two T's are connected in anti-parallel, and f2 is so that not only direct current but also alternating current can be applied between terminals 24 and 25.

(g) Effects of the invention According to the present invention, a vertically structured Mi having a self-holding function
s-FET''Pr GBT can be realized, and by using these, a semiconductor relay device with a self-holding function can be provided.

According to such a semiconductor relay device, a self-holding relay operation can be realized without providing a special peripheral circuit for self-holding, so it is extremely useful from the point of view of miniaturization and high integration of various control elements. .

[Brief explanation of drawings]

FIGS. 1(a) to (d) are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a second manufacturing process diagram showing an embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing another embodiment of the semiconductor relay device, and FIGS. 5 and 6 are each a conventional insulated gate semiconductor device with a vertical structure. It is a configuration explanatory diagram illustrating an example. 1...High concentration n-type single crystal silicon substrate, 2...
...N-type car crystal silicon film, 3.5, 9.27...
... Silicon oxide film, 4 ... Polycrystalline silicon film (first electrode) that will become a floating gate, 6 ... Polycrystalline silicon film (second electrode) that will become a control gate, 7...p-type region, 8...high concentration n-type region, 10...source electrode (aluminum II)
, 2... Surface protective film, 12... Drain electrode (gold film), 13...
・High concentration p-type crystal silicon substrate, 14...
Emitter electrode (aluminum film), 15... Collector electrode (gold film), 16.17... MIS-FET with self-holding function. 18.19...Drain electron, 20...
・Source terminal, 2 [, 26... Gate terminal, 2
2゜23... IGBT with self-holding function. 24°25... terminal, 28... gate electrode (polycrystalline silicon film).笥3 Zuken Zuzu Zuzu Meal Zuzu

Claims (1)

[Claims] 1. An insulated gate transistor with a vertical structure in which the source electrode is on the front surface side of the substrate and the drain electrode is on the back side of the substrate, and the insulated gate part of the insulated gate transistor is connected to the gate insulating film. a first insulating film forming a floating gate; a first electrode provided on the first insulating film and forming a floating gate; a second insulating film covering the first electrode; and a first electrode provided on the second insulating film. A self-holding semiconductor device comprising a second electrode constituting a control gate capable of injecting electrons into the semiconductor device. 2. Consists of an insulated gate bipolar transistor with a vertical structure in which the emitter electrode is on the front side of the substrate and the collector electrode is on the back side of the substrate, and the insulated gate part of the insulated gate bipolar transistor constitutes a gate insulating film. a first insulating film, a first electrode provided on the first insulating film and forming a floating gate, and a second electrode covering the first electrode.
A self-holding semiconductor device comprising an insulating film and a second electrode that is provided on the second insulating film and constitutes a control gate capable of injecting electrons into the first electrode. 3. A semiconductor relay device using the self-holding semiconductor device according to claim 1 or 2 as a relay element.