JPH03208373A - Soi type thin film transistor - Google Patents

Abstract

PURPOSE:To improve the deterioration in the drain breakdown strength during OFF time while retaining the high mobility and high characteristics by a method wherein channel potential fixing electrodes are formed on a single crystal semiconductor layer grown using a single crystal substrate as a seed on the opposite side to a gate electrode and beneath a channel part. CONSTITUTION:An insulating film 2 is formed on a single crystal substrate 1 as a basic body while an opening part 3 is made in a specific region and then a semiconductor layer 4 to form a transistor is formed on the opening part 3. As for the semiconductor layer 4, single crystal or amorphous silicon is selectively epitaxial grown through the opening part 3 from the single crystal substrate 1 further to be grown in the lateral direction on the insulating film 2 or deposited covering the opening part 3 further to be grown in the lateral direction in the insulating film using the single crystal as a seed. Finally, a gate insulating film 5 and a gate electrode 6 are formed and then source and drain regions 7 are formed to form respective leading electrodes 8. Through these procedures, the high performances such as the high mobility and the low parasitic capacity by the thin film formation can be retained while enabling the transistor characteristics to be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on So r (Silicon On I
The present invention relates to a thin film transistor having a nsulating substrate structure.

[Prior Art] In recent years, 5OI transistors have been actively researched to realize three-dimensional circuit elements. Such an SOI device is
For example, it was formed as follows.

An insulating film is formed on a single crystal wafer, and holes are opened in desired areas to expose the single crystal that will serve as a seed. Next, a single crystal is grown from the seed crystal portion onto the insulating film, and a transistor is formed in that region.

As a method for growing a single crystal, a single crystal substrate with an opening in an insulating film is selectively epitaxially grown from the opening using an ordinary epitaxial apparatus, and then ELO (ELO) is applied onto the insulating film.
Amorphous silicon or polycrystalline silicon is deposited to cover the opening, and then LSPE (Latera
l 5olid Phase)
Those that have been grown are used.

Is the single crystal on these insulating films used as is?
If necessary, by polishing, etching, sacrificial oxidation, etc.
After being flattened or made into a thin film, it is etched and separated into islands for electrical isolation.

[Problem to be solved by the invention] The above-mentioned SOIO crystal has been improved in performance by bringing its crystallinity closer to that of a single crystal, and recently, the film thickness has been made ultra-thin (
There is research that attempts to obtain extremely high mobility using a unique mechanism by reducing the diameter (0.1 μm or less).

However, such research has focused only on specific characteristics, and on the other hand, various problems specific to SOI have not yet been sufficiently resolved. That is, as a result of our research on the general electrical characteristics of thin film transistors having an SOI conductor structure, the present inventors found that when the thickness of the semiconductor layer becomes thinner than a certain predetermined thickness, the well-known SOIO conductor layer In addition to the bending phenomenon (kink phenomenon) of the drain current as shown in 1 in FIG. 2 due to floating.

The drain breakdown voltage when the gate voltage is O■ (when OFF) is
It was found that the deterioration occurred more rapidly than in the case of thick films.

This is true even when the SOI MIS-FET is OFF, which is composed of semiconductor layers sandwiched between insulating layers on both sides.
The generated minority carriers accumulate in the gate insulating film in the channel region or in the low potential region near the interface with other insulating layers, resulting in deterioration of the source/drain breakdown voltage.

In order to prevent the accumulation of carriers in the channel as described above, it is necessary to set the channel potential as seen in transistors using bulk Si to prevent the accumulation of minority carriers that have flowed into the channel. Conceivable. However, if the device structure is similar to that of a transistor on ordinary bulk Si, the channel potential must be taken from outside the source/drain region, which increases the device area and increases the integration of the three-dimensional circuit required for SOIO transistors. There was a problem with the thickness (shifting) from the perspective of compatibility.

[Object of the invention] The present invention is based on the above new findings, and the SOIO
In manufactured transistors, while maintaining high characteristics such as high mobility and low parasitic capacitance due to thinner films,
The objective is to realize a thin film transistor that improves the deterioration of the drain breakdown voltage during operation and does not increase the device area.

[Means and effects for solving the problems] In order to solve the above-mentioned problems, the present invention provides an SOIO which consists of a channel part, a gate, a source and a drain part, and their extraction electrodes formed on an insulating film. In thin film transistors,
The SOTO thin film transistor is formed on a single crystal semiconductor layer grown using a single crystal substrate as a seed, and has a channel potential fixing electrode by the substrate via the seed crystal on the opposite side from the gate electrode and directly under the channel part. The present invention provides a SOIO thin film transistor characterized by the following.

According to the present invention, the carriers injected into the channel part are
The channel can be quenched by voltage-clamping electrodes,
It is possible to prevent carriers from accumulating in the channel portion.

[Example of implementation] Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing the manufacturing process of a SOIO thin transistor according to the present invention.

As shown in FIG. 1(a), an insulating film 2 is formed on a single crystal substrate 1 as a base, and openings 3 are provided in desired regions.

Next, as shown in FIG. 1(b), a semiconductor layer 4 for forming a transistor is formed on the opening 3. The semiconductor layer 4 is selectively epitaxially grown from the single-crystal substrate 1 through the opening 3 by vapor phase growth, and then grown on the insulating film 2 by lateral epitaxial growth (ELO).
Polycrystalline or amorphous silicon deposited covering the opening 3 is laterally grown into an insulating film shape using a laser or the like using a single crystal as a seed.
It is possible to use one that has been subjected to a lid phase.

If necessary, the surfaces of these semiconductor layers are flattened by polishing or the like, and then removed by etching, leaving only desired regions.

Next, as shown in FIG. 1(C) and FIG. 1(d), a gate insulating film 5 is formed and a gate electrode 6 is formed.
Using a well-known technique, source and drain regions 7 are formed by ion implantation or the like, and respective extraction electrodes 8 are formed.

[Example] Embodiments of the present invention will be described in detail using the drawings.

FIG. 1 shows a cross-sectional process flow of an SOI type thin film transistor according to the present invention.

As a plate-like substrate, P (100) 0.1 to 0.2 Ωc
A monocrystalline silicon wafer substrate 1 with a thickness of 5,000 mm was thermally oxidized to form an oxide film 2 of 5,000 mm, and an opening 3 of 1 μm was formed in the oxide film 2 by a well-known photolithography technique (see Fig. 1).
a)).

Next, selective epitaxial growth and ELO growth were performed using a normal epitaxial apparatus using 5iC1□H2 as a source gas, H2 as a carrier gas, BaHa as an impurity gas, a pressure cuff of 60 Torr, and a temperature of 10
501 layer 4 was grown under conditions of 00°C. This 5
01 layer 4 has a size of 1 to form a transistor.
After ELO growth to 5 μm x 15 μm or more, the surface is polished by normal mechanochemical polishing to a thickness of 200 μm.
It flattened to 0 (Fig. 1(b)).

Next, 500 gate oxide films 5 were formed by a thermal oxidation method, and a gate electrode 6 having a gate length of 3 μm and a gate width of 9 μm was formed to cover the opening 3. Next, source/drain regions 7 were formed by ion implantation. that time,
The opening portion 3 is connected to a channel portion into which ions are not implanted (FIG. 1(C)).

Next, after forming an interlayer insulating film 9, a contact hole 10 was formed, and an extraction electrode 8 was formed. In addition, the pull electrode 8 was taken from the substrate 1 in addition to the gate 6 and the source/drain region 7 (FIG. 1(d)).

According to this embodiment, the single crystal silicon substrate 1 for selective epitaxial growth can be used as it is as an electrode for fixing the channel potential.

If a new electrode is to be provided in the SOI layer 4, it is necessary to form a contact space and an electrode in the channel part from the side of the element surface with a step, and considering the alignment and etching margin for this, the above-mentioned As a result, the area of the device increases. In this embodiment, since the channel electrodes are substantially aligned (self-aligned) by the silicon islands, they do not interfere with the integration of devices.

The minority carriers that have flowed into the channel are quickly annihilated by the channel electrode, and KI due to potential fluctuations in the channel portion due to the accumulation of minority carriers.
It was possible to prevent the NK phenomenon.

This means that with the same configuration as this example, the SOI film thickness is
For example, even when the number of participants was 5,000 or 10,000, the same <KINK phenomenon was not observed, confirming the effect of the present invention.

In addition, the drain breakdown voltage in the OFF state was about 7.0 cm when no channel potential was taken, but in this example, it improved to more than IOV. This means that the minority carriers flowing into the channel due to the channel electrode are
This prevents minority carriers from accumulating in the gate insulating film in the channel region or in low potential regions near the interface with other insulating layers, resulting in deterioration of source/drain breakdown voltage. It is thought that this is because of this.

Moreover, this effect is sufficient even if the thickness of the SOI layer is made even thinner. For example, when 500 people are served, the withstand voltage increases from the conventional 4V to about IOV.

On the other hand, other electrical properties, especially carrier mobility,
There was no difference compared to the case where the channel potential was not fixed, demonstrating the effectiveness of this example.

In addition, in this example, the 801 layer was grown by selective epitaxial growth using a wafer substrate and by ELO, but the 801 layer was grown by LSPE using a laser beam or the like.
A similar effect was found in the layers.

[Effects of the Invention] As explained above, according to the present invention, even if the thickness of the 801 layer is reduced, there is no deterioration in the drain breakdown voltage, and the K
The INK phenomenon can also be prevented, and it has become possible to form an SOI type thin film transistor that maintains high performance such as high mobility and low parasitic capacitance due to thinning.

Further, according to the present invention, in an SOI type thin film transistor, the potential of the channel portion can be fixed without increasing the element area, and the transistor characteristics can be improved.

Further, according to the present invention, as a channel potential fixing electrode,
Since a single crystal wafer can be used as a base as it is, no special process is required.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional flowchart of a process for manufacturing an SOI thin film transistor according to the present invention. FIG. 2 is a diagram of transistor characteristics showing problems in the prior art. Substrate 2: Insulating film 3: Opening part 4: 801 layer 5: Gate oxide film 6: Gate electrode 7: Source/drain region 8: Leading electrode 9: Insulating film between eyebrows 10: Contact hole Fig. 1

Claims (1)

[Claims] SO consisting of a channel part, gate, source and drain parts, and their lead electrodes formed on an insulating film.
In the I-type thin film transistor, the SOI-type thin film transistor is formed on a single-crystal semiconductor layer grown using a single-crystal substrate as a seed, and the SOI-type thin film transistor is formed on a single-crystal semiconductor layer grown using a single-crystal substrate as a seed, and is formed on the substrate via the seed crystal on the opposite side of the gate electrode and directly under the channel part. An SOI type thin film transistor characterized by having a channel potential fixing electrode.