JPH03208359A - Wiring of semiconductor device - Google Patents

Abstract

PURPOSE:To easily wire in an equal length if a circuit having no skew is required by gathering and grouping a plurality of nets of wirings when the wirings of the plurality of nets are formed between two functional blocks, and determining a wiring route with the net group as one net. CONSTITUTION:A plurality of functional blocks 1-3 are disposed separately at channel regions C1-C3 from each other. In a semiconductor device, when wirings of a plurality of nets are respectively formed between the blocks 1 and 2, between the blocks 1 and 3, the wirings of the plurality of nets between the blocks 1 and 2 are gathered, grouped with the group as a net group A, the wirings of the plurality of nets between the blocks 1 and 3 are gathered, and grouped with the group as a net group B. A wiring route is determined with the groups A, B as one nets. Thus, if a circuit having no skew is required, the wirings of the plurality of nets formed between the two blocks can easily be wired in an equal length.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a wiring method for a semiconductor device, and more specifically, relates to a wiring method for a semiconductor device in which a plurality of functional blocks are arranged with channel regions separated from each other. 2 [Field of Industrial Application] The present invention relates to a wiring method for a semiconductor device, and more particularly, to a wiring method for a semiconductor device in which a plurality of functional blocks are arranged with channel regions separated from each other.

In recent years, LSIs have become more highly integrated and faster, making it easier for users to integrate the entire system they desire into one chip.

However, along with this, it has become necessary to design circuits that take signal flow into consideration more than ever. That is, L.S.
In the circuit design of I, it is required that a certain functional block output a plurality of output signals at the same timing and supply them to other functional blocks with the same delay time. A functional block is often a module containing a large number of basic cells, and when multiple basic cells to which signals are supplied are in the same module, the required condition is skinny, that is, the signal transmission time. There is a need to eliminate the differences.

In addition, in layout processing, wiring processing at the functional block level is to optimally allocate the wiring of nets between functional blocks to the channel areas between functional blocks, and for this purpose, in layout processing, the channel width between functional blocks must be accurately determined. It is necessary to estimate the

[Prior Art] Conventionally, in layout technology for manufacturing semiconductor devices, for example, when performing a layout that takes into account the time lag of signals between different nets on a chip, it is necessary to simply place a target cell within a functional block. Alternatively, certain types of cells were gathered close to each other using cost (weighting), and each net was wired to the same length manually for the gathered cells.

[Problems to be Solved by the Invention] However, in the conventional wiring method described above, the wiring is of equal length for each net, and since the wiring is done manually, strictly speaking, the wiring is not of equal length. However, there was a problem in that the work required a great deal of effort.

The present invention has been made to solve the above-mentioned problems, and its purpose is, for example, to reduce the wiring of multiple nets formed between two functional blocks when a skew-free circuit is required. It is possible to reduce the number of work steps and easily create equal length wiring, and during layout processing, it is possible to estimate the channel width between functional blocks and to easily and effectively place the functional blocks. The purpose is to provide a wiring method.

“Means to solve problems” FIG. 1 shows a diagram explaining the principle of the present invention.

The semiconductor device has a plurality of functional blocks 1 to 3 arranged with channel regions C1 to C3 separated from each other.

In this semiconductor device, between functional blocks 1 and 2,
When wiring of multiple nets is formed between functional blocks 1 and 3, the wiring of multiple nets between functional blocks 1 and 2 is collected and grouped, and the group is defined as net group A, and the wiring between functional blocks 1 and 3 is The wires of a plurality of nets are collected and grouped, and the group is defined as a net group B. Then, a wiring route is determined with each of the net groups A and B as one net.

[Operation] Net group A is configured by collecting the wiring of multiple nets between functional blocks 1 and 2, and functional block 1
Collect the wiring of multiple nets between and 3 and create net group B
is configured, and the wiring route is determined with each net group A and B as one net. Therefore, if a skew-free circuit is required, it is easy to wire multiple nets formed between two functional blocks. Wiring can be made of equal length.

In addition, during layout processing, channel widths between functional blocks can be estimated and the layout of functional blocks can be easily and effectively performed.

[Example] An example embodying the present invention will be described below with reference to FIGS. 2 to 5.

This example shows a case where a skew-free circuit is constructed by making the wiring of multiple nets wired between two functional blocks equal length wiring, as shown in FIG. 3.
A plurality of functional blocks 11 to 16 are arranged on the substrate with channel regions CII to C18 separated from each other.

When determining the wiring routes of multiple nets between two functional blocks in FIG. 3, first, as shown in FIG. Then, a plurality of output (or input) terminals forming a plurality of nets with input (or output) terminals of the functional block are grouped to form net groups G1 to G4. In FIG. 2, each net group 01 to G4 is formed by six terminals. Next, a main bus MBII is formed by allocating annular wiring groups Ll-L4 connected to each of the net groups 01 to G4 at predetermined intervals around the outer periphery of the functional block 11.

Each of the ring wiring groups L1 to L4 is connected to each of the groups 01 and 01, respectively.
~ Consists of the same number of wires as the number of terminals of G4, thereby,
The thickness (number of wires) of the main bus MBII is determined.

Grouping the nets and forming the main bus as described above is as follows:
The same process is performed for the other functional blocks 12 to 16.

Next, each ring wiring group of the main bus MB formed around each functional block 11-16 is treated as one wiring, and the route of the sub-bus SB for connecting the functional blocks is determined for each ring wiring group. That is, as shown in FIG. 3, the sub-bus 5B16 that connects the functional blocks 11 and 16 follows the guidelines (shown by broken lines) set in the connection information of the channel areas CIl to CI8 and the channel area CIl.
~ While considering the degree of congestion (occupancy rate) of C18, search for a route from functional block 11 to functional block 16 so that the wiring length is the shortest distance, and when the guideline adjacent to functional block 16 is reached, This is determined by connecting to the main bus MB of the functional block 16. In this embodiment, the guideline is in the channel region C11-C1.
It is set at the center of 8.

The sub-buses SB between the other functional blocks 12 to 16 are also determined in the same manner as described above.

Finally, as shown in FIG.
The wiring is completed by deleting unnecessary portions of each ring wiring group forming each main bus MB.

As described above, in this embodiment, for each of the functional blocks 11 to 16, a net group is formed by grouping a plurality of terminals that form a plurality of nets with a plurality of terminals of other functional blocks among the large number of terminals. At the same time, a main bus MB consisting of a ring wiring group corresponding to each net group is formed on the outer periphery of each functional block 11 to 16, and each ring wiring group of each main bus is treated as one wiring, thereby creating two functional blocks. Since the route of the sub-bus SB for connecting the nets is determined for each ring wiring group, some nets do not have different wiring routes in a net group where skew needs to be taken into consideration. The wiring for all nets within a group can be easily made to have the same length, and the occurrence of skew can be reliably prevented.

In addition, in this embodiment, a sub-bus S connecting two functional blocks is used.
B is treated as a single wire, and its route is searched according to the guidelines set based on the connection information of channel regions C1l to C18 between all functional blocks, so the optimal route can be determined. .

Figure 5 shows the wiring method of this embodiment for L with a built-in CPU core.
This is adopted for SI, and the clock system terminals of the CPU core 20 form a net group G5, and the wiring processing is performed for functional blocks 17 to 19, and the data system terminals of the CPU core 20 form a net group G6. is formed, and wiring processing is performed for the functional blocks 21 and 22. The output signals of the CPU 20 are clock system, address system,
There are types such as data type and control type, and by forming net groups according to the type of signals in this way, it is possible to reduce skew in peripheral circuits (functional blocks).

Incidentally, in the above embodiment, the process was carried out for a designed functional block in which the positions of a large number of terminals have already been determined, but the process may be carried out for an undesigned functional block. In other words, in an undesigned functional block, the terminals can be placed in any position, so you can collect multiple terminals that make up a net group, and consider equal length wiring for these multiple terminals inside the functional block. This is because skew can be reduced by performing the placement and wiring process.

Furthermore, in this embodiment, the route of the sub-bus SB is connected to the channel area C.
Although the search is performed according to the guidelines based on the connection information of No. 11-C18, it is also possible to take a route that takes circuit characteristics into consideration.

FIG. 6 shows an example in which the wiring method of this embodiment is adopted for layout processing. In this example, since each of the functional blocks 23 to 27 has a connection relationship of multiple nets with other functional blocks, the multiple nets are grouped for each of the functional blocks 23 to 27, and sub-buses SBI to SB5 are connected to each other.
In particular, sub-buses SB2 . SB3. SB4 has been decided. In this way, by grouping multiple nets for each functional block 23 to 27 during layout processing, it is possible to optimally allocate the wiring of nets between functional blocks to the channel areas between functional blocks. Estimation of Channel Width 9 Functional blocks can be placed easily and effectively.

[Effects of the Invention] As detailed above, according to the present invention, for example, when a skew-free circuit is required, wiring of multiple nets formed between two functional blocks can be easily done by reducing the number of man-hours. Furthermore, during layout processing, channel widths between functional blocks can be estimated, and functional blocks can be placed easily and effectively, which is an excellent effect.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a diagram showing a process of providing a main bus around the outer periphery of a functional block in one embodiment. FIG. 3 is a diagram showing a process of providing a sub-bus in a channel region. The figure shows the wiring results. Figure 5 is an explanatory diagram showing the wiring results of an LSI with a built-in CPU core using the wiring method of one embodiment. Figure 6 shows the case where the wiring method of one embodiment is adopted for layout processing. FIG. FIG. 1 Drawing Part 1 In the figure, 1 to 3 are functional blocks, A and B are net groups, and 01 to C3 are channel areas. Agent Patent Attorney Sada Igeta - Fig. 2 Fig. 3 Fig. 1 - Diagram showing the process of each area [Fig.

Claims (1)

[Claims] In a semiconductor device in which a plurality of functional blocks are arranged with channel regions separated from each other, when wiring of a plurality of nets is formed between two functional blocks, the wiring of the plurality of nets is collected and grouped. A wiring method for a semiconductor device, characterized in that a wiring route is determined using a net group as one net.