JPH0320808A - Direct digital synthesizer - Google Patents

Abstract

PURPOSE:To make a jitter small by selecting a sine wave in a high frequency area and a waveform whose inclination at a start point is larger than ever in a low frequency area corresponding to a preset frequency value in the switching of a various kinds of waveforms stored in a memory. CONSTITUTION:A frequency value conforming to the preset frequency value is inputted to an integrator 1, and the output of the integrator 1 is inputted to the address input AD of the memory 11 storing every kind of waveform data. Meanwhile, a comparator 10 supplies a waveform switching signal corre sponding to the frequency value to the memory 11 by receiving th same fre quency value as an input value to the integrator 1. In other words, the sine wave is selected when an input frequency value is the one in the high frequency area, and a rectangular wave when it is the one in the low frequency area, and the intermediate waveform of the sine wave and the rectangular wave when it is the one in an intermediate frequency area. The output of the memory 11 is inputted to a D/A converter 3, and an analog signal waveform is outputted. The output is inputted to a comparator 5 after an unrequired component being eliminated with a low-pass filter 4, and is converted to the rectangular wave with the same frequency, then, is outputted as a clock.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a direct digital synthesizer that can accurately generate waveforms of arbitrary frequencies, and more particularly, it relates to a direct digital synthesizer that can accurately generate waveforms of arbitrary frequencies. This invention relates to a direct digital synthesizer that can generate

(Prior Art) A direct digital synthesizer (abbreviated as DDS) is a frequency generator that can accurately generate a waveform of any frequency. When an operator sets an arbitrary frequency using a digital switch on a panel or the like, this DDS outputs a waveform (for example, a sine wave) at the set frequency. Moreover, this DDS is characterized in that it can finely vary the frequency in units of one digit. The type of waveform to be output (sine wave, rectangular wave, etc.) can also be set by the operator from the panel.

FIG. 4 is a block diagram showing an example of a conventional configuration of a DDS.

When the operator sets a frequency value to be generated, data corresponding to the set frequency (hereinafter referred to as frequency value) is input to the integrator 1. A master clock is manually input to the integrator 1 as an operating clock, and input data is integrated each time the clock is input. As a result, the output of the integrator 1 increases stepwise every time the master clock is input. The output of the integrator 1 is input to the address AD of the memory 2 as address data. Sine wave data is written in the memory 2, and the sine wave data that changes each time the manual address changes is outputted from the data output DATA in synchronization with the master clock.

The output of this memory 2 enters the D/A converter 3 and is converted to an analog signal. As a result, the D/A converter 3 outputs a sine wave converted to an analog signal.D
The output of the /A converter 3 is passed through a low pass filter (LPF) 4.
The waveform is shaped into a smooth sine wave by The waveform-shaped sine wave is input to a comparator 5 as required, converted into a rectangular wave, and then output. Alternatively, the output of the low-pass filter 4 may be output as is.

(Problem to be solved by the invention) In the conventional circuit described above, when the frequency is varied continuously (continuously in phase) over a wide range (for example, when sweeping), jitter (frequency fluctuation) is proportional to the period. In particular, the jitter of the generated waveform in the low frequency range was relatively large. For example, if a frequency sweep of 1000 times is performed, the amount of jitter will also be 1000 times greater. This will be explained in detail below.

Generally, when a sine wave is output by a D/A converter, the amount of jitter can be obtained from the quantization noise and the slope of the sine wave, then the amount of jitter - (peak value of noise / slope of sine wave) - T /
(2B ・π) It is expressed as (1). Here, B is the number of bits of the D/A converter, and T is the period of the output signal. Due to the frequency sweep, as the frequency data is updated, the sine wave changes as shown in FIG. f in the diagram
l-f3 indicates a sine wave waveform, f3 has the highest frequency, and f1 has the lowest frequency. 11 to g3 are the slopes at the starting point O of the respective sine waves f1 to f3.

The lower the frequency, the smaller the slope. On the other hand, the peak value of noise included in the output is almost constant regardless of frequency. Therefore, according to equation (1), the amount of jitter becomes larger at lower frequencies.

The present invention has been made in view of these problems, and its purpose is to realize a direct digital synthesizer with less jitter over a wide frequency range.

(Means for Solving the Problems) The present invention for solving the problems described above includes an integrator that receives a frequency value and calculates its integrated value for each master clock, and stores various waveform data, and the integrator In a direct digital synthesizer, the direct digital synthesizer is composed of a memory that receives the output of the memory as an address and outputs stored data, a D/A converter that receives the output of the memory, and a low-pass filter that receives the output of the D/A converter. , a comparator is provided that receives the frequency value and generates a signal for switching the type of waveform stored in the memory according to the value, and generates a sine wave in the high frequency region and a waveform with a larger slope at the starting point in the low frequency region. It is characterized by being configured so that it can be selected.

(Operation) In the high frequency region, sine wave data is read from a memory in which various waveforms are stored, and in the low frequency region, waveform data having a larger slope at the starting point is selected. As a result of selecting a waveform with a larger slope at the starting point in the low frequency region, it is possible to reduce the jitter according to equation (1).

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 4 are designated by the same reference numerals. In the figure, 10 is a comparator that receives a frequency value and generates a signal for switching the types of waveforms stored in the memory according to the frequency value, and 11 is a memory that stores various waveforms.

The memory 11 stores various waveforms as shown in FIG. 2, for example, in the form of digital data. (A) is a sine waveform, (C) is a rectangular waveform, and (B) is a waveform with rounded corners that is intermediate in character between a sine waveform and a rectangular waveform. The operation of the circuit configured as described above will be explained as follows.

When the operator sets a frequency value to be generated, data corresponding to the set frequency (hereinafter referred to as frequency value) is input to the integrator 1. A master clock is input to the integrator 1 as an operating clock, and input data is integrated each time the clock is input. As a result, the output of the integrator 1 increases stepwise every time the master clock is input. The output of the integrator 1 is input to the address input AD of the memory 2 as address data. The memory 2 stores various waveform data as shown in FIG.

On the other hand, the comparator 10 receives the same frequency value and provides the memory 11 with a waveform switching signal according to the frequency value. Specifically, if the input frequency value is in the high frequency region, a sine wave as shown in Figure 2 (A) is selected, and if it is in the low frequency region, the sine wave as shown in (C) is selected. A rectangular wave is selected, and if the waveform is in the intermediate frequency region, a switching signal is generated to select the intermediate waveform as shown in (opening) and is applied to the memory 11.

When the type of waveform stored in the memory 11 is determined by the waveform switching signal, the memory that receives the output of the integrator 1 as address data outputs the waveform data stored at the corresponding address from the data output DATA. In this case, since the master clock is input to the integrator 1 and the memory 11 as a synchronization signal, the integrator 1 output changes in synchronization with the master clock, and the memory 11 receives the integrator 1 output as address data. The output also changes in synchronization with the master clock.

The output of memory 11 enters D/A converter 3. Since D/A converter 3 also contains a master clock, the D/A converter 3
The output of converter 3 also changes in synchronization with the master clock,
As a result, an analog signal waveform corresponding to the waveform data read from the memory 11 is output from the output. D/
Among the output of the A converter 3, a frequency component higher than 1/2 of the frequency of the master clock is an unnecessary component caused by D/A conversion, and the unnecessary component is removed by the low-pass filter 4. .

The output of the low-pass filter 4 enters the converter 5, where it is converted into a rectangular wave of the same frequency and output as a clock. In the illustrated embodiment, the output of the converter 5 is used as the output, but the output of the low-pass filter 4 may be used as the output.

Next, the jitter suppression function according to the present invention will be explained. The comparator 10 outputs a sine wave when the human frequency value is a high frequency, a rectangular wave when it is a low frequency, and an intermediate wave as shown in FIG. A waveform switching signal for selecting a wave is given to the memory 11. In the high frequency region, as is clear from FIG. 5, the slope of the waveform (1) 3) at the starting point of the sine wave is sufficiently large.

Therefore, the jitter given by equation (1) can be made sufficiently small.

On the other hand, in the low frequency region, as is clear from FIG. 5, the slope at the starting point of the sine wave becomes smaller. Therefore, if a sine wave is used even in a low frequency region, jitter increases as is clear from equation (1). In the present invention, a rectangular wave having a larger slope at the starting point is used in the low frequency region. In the case of a rectangular wave, as is clear from FIG. 2(c), the slope at the starting point is the largest. Therefore, even in the low frequency region, the jitter determined by equation (1) can be suppressed to the period of the master clock.

Furthermore, in the intermediate frequency region, by using an intermediate region waveform between a sine wave and a rectangular wave as shown in FIG. 2, it is possible to sweep the frequency more smoothly (phase continuous).

FIG. 3 is a diagram showing jitter characteristics showing the effects of the present invention. The horizontal axis indicates the frequency expressed on a logarithmic scale, and the vertical axis indicates the amount of jitter. The maximum frequency is fm. f1 indicates the jitter characteristic according to the conventional circuit, and f2 indicates the jitter characteristic according to the present invention. In the case of the conventional circuit, f
As shown in Figure 1, the relationship between frequency and jitter is represented by a straight line. In other words, jitter is suppressed to a low level in the high frequency range, but increases as shown by the broken line in the low frequency range. In contrast, in the case of the present invention, the low frequency region has a flat jitter characteristic as shown by f2. This flat area indicates the minimum level of jitter determined by the period of the master clock.

In the above embodiment, three types of waveforms, sine waves, rectangular waves, and intermediate waves, are shown as types of waveforms to be stored in the memory, but the present invention is not limited to these. Depending on the case, there may be two types of waveforms, a sine wave and a rectangular wave, or four or more types of waveforms. In short, in the low frequency region, it is sufficient to use a waveform that has a larger slope at the starting point.

(Effects of the Invention) As described above in detail, according to the present invention, in the low frequency region, waveform data in which the slope at the starting point is larger than that of the sine wave is stored in the memory. By configuring the waveform data to be read in the frequency domain, it is possible to realize a direct digital synthesizer with less jitter over a wide frequency range.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention;
The figure shows various waveforms stored in memory, Figure 3 shows jitter characteristics showing the effects of the present invention, and Figure 4 shows DDS.
FIG. 5 is a block diagram showing an example of a conventional configuration. 1... Integrator 3... D/A converter 4
...Low pass filter 5...Comparator 10
...Comparator 11...Memory.

Claims (1)

[Claims] an integrator that receives a frequency value and calculates its integrated value for each master clock; a memory that stores various waveform data and receives the output of the integrator as an address and outputs the stored data; a D/A converter that receives the
A comparator that receives the frequency value and generates a signal for switching the type of waveform stored in the memory according to the frequency value in a direct digital synthesizer configured with a low-pass filter that receives the output of the D/A converter. 1. A direct digital synthesizer characterized in that the direct digital synthesizer is configured to select a sine wave in the high frequency region and a waveform with a larger slope at the starting point in the low frequency region.