JPH03206773A - Pll output switching device - Google Patents

Abstract

PURPOSE:To attain circuit integration, to make the device small and to save number of components by using a single PLL signal processing circuit so as to attain switch selection of two kinds of high frequency oscillation clock phase- locked to a horizontal synchronizing signal. CONSTITUTION:A single signal processing circuit consists of plural coils 6, 7, plural frequency dividers 8, 9, and plural switches 10, 11, 12 connecting each to a single signal processing PLL circuit (comprising circuits 2-5) and selecting and extracting a desired high frequency clock being the output. Thus, the phase- lock of plural kinds of high frequency clocks with respect to a same horizontal synchronizing signal is simply designed by using the single signal processing PLL circuit (comprising circuits 2-5) and complicated circuit constitution is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a plurality of signal processing systems that are necessary for a device that switches the aspect ratio using a switch when displaying a television signal or a high-definition signal on a video monitor. This invention relates to a PLL output switching device for obtaining a high frequency clock. Conventional technology In general equipment, for example, when two types of high-frequency clocks were to be locked to the same horizontal synchronization signal, two systems of PLL circuits were provided, but the integration of circuits, miniaturization of equipment,
Efforts are expected to be made to simplify the process in order to save on parts. Figure 2 shows a signal system diagram related to conventional PLL output switching. In FIG. 2, 13 is a detector that extracts a horizontal synchronization signal from the composite video signal, and the extracted synchronization signal is sent to the output of a frequency divider 19 and a phase comparator 14, which will be described later.
The phase is compared with . 15 is a CO that adjusts the voltage of the voltage controlled oscillator (VCO) 16 based on the output of the phase comparator 14.
This is a controller, and this C016 controls the high/low of the oscillation frequency of the coil 17. The high frequency clock output from the V C 016 is waveform-shaped by a waveform converter 18. Here, 13 to 18 are integrated circuits, and a first integrated circuit, which is a signal processing circuit, is set. 19 converts the frequency of the high frequency clock output from the waveform shaper 18 into the horizontal synchronizing signal frequency 15. This is a frequency divider that makes the frequency 7kHz.
The above is a loop (PLL) system for phase-locking one high-frequency clock to a horizontal synchronization signal. Similarly, a second integrated circuit (2
0 to 26 (corresponding to 13 to 18 of the first integrated circuit) are set, and by adding the frequency divider 26 to this, another loop 7' (PLL) system is formed.

As described above, the two types of high frequency clocks produced by each system are selected by the switch 27 using the control signal, and finally a desired high frequency clock can be obtained.

Problems to be Solved by the Invention In the case of a conventional device, two
Since two systems of PLL circuits were required to phase-lock different types of high-frequency clocks, the circuit structure was redundant and complicated. The present invention solves the above problem, and the same circuit system can be used in two ways.
The object of the present invention is to provide a PLL output switching device that enables simplification of circuit layout, rather than providing one PLL output switching device.

Means for Solving the Problems In order to solve the above problems, the PLL output switching device of the present invention combines a single signal processing circuit with a plurality of coils and a plurality of It is equipped with a frequency divider and a plurality of switches that perform synchronization switching between them, connect one of each to the single signal processing circuit, and select and take out a desired high-frequency clock as an output. .

Effect Due to the above ellipse, the circuit structure allows phase-locking of multiple types of high-frequency clocks to the same horizontal synchronization signal using a single signal processing circuit, which eliminates the need for conventional complicated circuits. Yokosei can be omitted. EXAMPLE An example of the present invention will be described below based on the drawings. FIG. 1 is a block diagram of a PLL output switching device according to an embodiment of the present invention. Here, as in the conventional technology, a television signal is set as the input signal. In Figure 1, 1
is a detector that extracts the horizontal synchronization signal from the video composite signal, and this extracted horizontal synchronization signal is passed to the first frequency divider 8.
Alternatively, the phase is compared with the output of the second frequency divider 9 by the phase comparator 2. 3 is a VCO controller that controls the voltage of a voltage controlled oscillator (VCO) 4 using the output of the phase comparator 2, and the VCO 4 applies a desired frequency to the first high frequency coil 6 or the second high frequency coil 7, respectively. make it oscillate. The first frequency divider 8 and the second frequency divider 9 change the oscillation frequency of the first high-frequency coil 8 and the second high-frequency coil 9 to 15.0, which is the frequency of the horizontal synchronization signal, respectively. This is to divide the frequency into 7kHz. 5 is a waveform shaper that shapes the waveform of the high frequency clock oscillated by VCO4. 1
0 is the first high frequency clock output from the waveform shaper 5.
A switch 11.12 is a switch that switches and connects the first coil 6 or second coil 7 to the VCO 4, and these switches 10 to 12, synchronous switching is performed by a control signal. In the above-mentioned ellipse, the two types of high frequency clocks phase-locked to the horizontal synchronization signal are synchronized and switched by the three switches 10 to 12, so that a desired high frequency clock is selected and extracted.

Effects of the Invention As described above, according to the present invention, a single PLL signal processing circuit can switch between two types of high-frequency oscillation clocks that are phase-locked to a horizontal synchronization signal. The signal processing circuit can be omitted to one system, resulting in significant effects in terms of circuit integration, device miniaturization, and parts savings.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PLL output switching device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional PLL output switching circuit. 1...Horizontal synchronization signal detector, 2...Phase comparator, 3
...vCO controller, 4...Vco, 5...
- Waveform shaper, 6.7... First and second high frequency coil, 8.9... First and second frequency divider, 10-1
2...Sinch.

Claims (1)

[Claims] 1. A PLL output switching device obtained by switching a loop that synchronizes the phase of a plurality of high-frequency clocks generated inside the device with a horizontal synchronization signal extracted from a composite video signal input from outside the device. one signal processing circuit, a plurality of coils that generate high-frequency clocks, a plurality of frequency dividers that divide the respective high-frequency clocks to obtain the frequency of a horizontal synchronization signal, and the plurality of coils and a plurality of frequency dividers. A PLL output switching device comprising a plurality of switches for performing synchronous switching, one of each being connected to the single signal processing circuit, and selecting and extracting a desired high frequency clock.