JPH03206707A - Switched capacitor circuit - Google Patents

Abstract

PURPOSE:To reduce the definite GB product of an operational amplifier OP and to attain low power consumption by attaining addition with one operational amplifier, and forming a switched capacitor circuit. CONSTITUTION:The circuit consists of a 1st coefficient circuit network AC where 1st unit blocks each comprising switched capacitors are arranged as a matrix, and a 2nd coefficient circuit network BC comprising similar 2nd unit blocks. Moreover, an adder OP is provided, which fetches an input signal to an input terminal via the 1st coefficient circuit network AC to calculate it and fetches the output signal from an output terminal to the input terminal via the 2nd coefficient circuit network BC to calculate it. Addition arrays of each coefficient in the 1st coefficient circuit network AC and the 2nd coefficient circuit network BC are arranged in the relation of realizing each coefficient of the transfer function of the entire circuit as to each column and each row and each unit block is formed in the circuit in response to the sign of each coefficient. Furthermore, switches are switched in a prescribed order with clock pulses more than the coefficients by a prescribed number. Thus, the number of operational amplifiers is decreased to attain power saving and high circuit integration and the effect of the definite GB produce is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a capacitor circuit that can be used as an analog sample value filter. (Prior art) This type of switched capacitor
-CapaCitor; S C ) The circuit consists of a four-capacitor, a switch that opens and closes periodically, and an operational amplifier as a voltage-controlled voltage source. This SC circuit has the characteristics of low power consumption and high integration density because its elliptical elements can be realized using MOS technology. especially,
This SC circuit has high accuracy and high stability because the transfer coefficient is determined by the capacitor ratio.

FIG. 10 is a circuit example showing a conventional SC circuit that realizes a biquadratic transfer function. The circuit shown in Figure 10 consists of FLEISCHER and LAKER
), and it is well known that it uses two operational amplifiers and two-phase clock pulses to realize various filter characteristics. This SC circuit consists of capacitors A-D, G, and I, and a switch SW that switches using two-phase clock pulses φ1φ2.
1 to SW7 and operational amplifiers OP+OP2. Input zero pressure ■, is switch SW5, -1 Yapacita G,
Operational amplifier OPi is connected via a circuit consisting of switch SW6.
It is also input to the operational amplifier OP2 via the capacitor . An integrating capacitor D is connected between the input and output of the operational amplifier OPi, and an integrating capacitor B is connected between the input and output of the operational amplifier OP2. A capacitor E and a switch SW are connected to the input terminal of the operational amplifier OP1 and the output terminal of the operational amplifier OP2.
A circuit consisting of a, SW4, and a capacitor C is connected. The output of operational amplifier OP1 is connected to switch SW+
, SW2-capacitor A are connected. The output VO of the circuit can be taken out via a switch SW7.

According to such an SC circuit, capacitors A to D, G,
By setting I to a predetermined value and switching the switches SW+ to SW7 with two-phase clock pulses φ1 and φ2 of a predetermined frequency, various filter characteristics can be obtained.

(Problems to be Solved by the Invention) According to such an SC circuit, two operational amplifiers are required, power consumption increases, high integration is not possible, and the high frequency range inherent to operational amplifiers increases. The disadvantage is that the gain is strongly affected by attenuation. In addition, the major cause of characteristic deterioration in the above SC circuit is
The finite gain bandwidth product of an operational amplifier (hereinafter referred to as the finite GBM in the field
). Figure 11 is the SC of Figure 10.
It shows the characteristic change due to the existence of the circuit @GB[,
The horizontal axis shows the ratio of the sampling frequency fs to the frequency f of the input voltage, and the #ti axis shows the attenuation ratio [dB; ”, 1986, Institute of Electronics and Communication Engineers,
CAS86-38, pages 23-30).

In the conventional SC circuit shown in FIG. 10, the unit gain frequency f
When t-100kHz and capacitor C=1000PF, the ideal characteristic a) as shown in Fig. 11 is obtained by calculating the sampling frequency fs=30kHz, resulting in characteristic b), and the sampling frequency f,
When the calculated value is set as =50kHz, characteristic C) is obtained. In addition, in the conventional SC circuit shown in Fig. 10, when the unit gain frequency ft = 100 kHz, the resistance R = 150 Ω, and the capacitor C 1000 pF, when actually measured, the result is as shown by O in the diagram when the sampling frequency fs = 30 kHz. , sampling frequency fs=50 κ
When the value is Hz, the value is indicated by an x in the diagram, which is approximately above the calculated value. Here, ft/f. ″-3.3, the characteristics have deteriorated,
The characteristics deteriorate further at ft/fs:2. Also, the notch frequency moves and the gain attenuates. SUMMARY OF THE INVENTION An object of the present invention is to provide a switched capacitor circuit which solves the above-mentioned problems of the prior art, achieves power saving and high integration by reducing the number of operational amplifiers, and reduces the influence of finite GBM. do. (Means for Solving the Problems) In order to achieve the above object, the first switched capacitor circuit of the present invention takes in a signal, delays it by a unit, and multiplies each unit-delayed signal by a predetermined coefficient. a first coefficient circuit network configured by arranging first unit blocks consisting of switched capacitors in a matrix shape,
a second coefficient circuit network configured by arranging second unit blocks in a matrix, each consisting of a switch capacitor that takes in a signal, delays it by a unit, and multiplies each unit-delayed signal by a predetermined coefficient; an adder that takes input signals through the first coefficient circuit network into a manual end and calculates them, and takes an output signal from the output end into the input end through the second coefficient circuit network and calculates them; The first coefficient circuit network and the second coefficient circuit network realize each coefficient of the transfer function of the entire circuit by adding columns of each coefficient in each row and each column of unit blocks arranged in a matrix. In addition, the unit blocks are arranged in a circuit configuration according to the sign of the coefficient, and the switches of the first coefficient circuit network and the second coefficient network are activated by a predetermined number of clock pulses that are greater than the coefficient by a predetermined number. It is characterized by a configuration in which switching is performed in sequence. Further, in the second switched capacitor circuit of the present invention, unit blocks made of switched capacitors that take in a signal, delay it by a unit, and multiply each unit delayed signal by a predetermined coefficient are arranged in a matrix. and an adder that receives an input signal through the coefficient circuit network to an input terminal and calculates the input signal. The addition column of each coefficient in a column is arranged in such a manner that it appears in each row and each column, and the unit block has a circuit configuration according to the sign of the coefficient, and the number of switches in the coefficient network is a predetermined number from the coefficient. This is characterized by a configuration in which switching is performed in a predetermined order using a large number of clock pulses.

(Function) According to the first switched capacitor circuit of the present invention, the following functions are achieved.

An infinite impulse response (IIR) direct form 1tI circuit consists of an adder that adds the applied signals, a unit delay element that delays the input signal, and a signal obtained by this unit delay element that is multiplied by a certain coefficient. It consists of a coefficient multiplier that supplies the adder, a delay element that delays the output from the adder, and a coefficient multiplier that multiplies the signal obtained by the delay element by a certain coefficient and supplies it to the adder.

Here, if a storage element is configured with a capacitor that depends on the coefficient and a switch related thereto, and the first unit block and the second unit block are configured by replacing the delay element and the coefficient multiplier, the coefficient addition A switched capacitor circuit with a single operational amplifier can be obtained. Here, the first unit block aQ, al according to the coefficient
, . . . +all are prepared and arranged while maintaining a constant relationship in each row and each column. Second unit block 1+bi, b2
, ..., bN are prepared and arranged maintaining a constant relationship in each row and each column. That is, each unit block is arranged according to each coefficient when determining the transfer function of the switched capacitor circuit. In addition, each block is provided with a positive phase circuit, a negative phase circuit, and a pass circuit according to the sign of the coefficient, and the circuits are selectively arranged according to the coefficient. By doing this, an SC circuit can be obtained with one adder. Also, since it is one adder, finite Q
The influence of the B product can be kept small. On the other hand, the second switched capacitor circuit of the present invention has the following effects. Finite impulse response (F
The circuit of IR) can be obtained by omitting the second coefficient circuit in the first switched capacitor circuit. Although the coefficients are different for the first switched capacitor circuit described above, they are almost the same in structure. The effects are also almost the same.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

1 to 5 are diagrams shown to explain one embodiment of the present invention. FIG. 1 is a block circuit diagram showing an embodiment of the switched capacitor circuit of the present invention. 2(I)-(V) are circuit diagrams showing unit blocks used in the SC circuit of FIG. 1. FIG. 3 is a diagram showing clock pulses for driving the SC circuit of FIG. 1. FIGS. 4(I) and 4(II) are explanatory diagrams for determining the transfer function in consideration of the finite GB product of the circuit in FIG. 1. FIG. 5 is a circuit diagram for explaining the principle of the present invention. Now, the principle of the present invention will be explained using Fig. 5. In Figure 5, the output signal y is obtained by adding the given signals.
, an adder Σ that outputs the input signal X, a unit delay element that delays the input signal X, and coefficient multipliers aO, a1, .
. . , am, a delay element that delays the output from the adder Σ, and coefficient multipliers b1, b2, .
, bn, an infinite impulse response (IIR) type circuit is constructed. This circuit can be constructed as follows. First, assuming that the required Z-domain transfer function is the following equation, then. If this formula is used as a time function formula, it becomes . Here, x (n) is the input signal and y (n) is the output signal. As can be understood from this figure, if a capacitor that depends on the coefficient and a switch opened by it are used as storage elements, an operational amplifier for the delay element is not required, and an SC circuit can be completed with a single operational amplifier for the adder Σ. It can be realized.

FIG. 1 shows an SC circuit configured as described above, which includes an operational amplifier OP as an adder Σ, a capacitor CO connected between the input and output of the operational amplifier OP,
Input signal X is passed through coefficient multipliers aQ, ai,...,a
．． A first unit block aOal consisting of a capacitor and a switch acts as . a and y are supplied to the operational amplifier OP through a first coefficient network AC arranged in a matrix, and feedback coefficient multipliers bi, b2, . . . , b. Feedback is provided by a second coefficient circuit BC in which second unit blocks 1+b1, b2, . ? Here, the first coefficient circuit AC also has the second coefficient circuit #! lB
C also has a first unit block at:+. ai, ゛゜゛aM, or second unit block 1+b1, b2,・
... bN are arranged in a matrix, and the first coefficient circuit network AC is composed of evening lock pulses φ0, φ1..., φMa
+, the second coefficient circuit BC receives clock pulses φ'1,
With φl 2,..., -φ Ni1, each row is charged by turning on two clock pulses φJ,
The structure is such that when one clock pulse φ is turned on, the discharge occurs one row at a time. In addition, the clock pulses φ0, φ1, ..., φtl,
The clock pulses φ11, φ02, ..., φ N + each pulse width T is the same as the sampling period, and φ0
, φ1 ,..., φMa1 and φ゜1φ12,...
・, φ1N+1 timing is φ0, φ1..., φ■1
The rising edge of one of the pulses and φ11, φ゜2,...
・．． It is sufficient if it coincides with the rise of any one of φ1N+1. FIG. 3 shows a state in which the rises of the clock pulses φa and φ°1 coincide.

In addition, in the above embodiment, in order to store all the delay data of the above equation (1), (M+1)(
M+2) and N(N+1) are prepared for the coefficients of the numerator, and furthermore, with M=N, the capacitor CO for the operational amplifier OP is normalized to l.

FIG. 2 (I> is the first unit block a+ (here,
i=0.1,2,...,M) [or second unit block b, (where i=1,'2,...N) This is what is shown. When connecting to an external circuit or as shown in Figure 2 (I),
As the first unit block/block ao I a+ ,..., aM, coefficient multipliers aQ , ai ,..., all
By the sign of a. >O, the positive phase circuit in Figure 2 (II) is a, and when 0, the negative phase circuit in Figure 2 (II[), aI
-0, the bus circuit shown in Figure 2 (■) is used.

Moreover, when the connection relationship with the external circuit is as shown in FIG. 2 (I), the second unit block t+b1, b2,..., b
As N, coefficient multipliers b1, b2,...bN
According to the sign of b. =
When O, the bus circuit of FIG. 2 (IV) is used.6 Note that the first unit block aD'la11..., aM also has the second unit block l+bB... b2,..., bN
Also, when compensating for gross capacitance, use the circuit shown in Figure 2 (V). That is, the reverse phase first unit block a1 in FIG. 2 (II)
has a configuration in which a capacitor CM+ is connected between switches SWJ and SWJ connected in series between the input line q and the ground potential, and switches SWK and SWJ connected in series between the output line r and the ground potential. be.

The positive phase first unit block a1 in FIG. 2 (I[) includes switches SWJ, which are connected in series between the input line q and the output line r.
It has a structure in which a capacitor C is connected between the midpoint of SWK and the ground potential.

The pass circuit shown in FIG. 2 (IV) has no circuit and only an input line q and an output 11r.

The first unit block in Figure 2 (V). , is a switch S W J・S W JSWK between input line q and output line r.
and a capacitor C at are connected in series, and a capacitor C1
Both ends of the switch SWl [ , SW, are grounded, and the connection point of the output line measurement switches sW, , SWK is connected to the capacitor C.
．． , is doubled and is grounded. This circuit is called a parasitic capacitance compensated anti-phase integrator and eliminates the influence of parasitic capacitance. In addition, the second unit block 1-1-tz
, b2, . The operation of the embodiment constructed as described above will be explained. Clock pulse φO, φ1, ·゜゜, φtorl, φ10,
It is assumed that φ'1, . . . , φ'N+1 are given in the state shown in FIG. And in Figure 1,
First unit block aQ. al. . . . am and the second unit blocks 1+b+, b2, . In addition, in Fig. 7l, the first unit block aQ,
ai ・゜゜゜・aM and second unit block 1+bl
, b2 , ..., bN indicate that each capacitor in a vertical column is connected to the inverting input terminal of the operational amplifier OP when the number of the clock pulse φ shown in the diagram of the block is on. become. That is, in the first left column of FIG. 1, the sampling time φ. +
ao + a1 +...a corresponding to 1 to φ1
ll coefficient capacitor is also sampled at the sampling time φNi
1 to φ12t. 1+b1, b2 corresponding to ,...
・b. The coefficient capacitors to their left store the input signal at the time of the clock pulse on, and the charge thus stored is transferred to the second coefficient in the first coefficient network AC at the time of the clock pulse φ0. Circuit, II! i
In BC, all calculations are performed and output when evening lock pulse φ11 is turned on. After that, the second row, third row, fourth row, etc.
and IIJ! The following calculation will be performed in the same way. At this time,
The 1 of the feedback capacitor (1+b1) erases the output of the operational amplifier OP immediately before each cycle.

By the way, in the above embodiment, if the characteristics of the operational amplifier OP are ideal, no problem occurs in the characteristics.

However, in reality. Subject to m constraints. especially,
The presence of the operational amplifier OP @GBI deteriorates the characteristics of the entire SC circuit, and specifically limits the sampling frequency f3. Also, from the sampling theorem, it is necessary to set the sampling frequency f5 to at least twice the frequency used.

Therefore, a transfer function considering the finite GBI of the above embodiment will be determined.

The operational amplifier OP can be approximated by the frequency response of a first-order delay element with a high DC gain. Therefore, if the unit gain frequency of the operational amplifier alone in the circuit composed of the operational amplifier OP and the capacitor CD in FIG. 4 is ft, then the high FfU
In the wave front region, it can be approximated as follows. ddtv. (t)=-2πf t v+-(t)
(3) Since the configuration shown in FIG. 1 has the same circuit configuration for each sampling period, we will determine the response for one section (;T=1/fs) of a certain sampling period. That is, n
Operational amplifier OP in one section of T≦t≦(n+1)T
Let us analyze the influence of the finite G8 product of . Since the inverting input terminal voltage of the operational amplifier OP changes discontinuously at each sampling point, the voltage immediately before and immediately after that point will be expressed as follows. Immediately before t=nT・v+fi(n) Immediately after t=nT”・V111(fi”) Also, the relationship between each constant of the original circuit and the capacitance is expressed as follows. 1) The standardized 1 of the operational amplifier integration capacitor is C
Let it be o. 2) Set 1 of unit block (1+b1) to 01 (=Co)
Suppose that 3) Express the capacitance of other coefficients as follows. [Response from immediately after time nT to (n+1)T] The circuit state in this period is as shown in FIG. 4(I). According to the law of conservation of charge, +Co[v+. (t)
−v+. (n')-{vo(t) vo(n))]=
O ・-<4)-'-vo (t) =v0(n)
+K {v+,,(t) −Mla(n”) )
- (5) It will be a failure. The approximation formula for the high frequency region of the operational amplifier OP is Equation (3), so if we rearrange Equation (3) by differentiating both sides of Equation (5), we get 2πft −'− v+a(t) +▼v+ −(t) =Qum
...(7) Solving with the initial value as V lm (n”), time (n+
1) The input of the operational amplifier just before T is v +Il(n+1) = v ln(n'')e1...
・(8) Substituting the above equation into equation (5), the output immediately before (n+1)T is Vo (n+1) = vo (n) K (1e-tsv+a(n')...(9) However, 2π f, p=3 ``7''...(10) (Response immediately before and after nT) In this section, the input terminal pressure of the operational amplifier OP becomes discontinuous.The circuit state is as follows. As shown in FIG.
and bL are assumed to be negative coefficients. In such a circuit, according to the law of conservation of charge, when we realize the term with a negative coefficient of the numerator polynomial in equation (1), the term with a positive coefficient of the denominator polynomial, and c1 with TSC, time From equation (12), the operational amplifier input terminal voltage immediately after nT is calculated by substituting equation (13) into equations (8) and (9), respectively. (n+D C c.i.+c+ +”i Cbm+Co }' e
-p[Co V +a(n) Vo (n+1) =vo (n) -Co'(1-e
-p) [Co v+a(n) ... (15) Furthermore, when formulas (14) and (15) are converted by 2, (zl)Vo (2)= co (1-e-') [CoV+. (z) Substituting equation (16) into equation (17), +fi C
amCo −'Z−'} X (Z) {C1 Co −
'z-'+c Cbm+C(1-'Z-' CbL
Co-'Z-Lkζl +c Cbm+Co -'z-'} Y (Z)
...(18) Therefore, e-t(2 1)Vo (z) ...(19) Since the output V O (n+l) is y (n), v
Q (z)-”Z-'Y (z), and [(I
K-'e-''z-two (1-z-')+(1-e one
{I in z: bm z−″} ] Y (z)k−1 = (1− e −′) fia, z −”X (z
)...(20) Therefore, the transfer coefficient considering the finite GB product of the operational amplifier is:
H (z") = "-Engineer X (z-') However, ... (23). In the case of FIG. 2(V), it is sufficient to double the coefficient corresponding to FIG. 2(V) for the second and subsequent items in the above equation (23). As can be seen from equations (22) and (23) above, the fact that the numerator coefficient does not change means that the designed zero point does not move. Thus, it can be seen that this example has very excellent characteristics. Next, Figure 6 shows the configuration of a specific circuit that realizes a biquadratic transfer function. FIG. 7 shows the clock pulses of the circuit of FIG. However, the coefficients of the numerator and denominator are equal <-
M=N=2. Further, the clock pulse of the first coefficient circuit network AC and the clock pulse of the second coefficient circuit III48C are shared. To that end, the second coefficient network BC
It is assumed that the clock pulse of the first coefficient circuit 11i1AC is the same as that of the first coefficient circuit 11i1AC. At this time, in the prototype circuit of FIG. 1, the second coefficient network BC has N (N+2) coefficients. The specific circuit that realizes the biquadratic transfer function is originally elliptical as shown below. That is, the input signal ratio X is supplied to the inverting input terminal of the operational amplifier OP by a circuit in which first unit blocks aQ, ai, a2a3 are arranged in a matrix. Further, the feedback is performed by a circuit in which second unit blocks b (1, b1, b2, b3 are arranged in a matrix).

Here, the first unit block ao. a1, a2a
As shown in Figure 6, a circuit in which 3 is arranged in a matrix is reduced in number by reducing the number of capacitors that can be shared, and by reducing the number of switches SW by reducing the number of switches SW that can be shared. It dominates α. Also, the first unit block bo, Lz, b2, bs
As shown in Figure 6, a circuit in which the It forms an elliptical coefficient circuit β that is insensitive to capacitance. Furthermore, switches SWo, SW1, SW
2, SWs are clock pulses φ0, φ shown in FIG.
1. Switching operation is performed by turning on φ2 and φ36
Also, the coefficient circuit α? Sita is C. . ,c,,,C,
．． The capacitor of the coefficient circuit β is Cfl+C
Consisting of I21 Crs. Here, Ct+=2 (
C+ Cy), Ctz=2Cb■, Cts=2
(C + C b+ + C b2). Further, C0 is an integral capacitor of the operational amplifier OP.

In addition, the capacitor C Ilo+ C a l C a
2+ C ylC f2+ C ts. Assume that the values of C o are given as shown in Table 1. [Table 1] Here, the tolerance of the capacitor is 5%. Furthermore, in the practicable circuit described above, the unit gain frequency ft
Suppose that the sampling frequency fs is measured at 50 kHz and 100 kHz using an operational amplifier OP realized with 50 kHz. Assuming that the above values are given, if we calculate the transfer function, we will obtain the solid line characteristic as shown in Figure 8. In Figure 8,
The horizontal axis shows f/fs, and the vertical axis shows loss.

In Figure 8, the solid line (A) is the ideal characteristic determined by calculation, and the solid line (B) is the sampling frequency f9 of 50
This is the characteristic calculated using kHz, and (C) is the characteristic calculated using the sampling frequency full as 100kHz. Then, the circuit obtained by actually creating the above example is operated at each tempering frequency f3, and the actual measured transfer function is plotted on the solid lines (B) and (C). be. The measured characteristics almost matched the simulation results (transfer function determined by calculation) considering the finite OB product of the operational amplifier OP, and it was confirmed that there was no movement of the transmission zero. Further, FIG. 8 shows the simulation results of the movement of the upper pole of the Z plane with respect to the ratio (ft/fs) of the unit gain frequency rt and the sampling frequency f8. Ratio (ft/f.)=2
When , the ideal pole position (I P , z ,,=
Q, 4 + j 0.2), which is extremely close to the ideal characteristic.

In this way, the effectiveness of the embodiment of the present invention shown in FIG. 1 was demonstrated using the specific circuit of the biquadratic transfer function shown in FIG. That is, M-order coefficient multipliers aQ, a1, . . . aM
The numerator of the transfer function of the above equation (1) is formed by,
And by changing the denominator of the transfer with the coefficient multipliers bl, b2,...+bN, one operational amplifier OP
Since we made addition possible and improved the switched capacitor circuit, we have the following advantages. a) Lower power consumption. This is because the memory and delay functions are realized using switches and capacitors, and there is only one operational amplifier for addition output.

b) Reduction of the presence@OB product of operational amplifier OP. Operational amplifier O
One calculation time of P is executed in the entire sampling period,
This is due to sampling at the end of the sampling period.

Therefore, when the operational amplifier OP operates within one cycle, it is only necessary to reach a value that satisfies the tolerance at the end of the period. ) The zero of the biquadratic transfer function does not shift due to the @GB product of the operational amplifier OP. As shown in equation (22), the zero point is not affected, so
With notch characteristics, there is no change in the frequency of the notch.
Regarding the poles, only the coefficients up to the square of the denominator of equation (1) are affected.

d) It is easy to design, and the capacitance of the capacitor for each coefficient can be calculated extremely easily for the coefficient of the transfer function. ) In general, S of the biquadratic transfer function by two operational amplifiers
C circuits require complex matching calculations in order to effectively utilize each other's dynamic C ranges, whereas the present invention does not require dynamic range matching calculations. It should be noted that although the above-described embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited thereto, and various modifications can be made without departing from the gist of the present invention. For example, in the above embodiment, an IIR type filter was explained, but
Based on a similar idea, FIR (Finite IiDIJ
ISf3 ReSDOnSC! ) type filter. When the above technical idea is applied to this FIR type filter, the second coefficient network BC can be considered to be omitted from the prototype circuit shown in FIG. At this time, the values of the coefficients ao, al l, . . . , a yo take different values. Also, the coefficients aQ, al, . . .
', am should be calculated by the linear phase method instead of using the coefficients according to the transfer function in equation (1) above as they are. According to this circuit, the second coefficient circuit BC is not required, so the number of parts is reduced and the structure is simplified. (Effects of the Invention) As explained above, the first invention has the following effects.

1) A high-speed SC circuit can be realized. In particular, since there is only one operational amplifier, the influence of finite GBm can be minimized. 2) Since only one operational amplifier is used, high-density integrated circuits can be manufactured. 3) Power consumption can be significantly reduced because the operational amplifier, which consumes a large amount of power, is integrated into one. 4) Circuit analysis can be easily performed. Further, according to the second invention, in addition to the effects of the first invention, one coefficient circuit can be omitted, so the number of parts is reduced and the elliptical precept is simplified.

[Brief explanation of drawings]

FIG. 1 shows block 2 showing an embodiment of the present invention. Figures 2 (I) to (V) are circuit diagrams of the first unit block. FIG. 3 is a diagram showing clock pulses that drive the SC circuit of FIG. 1. Figure 4 (I). (II) is an explanatory diagram illustrating a circuit for determining the @GB product of an operational amplifier. FIG. 5 is a diagram for explaining the principle of the present invention. FIG. 6 is a circuit diagram showing a circuit for realizing a biquadratic transfer function. Figure 7 is a diagram showing the clock pulses used in Figure 6. FIG. 8 is a characteristic diagram showing the transfer characteristics of the circuit shown in FIG. 6. Figure 9 is an explanatory diagram of the pole shift of the circuit shown in Figure 6. Figure 10 is a circuit diagram showing the conventional circuit, and Figure 11 is a characteristic diagram showing the characteristics of the conventional circuit. OP... operational amplifier, aQ, a1゜'゜a+i... first unit block, 1+b+, b2, ..., bN... second unit block, AC... first coefficient circuit network, BC ...Second coefficient network, CO...Integration capacitor, X...Input signal, y...Output signal.

Claims (2)

[Claims] (1) A first coefficient circuit configured by arranging a first unit block consisting of a switch capacitor in a matrix, which takes in a signal, delays it by a unit, and multiplies each unit-delayed signal by a predetermined coefficient. a second coefficient circuit configured by arranging in a matrix a second unit block consisting of a network and a switch capacitor that takes in a signal, delays it by a unit, and multiplies each unit-delayed signal by a predetermined coefficient; and input signals to the input terminal through the first coefficient circuit network and calculate them,
an adder that receives an output signal from the output terminal via the second coefficient circuit network to the input terminal and calculates the output signal, and the first coefficient circuit network and the second coefficient circuit network are units arranged in a matrix. The addition column of each coefficient in each row and each column of the block is arranged in a relationship that realizes each coefficient of the transfer function of the entire circuit in each row and each column, and the unit block is configured in a circuit according to the sign of the coefficient, and A switched capacitor circuit characterized in that the switches of the first coefficient circuit network and the second coefficient circuit network are configured to be switched in a predetermined order by clock pulses that are a predetermined number greater than the coefficient. (2) A coefficient circuit network configured by arranging unit blocks consisting of switch capacitors in a matrix, which takes in a signal, delays it by a unit, and multiplies each unit-delayed signal by a predetermined coefficient, and an input an adder that inputs signals to an input terminal through the coefficient circuit network and calculates the signals; In addition to arranging each column in such a manner that each column represents the same, the unit block has a circuit configuration according to the sign of the coefficient, and the switches of the coefficient circuit network are switched in a predetermined order by clock pulses that are a predetermined number more than the coefficient. A switched capacitor circuit characterized in that it has a configuration.