JPS628042B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable multiplier/multiplier circuit that variably divides (multiplies) or multiplies the period of a periodic input signal.

Conventionally, in digital circuits, although frequency division is relatively simple, multiplication requires the use of complex circuits, and variable frequency division and multiplication are even more difficult. Also, in analog circuits, you can obtain double or triple harmonics by utilizing the non-linearity of transistors, or sample the input waveform at a certain period, convert it from analog to digital, and temporarily store it in RAM etc. , the frequency was divided and multiplied by reading it again at a period different from the sample period and performing D-A conversion, but the former required adjustment, and it was not possible to perform high-order multiplication at once; It was nearly impossible to make the rate variable. On the other hand, the latter has a complicated circuit and is uneconomical, and requires a separate filter to select only the waves to be multiplied or frequency-divided from the input signal.

By using an N-way filter, the present invention
The present invention provides a variable multiplier/multiplier circuit which solves the above drawbacks and makes it possible to obtain non-integer multiplier multiplier/multiplier waves having waveforms faithful to the original waveforms without adjustment and at low cost.

The circuit of the present invention is an N-way filter that has the function of a filter to select only the periodic input signal that is desired to be multiplied (or divided) from among the input signals, and the function of storing the input signal voltage for exactly an integer multiple period. , is provided with means for reading out the voltage stored in this N-way filter at a cycle different from the sample clock of the input signal, and the read cycle is set to be M times the sample clock cycle of the input signal (M is a positive real number). This feature is characterized in that multiplication (frequency division) is performed by M times.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an embodiment of the present invention, and FIGS. 2a to 2d are waveform diagrams for explaining the operation of FIG. 1.

In FIG. 1, the variable multiplier/multiplier circuit of the present invention includes an N-way filter section 1, a readout section 2 for reading out the voltage stored in the N-way filter section 1, and a frequency
It consists of a clock signal generator 3 that generates a clock of Cw [Hz] and a clock signal generator 4 that generates a clock of frequency Cr [Hz].
In addition, the N-way filter section 1 has a resistor 11 (resistance value R)
, switches 12 to 15, and capacitors 16 to 1
9 (capacitance value C) and a switch control counter 10 for sequentially turning on the switches 12 to 15 in response to the clock frequency Cw.
It consists of a switch control counter 20 for sequentially turning on the switches 21 to 24 in response to Cr, and a high input impedance amplifier (buffer circuit) 25, which are connected as shown in the figure.

The operation of this circuit will be explained below.

The periodic input signal input from input terminal 5 is connected to resistor 1.
1 to capacitors 16 to 19 in a time-division manner, and the instantaneous value of the input signal is charged and discharged to each capacitor during the allotted time with a time constant determined by C.R. Follow switch 12-15
If the opening/closing period of , that is, the clock frequency Cw and the input signal frequency i are synchronized in a relationship of integral multiples, each instantaneous voltage of the input signal waveform is stored and held in the capacitors 16 to 19.

That is, due to the characteristics of the N-way filter, when it resonates with the input signal, each capacitor 16 to 19 always stores sample voltage values of the input waveform for an integral number of cycles in sequence.

Therefore, if the voltages stored in the capacitors 16 to 19 are read out in the same order as they were input, a waveform similar to the input can be obtained. Therefore, if the switches 21 to 24 are sequentially opened under the control of the counter 20 and the voltage is read out by the amplifier 25 with a high impedance input so as not to affect the memory section, the output terminal 6 will receive a signal similar to the input signal. A waveform is obtained.

The circuit operation of FIG. 1 will be explained in more detail using FIGS. 2a to 2d.

The periodic input signal indicated by the broken line in FIG. 2b is supplied to the N-way filter section 1. In this N-way filter section 1, N (in this case, 10) switches 12 to 15
The output signals S ₁₂ to _{S 15} of the counter 10 (Figure 2 a)
The voltage of the input signal is reduced to N (=
10) The capacitors 16 to 19 sequentially store the memory.

Here, if the relationship Cw=N/m _i (N>2m, m is a positive integer) holds, the same voltage is always maintained in each of the capacitors 16 to 19. That is, the switch 12 is closed by the pulse of the output signal _S12 of the counter 10, and the second
The voltage H ₁₆ in figure b is stored. Similarly, the output signal
Each pulse of S ₁₃ , S ₁₄ , ...S ₁₅ causes a voltage to be applied to capacitors 17, 18, ... 19, respectively.
H ₁₇ , H ₁₈ ,...H ₁₉ are stored. Also, the output signal
Capacitor 1 due to pulses of S ₁₂ , S ₁₃ and S ₁₄
Voltages H ₁₆ ′, H ₁₇ ′,
H ₁₈ ′ is stored. As is clear from FIG. 2a and b, if the above relational expressions hold, the voltages H ₁₆ = H ₁₆ ′, H ₁₇ = H ₁₇ ′, H ₁₈ = H ₁₈ ′,...H ₁₉ =
H ₁₉ ′.

If the above formula does not hold, the capacitor 16
The voltage of ~19 is charged and discharged by R of the resistor 11, and a constant voltage is not maintained. This is clear from the literature mentioned below.

Here, the above equation can be transformed into _i =m/NCw (1).

On the other hand, the frequency ₀ of the output signal of the output terminal 6 is
If formula (1) holds true, capacitors 16 to 19
Since instantaneous voltages of m-period waveforms are stored and held in memory, there is a relationship between Cr and the clock frequency Cr generated by the clock signal generator 4 as follows: ₀ =m/NCr (2).

This equation (2), similar to equation (1), uses the clock Cr, that is, the output signals S ₂₁ to S ₂₄ of the counter 20, to switch the switch 2.
1 to 24 are made conductive in sequence, and capacitors 16 to 19 are
This shows that the voltages H ₁₆ to _{H 19} and H ₁₆ ′ to _{H 18} ′ held at 1 are outputted to the output terminal 6 via the buffer circuit 25.

Therefore, the multiplication (frequency division) rate M becomes M= ₀ / _i =Cr/Cw (3) from equations (1) and (2).

Here, for example, M=2, i.e. Cr=
The waveforms when Cr is selected as 2Cw are shown in Figure 2C and d.

That is, as shown in FIG. 2b, the capacitors 16 to
19 protected voltages H ₁₆ ~ _{H 19} , H ₁₆ ′ ~ _{H 18} ′ are
The output signals S ₂₁ to _{S 24} of the counter 20 are read out at a clock frequency Cr that is twice as high as Cw, and are
A step-like waveform like this is obtained. The broken line in FIG. 2d is obtained by smoothing this stepped waveform. The frequency of the output signal in Fig. 2d is the second
This is twice the input signal frequency in Figure b.

Conversely, if M=1/2, that is, Cr=1/2Cw, the output signal frequency will be 1/2 of the input signal frequency.

Therefore, any M can be obtained by arbitrarily varying C _R .

For details of the N-way filter 1, see Frank et al.'s "An Alternativ Approach to the
Realization o Network Transer
Functions: The N-Path Filter” B.S.
T.J., September 1960, pp. 1321-1350 and Harden, Digital filters with IC's boost Q.
"without inductors" Electronics, July 24, 1967
See pages 91-100.

As described above, according to the present invention, it is possible to provide a multiplier/frequency divider circuit that selects a desired periodic input signal and can easily and inexpensively vary it freely without adjustment. Furthermore, since the N-way filter in particular can pass high-order harmonics, it has the advantage of being able to frequency-multiply and divide digital input signals as well.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of a multiplication circuit according to the present invention, and FIGS. 2a to 2d are waveform diagrams for explaining the operation of the circuit shown in FIG. 1. In the figure, 1... N-way filter, 2... Readout section, 3, 4... Clock signal generator, 5... Input terminal, 6... Output terminal, 10, 20... Counter, 11... Resistor, 12-15, 21-24...
Switch, 16-19... Capacitor, 25...
It is a buffer amplifier.

Claims (1)

[Claims] 1. A first means for generating a first clock signal having a frequency N times the frequency of the input signal (N is a natural number), and a first means for generating a first clock signal having a frequency N times the frequency of the input signal (N is a natural number); a second means for generating a second clock signal having a different frequency from the first clock signal;
and third means for sequentially reading out the stored voltages using a clock signal, and the input signal is divided or multiplied by varying the frequency of the second clock signal. Variable multiplier circuit using filters. 2. The N-way filter is composed of a resistor, a plurality of capacitors, and a plurality of first switches each provided between the resistor and the capacitor and cyclically and sequentially opened and closed by the first clock signal. A variable multiplier circuit using an N-way filter according to claim 1. 3. The third means is connected to a plurality of second switches each connected to the plurality of capacitors and cyclically and sequentially opened and closed by the second clock signal, and to an output of the plurality of second switches. 3. A variable multiplier circuit using an N-way filter according to claim 2, characterized in that the circuit comprises an output buffer circuit having an output buffer circuit.