JPH03201617A - Analog variable delay - Google Patents

Abstract

PURPOSE:To realize the change of a delay time without causing the fluctuation of a passing frequency band by controlling the read of a capacitor array to successively store the outputs of an input amplifier. CONSTITUTION:A capacitor array 2 is provided to successively store the outputs of an input amplifier 1, and a write switch group 3 is provided to control write to the respective capacitors of the capacitor array 2. Then, a read switch group 4 is provided to control the read of signals written from the respective capacitors. Namely, input analog signals are not successively serially transferred but successively stored into the capacitor array 2 and the stored signals are successively read out from this capacitor array 2. By controlling timing to read the signals, the delay time is made variable. Thus, since the delay time can be made variable without changing clocks different from sequential serial transfer type delay, the passing frequency band is not fluctuated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog signal delay capable of varying the delay time required for audio equipment and the like.

[Conventional technology]

Conventionally, BB is used as a delay circuit that delays analog signals.
By connecting charge transfer devices such as D and COD in multiple stages,
There was a configuration in which signals were transferred serially and delayed by one hour.

The delay operation using BBD will be explained below.

As shown in Figure 2, BBDs are constructed by arranging a series of capacitors called packets (pn junction capacitance between the collector paces in the case of bipolar BBDs, MO8 capacitance with the date electrode in the case of MO8 type BBDs), and forming capacitors called packets. It has a structure in which the capacitors are connected by non-polar type or MOS type transistors, and the switches are controlled by external clocks φ1 and φ2, and the charge is transferred from one capacitor to the adjacent capacitor. It is configured to delay the analog signal.

[Problem to be solved by the invention]

In conventional delay circuits using charge transfer devices as described above, variable delay time depends on changing the clock frequency.
There was a problem in that it was accompanied by fluctuations in the pass frequency band.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an analog variable delay that can vary the delay time without changing the pass frequency band.

[Means to solve the problem]

The analog variable delay of the present invention transfers input analog signals sequentially in series. This configuration allows the delay time to be varied by controlling the read timing.

[Effect]

With this configuration, the conventional BBD.

Unlike a serial transfer type delay using a CCD, the delay time can be varied without changing the clock, so the passing frequency band does not fluctuate.

〔Example〕

FIG. 1 shows an embodiment of the invention.

In the figure, 1 is an input amplifier that amplifies the input analog signal, 2 is a capacitor array that sequentially stores the output of the input amplifier 1, and 3 is a capacitor array that controls writing to each capacitor in the capacitor array 2. A group of connected write switches, 4 a read switch group connected to each capacitor that controls reading of the written signal from each capacitor of the capacitor array 2, 5 an output amplifier that amplifies the signal read from the capacitor array 2, and 6 a By controlling the write switch group 3, the output of the input amplifier 1 is sequentially transferred to each capacitor J? of the capacitor array 2. 7 is a second shift register that controls the readout switch group 4 to sequentially read out the written signals from each capacitor of the capacitor array 2;
8 is a first shift register 6 and a second shift register 7
This is a shift control that controls the timing of

The input analog signal is separated and amplified by the input amplifier 1 so that the charging of the capacitor array 2 is not influenced by previous circuits.

The amplified signal is sequentially written into each capacitor of the capacitor array 2 via a group of write switches 3 which are sequentially opened and closed under the control of the first shift register 6.

After the timing set in shift control 8, the second
The readout switch group 4 is sequentially opened and closed under the control of the shift register 7, and the signals written in each capacitor of the capacitor array 2 are sequentially read out.

The read signal is sent to the output amplifier 5, and is separated from the subsequent circuit so that the capacitor array 2 is not affected.
It is amplified and output.

When changing the delay time, the setting timing of the shift control 8 is changed to change the read timing.

Therefore, changing the delay time does not involve changing the pass frequency band.

〔Effect of the invention〕

As described above, according to the present invention, the delay time can be changed without changing the pass frequency band, and the practical effects are great.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the operation of an example of an analog delay using a conventional BBD. 1...Input amplifier, 2...Capacitor array%3.
-Write switch group, 4...Read switch group. 5... Output amplifier, 6... First shift register,
7... Second shift register, 8... Shift control O

Claims (1)

[Claims] An input amplifier that amplifies an input analog signal, a capacitor array that sequentially stores the output of the input amplifier, a group of write switches connected to each capacitor that controls writing to each capacitor in the capacitor array, and the capacitor array. a group of read switches connected to each capacitor that controls reading from each capacitor of the capacitor array, an output amplifier that amplifies and outputs the signal read from each capacitor of the capacitor array, and an output amplifier that controls the write switch group and connects to the input amplifier. a first shift register that sequentially writes the output of the above to each capacitor of the capacitor array; a second shift register that controls the readout switch group to sequentially read the written signal from each capacitor of the capacitor array; An analog variable delay comprising a shift control for controlling the timing of the first shift register and the second shift register.