JPS6292512A - Variable coefficient circuit - Google Patents

Abstract

PURPOSE:To vary easily an input/output voltage coefficient by a switched capacitor by controlling the number of transmission and the sampling of an input voltage by capacitors different from the capacitance ratio via a switch for varying the control speed. CONSTITUTION:An input voltage from a terminal 98 is sampled by a switched capacitor comprising switches 11, 12, 21, 31, 41, 32, 42 and capacitors 111, 122 of different capacitances and the result is fed to an inverting input terminal 97 of an operational amplifier 97. Then an output voltage is generated from a terminal 99 via an integration capacitor 100 brought into the initial state by switches 01, 02 and a capacitor 101. The operating speed of the switches 11, 12, 21, 22, 31, 32, 41, 42 applying input/output control of the capacitors 111, 122 is controlled within the operating period of the switches 01, 02 to change the switching number of times, then the output voltage is changed and the switched capacitor is used to apply fine adjustment of the input/output voltage coefficient having the input/output voltage ratio easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention J] The present invention relates to a variable coefficient circuit using a switched capacitor circuit suitable for IC and LSI implementation.

[Background of the invention]

The conventional variable coefficient circuit using switched capacitors is
Journal of the Institute of Electronics and Communication Engineers '84/8 Vol, J67-B
/16a As described in the paper entitled "Automatic filter using switched capacitors", it is possible to design a wide variable range of coefficients, but if high-precision coefficients are required, switching Because it is necessary to operate at even higher speeds, the area on the chip for switch drive circuits and switch circuits (transistors, etc.) becomes larger.
This method is not economical and requires a high-speed device to sample the sample-and-hold input signal at a higher frequency.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a variable coefficient circuit in which coefficient values can be finely adjusted using switched capacitors.

[Summary of the invention]

To achieve this objective, the present invention samples the input signal voltage across a plurality of capacitors with different capacitance ratios and adds them together by switching them individually.
This process is performed multiple times within the hold period of the input signal voltage, and by controlling the number of times this sampling and accumulation is performed, it is possible to finely adjust the coefficient using a switched capacitor.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a variable coefficient circuit according to the present invention, and shows 01.02, 11.12, 21.22, 31.52, 41.42. are the switches and 1 respectively.
00, 101° 111.122 are capacitors, respectively.
97 is an amplifier, 98 is a signal input terminal, and 99 is an output terminal.

2 is a time chart showing the waveforms of each part and the operating state of each switch shown in FIG. 1, and (a) is a time chart showing the input terminal 9.
8, (b) is the voltage waveform appearing at the output terminal 99, (C) is the state of change in the charge being charged and discharged to the capacitor 100, (d) is the state of change in the charge being charged and discharged by the capacitor 101, (e) shows the changing state of charge charged and discharged in the capacitor 111, and (f) shows the state of change in the charge charged and discharged in the capacitor 122.
(g) is the state of change in charge being charged and discharged in switch 01.
(h) is the operating state of switch 02; i) is the operating state of switches 11 and 12; (j) is the operating state of switch 21.
．． 22, (k) is the operating state of switches 31 and 32, (k) is the operating state of switches 41 and 42, and T is the operating period of switches 01 and 02, G, H, L.
, , L , Kl , 2 , Ks , Lt , L2゜L, , , , , L , , , , , , L, 2
each indicates the phase in which the switch becomes conductive. 1
．． , 12 indicate time.

This embodiment uses a switched capacitor, and first, the operation of each element in FIG. 1 will be briefly explained.

In the figure, a capacitor 100 is an integral capacitor connected between the input and output terminals of an amplifier 97, and the input and output of a capacitor 101 is controlled by switches 01 and 02, and the charge of the capacitor 100 is canceled at a constant period T. Capacitor 111 Switch 11, 12, 21.2
2, the capacitor 122 is connected to the switches 3j, 32,
The input and output are controlled by 41 and 42, respectively, and the input terminal 9
After sampling the signal a input to the amplifier 8 and accumulating the charge, this charge is transferred to the inverting input terminal of the amplifier 970. Switch 11.12, 21.22, 31.32, 41
．． 42 is synchronized with the operating cycle of the switches 01 and 02, and calculates the coefficient value of the coefficient circuit according to the number of on/off operations within one cycle of this operation, that is, the number of samplings of the input signal a to the capacitors 111 and 122 and the number of charge transfers. decide.

Next, the operation of this embodiment will be explained in detail.

In FIG. 1, the capacitance value of the capacitor 100 is C1oo
+The capacitance value of the capacitor 101 is C, the capacitance value of the o1p capacitor 111 is C111, and the capacitance value of the capacitor 122 is 0122. Here, in order to explain the operation in an easy-to-understand manner, the respective capacitance values are set as follows. In this embodiment, the variable range of the coefficient is 1 to 57 times, which is the minimum variation τ of the coefficient.

・61 FIG. 2 shows the waveforms of each part and the timing chart of each switch when this coefficient value is multiplied by 1T or I. In the same figure, the coefficient value between time t1 and time 3 t2 is 1T times 2. After time t2, the coefficient value φ is
It is 1 or 1 times larger. First, the operation of each part from time t1 to time t2 will be explained.

First, in phase G, switch 01 is closed and capacitor 101 is connected to the voltage (b) at output terminal 99 of amplifier 97.
) value V? A charge Q+o1 corresponding to 9 is accumulated through the switch 01. At this time, the output voltage of the amplifier 97 is a value V? proportional to the charge Q+oo of the capacitor 100? ? It is. Then, in phase H, switch 01 is open and switch 02 is closed, capacitor 101 is connected from output terminal 99 to input terminal 97, and charge Q of capacitor 100 is
Cancel 1oo. Here, C+oo "" C
+ot, so capacitor 100 and capacitor 10
The sum of charges of 1 is Q+oo +Q. ,=0. The capacitor 101 repeatedly performs the above operation at regular intervals by the switch 0102.

Capacitor 111 connects input terminal 9 with phase 11 and phase J1.
After sampling the voltage (a) of the direct La input to the amplifier 97, the sampled voltage value V? Charge Q11 corresponding to 8
．． is transferred to the capacitor 100 and stored therein.

Similarly, 1 in phase, 2 in phase L19, 2 in phase
With two phases and three positions AFLs, the capacitor 122 samples the voltage (a) of the value Vf@ input to the input terminal 98, and then converts this sampled voltage value v? The operation of transferring the charge QI22 corresponding to 8 to the capacitor 100 is repeated six times. With this fabrication, the capacitor 100 stores a charge of 15×Q122. At the next phase GK after the sampling and transfer operations by these capacitors 111 and 122 are completed, the output terminal 9
If the signal is taken out from 9, the value of input signal voltage (a) is V9
An output signal voltage (b) of a value V99 which is 1τ times m is obtained. If the charge of the capacitor 100 at this time is Qlao, -Q+no=Q1oo+Qyo+-Qul-3
It becomes Qtzz. This also means -CjOOV↓t = -C+ooVpp + C+o
It is expressed as 1Vu -C+n*pszuC+22Vta. Therefore, capacitor 100°101.111,1
Since the capacitance value of 22 has a relationship as shown in equation (1), Lp=1TV9g (2). That is, this indicates that the signal voltage (a) input to the input terminal 98 is multiplied by 1i and output to the output terminal 99.

Even after time t2, the above-mentioned time t1 and time t2
Perform the same operation as before.

That is, the capacitor 100 has a phase of 11 and a phase of L.
12 to 112 phase and capacitor 12202 at phase L12
The double charge 2XQ112 and the charge Q+a+ of the capacitor 101 in phase G and phase H are accumulated. capacitor 100
The initial charge Q+'oa, the input voltage at that time (a)
The value of V9@1 y is the next phase G after these operations are completed.
If the value of the voltage (b) appearing at the output terminal 99 is v991, then the following equation appears corresponding to the above equation (2): 0 -C100V? ? 1 = 'J product + Q, :o12Q;
22 From the relationship of equation (1), the above equation is V, , =-5-V9. , ・・・・・・・・・(3
), which indicates that the signal voltage (a) input to the input terminal 98 is multiplied by seven and output to the output terminal 99.

The case of two types of coefficient values has been explained above, but the coefficient value in this embodiment is determined by controlling the number of sampling and transfer of each of the capacitors 111 and 122 within the operation period T of the switches 01 and 02. It is clear that it can be varied. In addition, a switch 11 for controlling input/output of these capacitors 111°1220
, 12, 21° 22.61.32, 41.42 can easily be controlled by a logic circuit.

According to this embodiment, a variable coefficient circuit can be constructed in which the minimum variable amount is an upper arithmetic progression within the coefficient variable range of 1 to 7 times based on the switched capacitor.

FIG. 6 is a circuit diagram showing another embodiment of the variable coefficient circuit according to the present invention, in which 51, 61, 71, 81 are switches, 133, 144 are capacitors,
Parts corresponding to those in FIG. 1 are given the same reference numerals.

In the embodiment shown in FIG.
, 122 are connected to the amplifier by changing the polarity of the capacitors 111 and 122, but in this embodiment, the capacitors 111 and 122 are connected to the input terminal of the amplifier 970 without changing the polarity, and the other operations are as shown in FIG. This is similar to the example.

Moreover, FIG. 4 shows the waveforms of each part shown in FIG.

This is a time chart showing the operating status of each switch.
a) is a voltage waveform input to the input terminal 98;

(b) is the voltage waveform appearing at the output terminal 99, (C) is the change state of the charge charged and discharged in the capacitor 100, (d)
is the change state of the charge charged and discharged in the capacitor 101, (
e) shows the state of change in the charges charged and discharged to the capacitor 133, (f) shows the state of change in the charge charged and discharged to the capacitor 144, and (g) shows the operating state of the switch 01.

(h) is the operating state of switch 02, (i) is switch 5
1, (j) is the operating state of switch 61, (k
) indicates the operating state of the switch 71, and (1) indicates the operating state of the switch 81. In addition, in the same figure) v (h) −(
') t (J) - (k), <l) To make the explanation easier to understand, the operation of each switch is as shown in the time chart of each switch (g), (h), (
It is the same as i), U), (k), and (A').

The operation of this embodiment is similar to that of the embodiment shown in FIG. Therefore, between time t1 and time t2, capacitor 100 has charges Q+ss of capacitor CLSM in phase 1 and phase J2, and charges Q+ss in phase 1 and phase L+.
, 2 in phase and phase L22 5 in phase and 3 times charge in phase L3 3Q144 of capacitor C144, phase G and phase H
The charge Q+a+ of the capacitor 101 is accumulated. Qloa is the initial charge of the capacitor 100.

Set the value of input voltage (a) to v98. If the output voltage is V99, then C+oaVpt = -Qlao + (J+ot +Qt
ii + 3Q144 --- The relationship (4) holds true. Here, equation (4) becomes V! ! = -1-Base-vt@・・・・・・
...(6). This indicates that the signal voltage (a) input to the input terminal 99 should be outputted to the output terminal 99 with the polarity inverted and multiplied by 1-7 with respect to the input signal.

Moreover, after time t2, the capacitor 100 has a phase X
++ and phase L112 phase 12 and phase L+2 twice the charge 2Q of capacitor 144? 44, the charge Qio+ of the capacitor 101 is accumulated in phase G and phase H.

The initial charge of the capacitor 100, Q:co, and the input voltage (
Set the value of a) to V9111. Output voltage V? ? If it is 1,
Corresponding to the above equation (2), 1010υV? ? 1 =-Q:oO+ Qla+ +
2Q? 44, and from the relationship in equation (5), the above equation becomes L?
+=-Upward V96°. This is the signal voltage (
A) indicates that the input signal voltage is inverted and multiplied by 1 and output to the output terminal 99.

The case of two types of coefficient values has been described above, but the coefficient values of this embodiment are used to control the number of times of sampling and transfer of each of the capacitor 155 and the capacitor 144 within the operating cycle T of the switch 01.02. According to
It is clear that it can be changed. Also, a switch 51 for controlling the input and output of these capacitors 133 and 1440.
61, 71.

It is clear that the control of 81.91 can be easily realized using logic circuits.

According to this example, the coefficient variable range depending on the switched capacitor is 15 times, and the minimum value is 7 times to 3-2 times.
1. It is possible to construct a variable coefficient circuit in which the polarity of the output signal is inverted with respect to the input signal using a variable amount or T arithmetic progression.

FIG. 5 is a circuit diagram showing still another embodiment of the variable coefficient circuit according to the present invention. In this embodiment, parts corresponding to FIGS. 1 and 6 are given the same reference numerals. The charges obtained by sampling by the capacitor 111 and the capacitor 144 are input to the inverting input terminal of the amplifier 970 with different polarities, and the operation thereof is the same as in each of the embodiments described above.

Moreover, FIG. 6 is a time chart showing the waveforms of each part and the operating state of each switch shown in FIG. 5, and (a) shows the voltage waveform input to the input terminal 99.

(b) is the voltage waveform appearing at the output terminal 99, (C) is the change state of the charge charged and discharged in the capacitor 100, (d)
is the change state of the charge charged and discharged in the capacitor 101, (
e) shows the state of change in the charges charged and discharged to the capacitor 111, (f) shows the state of change in the charge charged and discharged to the capacitor 144, and (g) shows the operating state of the switch 01.

(h) is the operation K d of switch 02, (i> is the production record M of switch 11゜12, (j) is the switch 21.2
2 operating conditions.

(k) is the operating state of switch 71, (1) is switch 8
1 shows the operating state. billion), (h), (i)
, U), (k), and (1) are shown in (g) in Fig. 2 for ease of explanation.
), (h), (i), (j), (k)
, is the same as (A').

Therefore, between time t1 and time t2, capacitor 1
00 has the charge Q111 of the capacitor 111 in the phase 11 and the phase J1, the phase 1 and the phase Ll, the phase 2 and the phase L
2, in phase with the phase Ks, the charge 3Q+44 is three times that of the capacitor 144, and the capacitor 101 is in phase G and H.
A charge Q+o+ is accumulated. If the initial charge of the capacitor 100 is Qtoa and the value of the input voltage (a) is VtS, the value of the output voltage (b) V99 is -C+0fIV? ?
= −Q+ oo +Q1o+ −Q+ ++
+ 3 Qlaa --- The relationship (7) holds true. Here, if , equation (7) becomes ■9? =÷V98. This is the signal voltage (a
) is multiplied by seven and output to the output terminal 99.

Furthermore, after time t2, the capacitor 100 has a charge Q; 44 which is twice as much as the capacitor 14402 in phase 11, phase L112, 12 in phase IJ-12, and charge Q crystal of capacitor 101 in phase G and phase H. Accumulated.

If the initial charge of the capacitor ILIO is 'Joo' and the value of the input voltage (a) is v9-1, the output voltage Vtt+ is
-C+ooVtu=Q3QO+Q product+2Q144, and from the relationship in equation (8), the above equation becomes v9? , knee 2N'
? It becomes 81. This is the signal voltage (
a) indicates that the input signal (a) is outputted to the output terminal 99 with its polarity inverted and multiplied. that's all,
An explanation was given for two types of coefficients.

It is clear that the thread value in this embodiment can be varied by controlling the number of times of sampling and transfer of the capacitors 111 and 144, respectively, within the operation cycle T of the switches 04 and 02.

In addition, switches 11.12, 2j, 22, 71.81 control input and output of these capacitors 111, 144.
It is clear that control of can be easily realized using a logic circuit.0 According to this embodiment, the coefficient variable range by the switched capacitor is from -÷ times to 3 times, and the input signal is determined by the minimum variable amount or τ arithmetic progression. Therefore, it is possible to construct a variable coefficient circuit that can also control the polarity of the output signal.

〔Effect of the invention〕

As explained above, according to the present invention, the variable coefficient circuit using switched capacitors is advantageous in IC implementation, and highly accurate coefficients can be realized with low speed operation.
An excellent effect can be obtained in that the area on a chip such as a switch circuit and a switch drive circuit can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the variable coefficient circuit according to the present invention, FIG. 2 is a time chart showing the waveforms of each part and the operating state of each switch in FIG. 1, and FIG. 3 is a variable coefficient circuit according to the present invention. A circuit diagram showing another embodiment of the circuit, FIG. 4 is a time chart showing the signal waveform of each part and the operating state of each switch in FIG. 5, and FIG. 5 is a still another embodiment of the variable coefficient circuit according to the present invention. The circuit diagram shown in Figure 6 is
5 is a timing chart showing signal waveforms of each part in the figure and operating states of switches. 01.02, 11, 12, 21, 22, 31, 32, 4
1,42,51,61,71,81...Switch, 97...Amplifier, 100,111,122゜133.144...Capacitor. /7・Go. “,

Claims (1)

[Claims] an amplifier, a first capacitor connected between the inverting input terminal and the output terminal of the amplifier, one end of which is alternately connected to the inverting input terminal and the output terminal of the amplifier by a switch circuit, and the other end of which is grounded; a plurality of capacitors for accumulating a signal from a signal input terminal and transferring the accumulated signal to an inverting input terminal of the amplifier;
switch means for controlling the alternating connection of the signal input terminal at one end of the second capacitor and the inverting input terminal of the amplifier in order to cause the plurality of capacitors to store and transfer signals; By making the control speed of the switching means variable, the coefficient value between the input signal voltage supplied to the signal input terminal and the output signal voltage obtained at the output terminal can be made variable. A variable coefficient circuit characterized by: