JPH0320078A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain large-capacity, highly-integrated, high-reliability memories by making capacitors, piling up plate electrodes into a columnlike shape on both the upper and lower parts of MOS transistors. CONSTITUTION:An N-type diffusion layer 4 is formed by ion implantation with a poly-silicon gate (word line) 3, as a mask, provided through the medium of a gate oxide film 2 on a P-type conductivity semiconductor substrate 1. After that, second plates 6 made of conductors are piled up into a columnlike shape on the upper part of the poly-silicon gate 3 through the medium of a capacity insulating film 10. In addition, the first plate 5 made of a conductor is made so as to be kept contact with one side of the N-type diffusion layer 4 through the medium of the second plates 6 and capacity insulating film 10, and they make a capacitor. Accordingly, charges are stored on every side of the plate electrodes that store charges, and a wide area is not necessary. This makes it possible to obtain a large-capacity, highly-integrated and highly-reliable storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a MOS field effect transistor in which capacitors are provided in the upper and lower parts of the transistor in the form of a column or ring.
Conventional technology, particularly related to semiconductor memory devices with large storage capacity and good area efficiency.Conventional technology: In order to obtain semiconductor memory devices with high capacity, plate electrodes and insulating films are alternately stacked on top of a semiconductor substrate. Trench-type semiconductor memory devices are being researched and developed, in which a trench is dug and a plate electrode is buried through an insulating film.A diffusion layer is formed on the sides of the trench to form a capacitor.

Problems to be Solved by the Invention Method for forming a capacitor in which plate electrodes and insulating films are stacked alternately in a plane in a stacked semiconductor memory device (Part 1) Although the number of manufacturing steps is large and control is difficult, it is also A method of forming capacitors in memory devices by simply digging a groove in the semiconductor substrate and burying the plate (
In order to obtain a large capacity, it is necessary to reduce the area occupied by the upper surface of the groove on the mask, which is susceptible to the effects of crystal defects within the groove.The present invention was made in view of the above-mentioned problems, and the manufacturing process It is an object of the present invention to provide a highly reliable semiconductor memory device with a high degree of integration and a large capacity. Advantages of iMOs transistors Works well in semiconductor memory devices where plate electrodes are piled up in a columnar manner to form a capacitor on both the upper and lower parts of the lower body.The present invention uses the above-mentioned approach to provide plate electrodes and an insulating film in a columnar manner. As a result, charges are accumulated on all sides of the plate electrode that accumulates capacitance, and a highly reliable semiconductor memory device with large capacity and high integration can be obtained without requiring a large area. a) (t) A resistive polysilicon gate in which an n-type diffusion layer 4 is formed by ion implantation using a polysilicon gate (word line) 3 provided on a P-type conductivity type semiconductor substrate 1 via a gate oxide film 2 as a mask. A second plate 6 made of a conductor is stacked on top of the capacitive insulating film 10 in a columnar manner on top of the capacitive insulating film 10. A polysilicon electrode 8 is formed to be in contact with one side of the type diffusion layer 4 and to be in contact with the other side of the capacitor and the Ln type diffusion layer 4. Even if an insulating layer 7 is provided to insulate the first plate 5 and the polysilicon electrode 8, FIG. 1(b)
is a cross-turn diagram of FIG. 1(a) viewed from above. In addition, lla and llb are the first contact between the diffusion layer 4 and the polysilicon electrode, and the second contact between the diffusion layer 4 and the first plate 5, respectively 7). , FIG. 2(a) shows a polysilicon gate (word line) 3a and a polysilicon gate (dummy word line) 3b provided on a P-type conductivity type semiconductor substrate 1 via a gate oxide film 2 as a mask. After forming the n-type diffusion layer 4 by ion implantation, an insulating film 10 is formed on top of the polysilicon gates 3a and 3b.
A plurality of ring-shaped second plates 6 made of conductors are connected to each other through the conductor.
1, and furthermore, the first plate 5 made of a conductor is arranged in a circular column shape through the second plate 6 and the capacitive insulating film lO, and
A polysilicon electrode 8 is formed so as to be in contact with one side of the H-type diffusion layer 4 to contact the other side of the capacitor and LA n-type diffusion layer 4, and is in contact with an aluminum electrode (bit line) 9. Aluminum electrode 9 and first plate 5
, even if an insulating layer 7 is provided for insulation from the polysilicon electrode 8.
Even though it is a cross-sectional view when cut horizontally along a line, Figure 3 shows a groove extending from the top of the P-type conductivity type semiconductor substrate 1 in a direction perpendicular to the substrate 1! 6 is dug, and a fourth conductor is formed on the inner side wall portion of groove l6.
A third plate 12 made of a conductor is embedded in the groove 16 via a capacitive insulating film 14. Further, an epitaxial layer 15 of the same conductivity type as the substrate 1 is provided on the upper part of the substrate. , by ion implantation using the polysilicon gate (word line) 3 provided on the epitaxial layer l5 via the gate oxide film 2 as a mask, the n-type second diffusion layer 4a and the n-type second layer in contact with the fourth plate 13 are formed. A diffusion layer 4b is formed, and a second plate 6 made of a conductor is stacked in a columnar manner on top of the polysilicon gate 3 via a capacitive insulating film 10, and then the second plate 6 and the capacitive insulating film lO
A capacitor is formed on both the bottom and top of the substrate 1 by bringing the first plate 5 made of a conductor into contact with the n-type second diffusion layer 4b through the Ln-type diffusion layer 4a. (Na, it is also possible to make contact with the aluminum electrode (bit line) 9 and provide an insulating layer 7 between the aluminum electrode 9, the first plate 5, and the polysilicon electrode 8. A groove 16 is dug in a direction perpendicular to the substrate 1 from above the conductivity type semiconductor substrate l, and a plurality of ring-shaped fourth plate electrodes l3 are formed from the center of the groove l6.
A third plate electrode 12 is provided via a capacitive insulating film l4 so as to surround the fourth plate electrode 13, and an epitaxial layer 15 of the same conductivity type as the substrate l is further provided. Polysilicon gate (word line) 3a and 3a provided through gate oxide film 2 Polysilicon gate (dummy word line) 3
An n-type diffusion layer 4a is formed by ion implantation using b as a mask,
N-type second diffusion layer 4 in contact with fourth plate l3
An aluminum electrode (bit line) 9 is provided in contact with the Ln-type diffusion layer 4a forming the aluminum electrode 9. A horizontal cut of FIG. 4 along line b-b' (above) As shown in FIG. By forming a capacitor by forming a plate electrode and an insulating film in the shape of a column or ring on the top and bottom of a silicon gate electrode, an extremely large amount of charge can be stored. This is to prevent hot carrier deterioration by increasing the length of time.

[Brief explanation of the drawing]

FIG. 1(a) shows a cross section of a semiconductor memory device according to an embodiment of the present invention, and FIG. 1(b) shows its pattern.
a) is a cross section of a semiconductor memory device in another embodiment; FIG. 2(b) is a horizontal cross section of FIG. 2(a); FIG. 4 is a cross section of a semiconductor memory device in another embodiment. In the figure, L...Semiconductor base K2...Gate oxidation lit
3, 3a...Polysilicon gate, 3b...
Dummy polysilicon gate, 4, 4a...diffusion screen
4b...Second diffuser 5...First plate,
6...Second plate, 7...Insulating screen 8...
・・Polysilicon electric maple 9・・・・Aluminum electric 1i 1
0.14...Capacitive insulation Ill 12...3rd
plate, 13... Fourth plate, l5...
・Epitaxial 凰 l6・・・・Otori

Claims (4)

[Claims] (1) A columnar second plate electrode is in contact with the diffusion layer of the MOS transistor through an insulating film above the gate electrode of the MOS transistor formed on the semiconductor substrate;
A semiconductor memory device comprising a capacitor including a first plate electrode interposed between the second plate electrode and a capacitive insulating film. (2) A ring-shaped second plate electrode is in contact with the diffusion layer of the MOS transistor on the top of the MOS transistor formed on the semiconductor substrate via an insulating film, and the second plate electrode is in contact with the diffusion layer of the MOS transistor.
A semiconductor memory device comprising a capacitor including a first plate electrode interposed by a capacitive insulating film surrounding the plate electrode. (3) a groove formed in a first conductive type semiconductor substrate; a fourth plate electrode formed on an inner side wall portion of the groove;
A MOS transistor is formed in a first capacitor including a third plate electrode interposed between the fourth plate electrode and a first capacitive insulating film, and a first conductivity type epitaxial layer formed in the upper part of the groove. , the gate electrode of the MOS transistor is in contact with a diffusion layer of the MOS transistor which is in contact with a portion of the second plate electrode and a part of the fourth plate electrode via an insulating film; A semiconductor memory device comprising a second capacitor including a first plate electrode and a second insulating film interposed therebetween. (4) A ring-shaped fourth plate electrode formed in the center of the groove formed in the first conductivity type semiconductor substrate, and a fourth plate electrode formed in the center of the groove formed in the first conductive type semiconductor substrate, and a fourth plate electrode formed in the first conductivity type semiconductor substrate, and A MOS transistor is formed in a first conductivity type epitaxial layer formed in the upper part of the groove, and a diffusion layer of the MOS transistor and the fourth plate electrode are in contact with each other. A semiconductor memory device characterized by: