JPH03200340A - Field effect transistor - Google Patents

Abstract

PURPOSE:To increase the effective thickness of a channel layer while restraining the effect of a lattice mismatch by intervening a second channel layer wherein a composition is gradually changed so that the lattice mismatch causes no problem between a buffer layer and the channel layer. CONSTITUTION:Between a buffer layer 12 and a first channel layer 14 composed of mixed crystal semiconductor, intervenes a second channel layer 13 composed of the mixed crystal semiconductor wherein a composition is gradually changed so as to lattice-match the buffer layer 12 in a portion in contact with the buffer layer 12 and lattice-match the first channel layer 14 in a portion in contact with the first channel layer 14. Thus, even when a material which poorly lattice- matches the first channel layer 14 and the buffer layer 12 and from which only a small layer thickness can be taken for preventing a misfit dislocation from being generated is used for the first channel layer 14, by using the second channel layer 13, a channel layer as a whole can attain a large thickness while restraining the effect of a lattice mismatch.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to integrated circuits (IC) and large-scale integrated circuits (LS).
Field-effect transistors (FETs) used as components of I), in particular selectively doped FETs with a channel layer with lattice mismatch.

[Conventional technology]

Conventionally, in FETs used in ICs and LSIs, InGaAs mixed crystal x mixed crystal 1-
A selectively doped FET with x as the channel layer has been proposed, but in order to achieve high-speed operation in the − layer, InGa
The composition of the As mixed crystal is originally 1nP group x l
-x From x-0,53, which is the condition for lattice matching to the plate,
Attempts have been made to increase the electron mobility and saturation velocity of electrons by shifting the composition to a higher In content (for example, Journal of'Crystal Growth).
tal Growth), vol. 95, p. 189, 19
1989).

FIG. 2 shows an example of such a structure. In the same figure, an I
Buffer layer 2 made of nAlAs, channel layer 3 made of InGaAs, and x l-X +: InAllAs layer 4A doped with St, undoped InANAs layer 4B, and In doped with Sl.
A cap layer 4 made of a GaAs layer 4C is formed.

[Problem to be solved by the invention]

However, when using a channel layer made of InGa1-1As mixed crystal and having an In composition As the In composition increases, the lattice mismatch with respect to (matched) increases. Therefore, in order to obtain good electrical characteristics, the thickness of the channel layer must be set to such a level that the crystal lattice is deformed within the elastic limit and that misfit dislocations do not occur (approximately 150 A or less at X -0,75). It is necessary to keep it to

However, when the channel layer 3 is made so thin, the influence of unevenness at the atomic layer level at the interfaces between the channel layer 3 and the buffer layer 2 and between the channel layer 3 and the cap layer 4 on the electrical characteristics of the FET can be ignored. It disappears. That is, as the channel layer 2 becomes thinner, electrons traveling through the channel layer 2 experience potential disturbance due to the unevenness of the interface, and the electrical characteristics of the FET, particularly the electron mobility, deteriorate.

[Means to solve the problem]

In this invention, between a buffer layer and a channel layer (first channel layer) made of a mixed crystal semiconductor, the portion in contact with the buffer layer is substantially lattice matched to the buffer layer, and the portion in contact with the first channel layer is A second channel layer made of a mixed crystal semiconductor whose composition is gradually changed so as to be substantially lattice-matched to the first channel layer is interposed therebetween. This change in composition may be stepwise or continuous (gradient).

Note that the buffer layer and the second channel layer are
The lattice matching Δa/a of the channel layer is preferably 0.5% or less.

[Effect]

Even if the first channel layer is made of a material that has poor lattice matching with the buffer layer, and therefore can only be made extremely thin to prevent the occurrence of misfit dislocations, the second channel layer cannot be used. Therefore, the thickness of the entire channel layer can be increased while suppressing the influence of lattice mismatch.

For example, A II o, 481 no, 52A
When forming an In Ga As mixed crystal channel layer on the S buffer layer, the maximum layer x 1-x is about 1508 as mentioned above, but the layer with less In is a little more. It can be loaded. Therefore, with less In, Al7 1
n As buffer layer well lattice 0.48 0.
52. Insert a second channel layer whose composition is gradually shifted from a matching composition to a composition close to the first channel layer containing a large amount of In so that lattice mismatch does not become a problem. At this time, the second channel layer also contributes to the movement of electrons, although less than the first channel layer, and the first and second channel layers combined function as an effective channel layer.

As a result of the increased thickness of the channel layer as a whole, it becomes difficult to perceive disturbances in the potential due to the unevenness of the interface as a whole.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1(a) and 1(b) of the accompanying drawings.

FIG. 5A is a cross-sectional view showing the schematic structure of the FET of this example. Note that the scale of each part is not accurate.

In the figure, a second channel layer 13, a first channel layer 14, and a cab layer 15 are sequentially stacked on a semi-insulating semiconductor substrate 11 via a buffer layer 12 by molecular beam epitaxial growth. A Schottky gate electrode 16 and a source electrode 17 and a drain electrode 18 are formed separately therefrom.

The substrate 11 is made of InP doped with iron (Fe 2 ). The buffer layer 12 is made of AN 1 n As, which is lattice matched to the InP substrate, to prevent the adverse effects from directly affecting the channel layer even if the surface of the substrate 11 has poor crystallinity or has many impurities. ~0 mixed crystal
．． It is formed to have a thickness of 0.48 to 0.52 and a thickness of 3 μm.

The first channel layer 14 has a large In composition of 0.75
Q, is made of 25As mixed crystal, and its thickness is In
It is limited to 150 A, which is a range in which misfit dislocation due to lattice mismatch with the Ga cap layer 15 does not occur. On the other hand, the second channel layer 13 is made of InGa
0.53 0.47 layer 13A below the 200A thick layer made of As, and 0.53 0.47 layer 13A made of In Ga As.
60 0.40 200A middle layer 13B and In GaO, 880
, 32 As, the upper layer 13C is composed of three layers. 1n Ga AS in lower layer 13A has a buffer of 0.53
0.47 0.48 0.52A of lattice alignment layer 12 for As
jl In and also this lower layer 13A In GaO, 530
, 47 As, In Ga As of the middle layer 13B
The lattice mismatch of O,600,40 is hardly a problem. Similarly, upper layer 1
3C In Ga As has a middle layer of 130.8
The lattice mismatch of 0.60 0.40 for In'GaAs of 8 0.32 B is rarely a problem, and the I of the first channel layer 14 is
Almost lattice matched to n Ga AS, 0.75
0.25 The second channel layer 13 is a step-graded channel layer that alleviates the lattice mismatch between the buffer layer 12 and the first channel layer 14.

Furthermore, the cap layer 15 acts as an electron supply layer, but in order to ensure a sufficient depth of the potential well formed in the channel layer portion, the cap layer 15 is
A material with an electron affinity smaller than that of No. 4 is used. In this embodiment, the cap layer 15 is an undoped A layer with a thickness of 2OA.
Spacer layer 15A5 made of RO, 48In As
Donor 0.52 AΩ An AsO with a thickness of 300A doped with Sl as an impurity to a concentration of n-2X1018 (to)-3
, 480, 52 between the actual electron supply layer 15B and the Schottky gate electrode 16 (barrier hide).
200A thick undoped AI to ensure
Barrier made of I n As 0.48 0.5
It is composed of two layers 15C.

The Schottky gate electrode 16 is made of titanium (TI)/platinum (
Pt)/gold (Au), and the source and drain electrodes 17 and 18 are made of gold-germanium alloy (Au).
It is made of Ge )/nickel (N1)/gold (Au) and subjected to alloying heat treatment at 400° C. for 1 minute.

FIG. 1(b) shows an energy band diagram of the FET of this example.

For comparison, the second channel layer 13 from the configuration of this example
When we fabricated an FET with this removed, the electron mobility was approximately 7.
It was about 000 cd/V-s.

On the other hand, in this example, a value of about 90000-/v-8 was obtained, and the effect of increasing the effective thickness of the channel layer by introducing the second channel layer 13 is clearly visible. .

Note that this invention is not limited to the above embodiments, and various modifications are possible. First, the second channel layer 1
3 is not limited to the above-mentioned three-layer structure, and the average composition can be varied stepwise or continuously.

Further, the first channel layer 14 is made of "n(1,75Ga
InGaAs (0<x≦1) with various compositions as small as 0.25 x
l-x can be used. In either case, the buffer layer 1
If there is a lattice mismatch with respect to 2, the effect of introducing the second channel layer of the present invention can be obtained.

The cap layer 15 is also made of All In As mixed crystal 1
-x x (0≦X≦1), for example, Aj7 Ga1-
x x As mixed crystal (0≦X≦1) or the like may be used.

Furthermore, the method for forming each layer is not limited to the molecular beam epitaxial growth method, and metal organic vapor phase epitaxy, vapor phase epitaxial growth, liquid phase epitaxial growth, and the like can be used. Furthermore, various changes can be made to the impurity concentration and thickness of each layer without departing from the spirit of the invention. Also, the electrode material is not limited to the above examples.
Of course.

The above description has been made using an example in which a FET having a channel layer of x l-x made of InGaAs is formed on an InP substrate, but the present invention is not limited to this.
The present invention can also be applied to the case of forming an FET having a channel layer made of another mixed crystal semiconductor on another semi-insulating or insulating substrate.

〔Effect of the invention〕

As described above, in this invention, a second channel layer whose composition is gradually changed so that lattice mismatch does not become a problem is interposed between a buffer layer and a channel layer (first channel layer). This allows the effective thickness of the channel layer to be increased while suppressing the effects of lattice mismatch. Therefore, even if a material that can only be formed extremely thin due to lattice mismatch is used as the first channel layer, a decrease in electron mobility due to the unevenness of the interface can be avoided.

As a result, as the first channel layer, the electron mobility and saturation speed of This makes it possible to use a material with a large value, and has the effect of realizing a high-speed FET.

[Brief explanation of drawings]

FIG. 1(a) is a sectional view showing an embodiment of the present invention;
b) is its energy band diagram, and FIG. 2 is a sectional view showing a conventional example. 11... Semiconductor substrate, 12... Buffer layer, 13.
... second channel layer, 14... first channel layer,
15... Cap layer, 16... Schottky gate electrode, 17.18... Source/train electrode.

Claims (1)

[Claims] A channel layer made of a mixed crystal semiconductor and a cap layer made of a semiconductor material having a lower electron affinity than this channel layer and containing donor impurities are formed on a semi-insulating or insulating substrate via a buffer layer, and then In a selectively doped field effect transistor in which a Schottky gate electrode and a source/tray electrode are arranged in 1. A field effect transistor characterized in that a second channel layer made of a mixed crystal semiconductor whose composition is gradually changed so as to substantially lattice match the channel layer in the contacting portion thereof.