JPH03198361A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03198361A JPH03198361A JP33966489A JP33966489A JPH03198361A JP H03198361 A JPH03198361 A JP H03198361A JP 33966489 A JP33966489 A JP 33966489A JP 33966489 A JP33966489 A JP 33966489A JP H03198361 A JPH03198361 A JP H03198361A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- metal wiring
- wiring layer
- measurement
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000523 sample Substances 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000012360 testing method Methods 0.000 claims abstract description 5
- 238000005259 measurement Methods 0.000 abstract description 12
- 230000001681 protective effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にＴＡＢ型半導体装置の
電極に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an electrode of a TAB type semiconductor device.
従来、ＴＡＢ型半導体装置のウェーハ状能の測定は、チ
ップ表面の金属配線層の一部領域上にバンプを形成し、
そのバンプの上面に測定用のプローブ針を接触させ行っ
ていた。Conventionally, the wafer performance of TAB type semiconductor devices has been measured by forming bumps on a partial area of the metal wiring layer on the chip surface.
A measurement probe needle was brought into contact with the top surface of the bump.
上述した従来の半導体装置は、バンプの上面からウェー
ハ状態を測定するのでバンプの大きさのバラツキにより
、測定用のプローブ針との接触抵抗がバラツキ、又バン
プ材料が測定針を汚すので、ウェーハのテストが不安定
になるという欠点があった。In the conventional semiconductor device described above, the wafer condition is measured from the top surface of the bumps, so variations in the size of the bumps cause variations in the contact resistance with the measurement probe needles, and the bump material contaminates the measurement probes. The drawback was that the test was unstable.
すなわち、バンプの形成は通常電解メツキで行うが、電
極層の抵抗が均一でないためにバンプ高さにバラツキを
生じ、ウェーハ状態の測定のためプローブ針をバンプの
上面に接触させた場合に、高いバンプには強くプローブ
針の圧力がかかるので、プローブ針が早く磨耗したりま
たは汚れなりして、長期間にわたる安定な測定ができな
くなる。In other words, bumps are usually formed by electrolytic plating, but because the resistance of the electrode layer is not uniform, the height of the bumps varies, and when the probe needle is brought into contact with the top surface of the bumps to measure the wafer condition, the height of the bumps may vary. Since the probe needle applies strong pressure to the bump, the probe needle may wear out quickly or become dirty, making it impossible to perform stable measurements over a long period of time.
本発明の半導体装置は半導体ウェーハ基板の表面の一部
に金属配線層を設け、かつ該金属配線層の表面を覆う絶
縁膜に開孔部を形成してウェーハテスト用のプローブ針
用の接触電極を設けて構成されている。In the semiconductor device of the present invention, a metal wiring layer is provided on a part of the surface of a semiconductor wafer substrate, and an opening is formed in an insulating film covering the surface of the metal wiring layer to form a contact electrode for a probe needle for wafer testing. It is configured with the following.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）及び（ｂ）は本発明の一実施例の平面図及
びＡ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention.
ウェーハ基板上の一部に金属配線２を形成し、その表面
を保護膜３で覆っている。A metal wiring 2 is formed on a part of a wafer substrate, and its surface is covered with a protective film 3.
保護膜３は測定用接触領域４に対応して、開孔部６を形
成している。The protective film 3 has an opening 6 formed therein corresponding to the measurement contact area 4 .
ウェーハ状態を測定するプローブ針は、バンプ５にはバ
ンプ５が表面の一部に形成されている測定用接触領域４
に接触するので、バンプの高さのバラツキに無間係に安
定な測定ができる。The probe needle for measuring the state of the wafer has a bump 5 having a measurement contact area 4 on which the bump 5 is formed on a part of the surface.
Since it makes contact with the bump, stable measurements can be made regardless of variations in bump height.
以上説明したように本発明は、バンプ形成用の電極配線
層上ウェーハテスト用の接触電極を別に設けてウェーハ
の測定が安定にできる効果がある。As described above, the present invention has the effect that wafer measurements can be made stably by separately providing a contact electrode for wafer testing on the electrode wiring layer for forming bumps.
第１図（ａ）及び（ｂ）は本発明の一実施例の平面図及
びＡ−Ａ’線断面図である。
１・・・ウェーハ基板、２・・・金属配線、３・・・保
護膜、４・・・測定用接触領域、５・・・バンプ、６用
量孔部。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Wafer substrate, 2... Metal wiring, 3... Protective film, 4... Contact area for measurement, 5... Bump, 6 Dose hole part.
Claims (1)
かつ該金属配線層の表面を覆う絶縁膜に開孔部を形成し
てウェーハテスト用のプローブ針用の接触電極を設けた
ことを特徴とする半導体装置。A metal wiring layer is provided on a part of the surface of the semiconductor wafer substrate,
A semiconductor device characterized in that an opening is formed in an insulating film covering a surface of the metal wiring layer to provide a contact electrode for a probe needle for wafer testing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33966489A JPH03198361A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33966489A JPH03198361A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03198361A true JPH03198361A (en) | 1991-08-29 |
Family
ID=18329639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33966489A Pending JPH03198361A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03198361A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100327442B1 (en) * | 1995-07-14 | 2002-06-29 | 구본준, 론 위라하디락사 | Bump structure of semiconductor device and fabricating method thereof |
| JP2003068736A (en) * | 2001-08-24 | 2003-03-07 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
-
1989
- 1989-12-26 JP JP33966489A patent/JPH03198361A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100327442B1 (en) * | 1995-07-14 | 2002-06-29 | 구본준, 론 위라하디락사 | Bump structure of semiconductor device and fabricating method thereof |
| JP2003068736A (en) * | 2001-08-24 | 2003-03-07 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
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