JPS63220537A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPS63220537A
JPS63220537A JP5461287A JP5461287A JPS63220537A JP S63220537 A JPS63220537 A JP S63220537A JP 5461287 A JP5461287 A JP 5461287A JP 5461287 A JP5461287 A JP 5461287A JP S63220537 A JPS63220537 A JP S63220537A
Authority
JP
Japan
Prior art keywords
polysilicon
resistors
semiconductor substrate
polysilicon resistors
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5461287A
Other languages
Japanese (ja)
Inventor
Nobutaka Nagai
長井 信孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5461287A priority Critical patent/JPS63220537A/en
Publication of JPS63220537A publication Critical patent/JPS63220537A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the accuracy of measurement by inserting exclusive chips, to which inspection patterns for inspecting the characteristics of polysilicon resistors having a high resistance value of 0.1GOMEGA or more as well as semiconductor devices with the polysilicon resistors are formed, at several positions in the surface of a semiconductor substrate. CONSTITUTION:A semiconductor substrate 2 in which inspection pattern 1 chips inspecting the characteristics of polysilicon resistors 4 as well as semiconductor devices with the resistors being shaped by depositing polysilicon and having 0.1GOMEGA or more are inserted to several positions in the surface of a substrate is acquired. Each pattern 1 takes shapes having contacts 3 at both ends of the polysilicon resistors 4. The length of the polysilicon resistors 4 among the contacts 3 and the contacts 3 is brought to one over an integer of the length of the polysilicon resistors disposed to the actual semiconductor devices, and width thereof is brought to integral times, thus lowering the resistance values of inspection exclusive patterns 1, then forming correlation with the resistance values of the polysilicon resistors arranged to the actual semiconductor devices. Accordingly, the accuracy of the measurement of the resistors can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体基板に関し、特に0.1GΩ以上の高
いポリシリコン抵抗を有する半導体装置を形成した半導
体基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor substrate, and particularly to a semiconductor substrate on which a semiconductor device having a high polysilicon resistance of 0.1 GΩ or more is formed.

〔従来の技術〕[Conventional technology]

従来の半導体装置の例を第3図に示す。スクライプ線1
4で囲まれた半導体基板をコレクタとし、その中にベー
ス領域11とエミッタ領域12を有し、ベース領域11
上にはベース電極用のポンディングパッド6が、またエ
ミッタ領域12上にはエミッタ電極用のポンディングパ
ッド13を有し、これらポンディングパッド6と13と
が金属の配線8と0.1GΩ以上の高い抵抗値のポリシ
リコン抵抗7,9とで接続されている。かかるポリシリ
コン抵抗7,9のみの抵抗値の測定は、チェックパター
ンが存在しないため、実際の半導体装置の1つを用いて
いたが、配a8とのコンタクト窓10に10〜15ψμ
mあるグローブの針が当てられず、素子形成後にポンデ
ィングパッド部6,13にグローブ針を当てて測定して
いた。
An example of a conventional semiconductor device is shown in FIG. Scripe line 1
The semiconductor substrate surrounded by 4 is used as a collector, and has a base region 11 and an emitter region 12 therein.
There is a bonding pad 6 for the base electrode on the top, and a bonding pad 13 for the emitter electrode on the emitter region 12. The resistors 7 and 9 are connected to polysilicon resistors 7 and 9 having high resistance values. To measure the resistance value of only the polysilicon resistors 7 and 9, one of the actual semiconductor devices was used since there was no check pattern.
Since the glove needle could not be applied, the measurement was carried out by applying the glove needle to the bonding pad portions 6 and 13 after the element was formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の0.1GΩ以上の高いポリシリコン抵抗
を有する半導体装置を形成した半導体基板は、ポリシリ
コン抵抗の検査を行なう専用の検査パターンを有しない
ため、抵抗の特性を検査しようとするとき、次のような
欠点があった。
The above-described conventional semiconductor substrate on which a semiconductor device having a high polysilicon resistance of 0.1 GΩ or more is formed does not have a dedicated test pattern for testing polysilicon resistance, so when testing the resistance characteristics, It had the following drawbacks.

1、電極形成後でないと測定できない。1. Measurement cannot be performed until after electrode formation.

2、トランジスタのエミッターベース間(第3図(b)
)が抵抗と並列に入っているため測定値に影響を与える
2. Between the emitter and base of the transistor (Figure 3(b)
) is connected in parallel with the resistor, which affects the measured value.

3、抵抗が非常に太きいため、測定時に小電流1が流れ
ず測定精度が悪い。
3. Because the resistance is very thick, a small current 1 does not flow during measurement, resulting in poor measurement accuracy.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば、ポリシリコンを堆積させることによっ
て形成された0、1GΩ以上の抵抗を有する半導体装置
とともに、ポリシリコン抵抗の特性検査を行なう検査パ
ターンチップを基板面内数箇所に挿入した半導体基板を
得る。
According to the present invention, a semiconductor device having a resistance of 0.1 GΩ or more formed by depositing polysilicon, and a semiconductor substrate in which test pattern chips for testing the characteristics of the polysilicon resistance are inserted at several locations on the substrate surface. get.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の半導体基板の平面図である
。第2図は第1図の半導体基板に挿入されている抵抗検
査専用パターンの拡大図である。
FIG. 1 is a plan view of a semiconductor substrate according to an embodiment of the present invention. FIG. 2 is an enlarged view of a resistance testing pattern inserted into the semiconductor substrate of FIG. 1.

半導体基板2の数カ所に抵抗検査専用パターン1を有し
ておシ、各パターン1はポリシリコン抵抗4の両端にコ
ンタクト3を有する形状となっている。コンタクト3と
コンタクト3との間のポリシリコン抵抗4の長さは、実
際の半導体装置に配されているポリシリコン抵抗(第3
図7又は9)の長さの整数分の1とし、幅は、整数倍と
することで検査専用パターン1の抵抗値を下げ実際の半
導体装置に配されているポリシリコン抵抗(g3図7.
9)の抵抗値と相関をもたせている。尚、検査専用パタ
ーン1は他の半導体装置と同じ面積のチップ上に形成さ
れており、周囲はスクライブ線5で囲まれている。
Patterns 1 dedicated to resistance testing are provided at several locations on a semiconductor substrate 2, and each pattern 1 has a shape having contacts 3 at both ends of a polysilicon resistor 4. The length of the polysilicon resistor 4 between the contacts 3 is the same as the length of the polysilicon resistor (the third polysilicon resistor) arranged in the actual semiconductor device.
By setting the length to an integer fraction of the length (FIG. 7 or 9), and making the width an integral multiple, the resistance value of the test pattern 1 can be lowered and the polysilicon resistor (g3 in FIG. 7.
9) has a correlation with the resistance value. The inspection pattern 1 is formed on a chip having the same area as other semiconductor devices, and is surrounded by scribe lines 5.

この仁とによって、ポリシリコン抵抗の抵抗値の測定が
実際の半導体装置(第3図)に配されているポリシリコ
ン抵抗(第3図7,9)を測定したよシも大きな電流で
測定が可能となシ測定精度が高まり、又トランジスタの
影響を受けずに測定が可能となるという利点がある。
Due to this strength, the resistance value of a polysilicon resistor can be measured using a large current compared to the measurement of a polysilicon resistor (7, 9 in Figure 3) arranged in an actual semiconductor device (Figure 3). This has the advantage of increasing the accuracy of possible measurements and making it possible to perform measurements without being influenced by transistors.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、0.1GΩ以上の高抵
抗値のポリシリコン抵抗を有する半導体装置とともに、
ポリシリコン抵抗の特性検査のだめの検査パターンを設
けた専用のチップを半導体基板面内数箇所に挿入するこ
とにより、電極形成前に特性検査できることで、細かな
抵抗の制御が可能となり、又検査パターンの抵抗値を下
げられること、測定に際しトランジスタ部の影響を受け
々いため抵抗の測定精度を高めることができる効果があ
る。
As explained above, the present invention provides a semiconductor device having a polysilicon resistor with a high resistance value of 0.1 GΩ or more,
By inserting a dedicated chip with a test pattern for testing the characteristics of polysilicon resistors into several locations on the semiconductor substrate, the characteristics can be tested before electrode formation, making it possible to precisely control the resistance. This has the effect of lowering the resistance value of the resistor, and increasing the accuracy of resistance measurement because the measurement is less affected by the transistor section.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の半導体基板の平面図、第2
図は第1図の半導体基板に挿入される抵抗の検査パター
ンチップの拡大平面図、第3図(a)は従来からの抵抗
を有する半導体装置の平面図、第3図(b)は第3回し
)の等価回路図である。 1・・・・・・検査専用パターン、2・・・・・・半導
体基板、3・・・・・・コンタクト、4・・・・・・ポ
リシリコン抵抗、5・・・・・・スクライブ線、6・・
・・・・ポンディングパッド(ベース側)、7・・・・
・・ポリシリコン抵抗(エミッターベース間)、8・・
・・・・配線、9・・・・・・ポリシリコン抵抗(ベー
ス)、10・・・・・・コンタクト窓、11・・・・・
・ベース領域、12・・・・・・エミッタ領域、13・
・・・・・ポンディングパッド(エミッタ側)、14・
・・・・・スクライブ線。 −〇− (b) 葦 3 図
FIG. 1 is a plan view of a semiconductor substrate according to an embodiment of the present invention, and FIG.
The figure is an enlarged plan view of a resistor test pattern chip inserted into the semiconductor substrate of FIG. 1, FIG. 3(a) is a plan view of a semiconductor device having a conventional resistor, and FIG. 3(b) is a FIG. 1...Test pattern, 2...Semiconductor substrate, 3...Contact, 4...Polysilicon resistor, 5...Scribe line , 6...
...Ponding pad (base side), 7...
・Polysilicon resistor (between emitter and base), 8...
... Wiring, 9 ... Polysilicon resistor (base), 10 ... Contact window, 11 ...
・Base region, 12...Emitter region, 13.
...Ponding pad (emitter side), 14.
...Scribe line. -〇- (b) Reed 3 Figure

Claims (1)

【特許請求の範囲】[Claims] ポリシリコンを堆積させることによって形成された、0
.1GΩ以上の抵抗を有する半導体装置とともに、前記
抵抗の特性検査を行なう検査パターンを基板面内数箇所
に挿入したことを特徴とする半導体基板。
formed by depositing polysilicon, 0
.. 1. A semiconductor substrate, characterized in that a semiconductor device having a resistance of 1 GΩ or more and test patterns for testing characteristics of the resistance are inserted at several locations within the surface of the substrate.
JP5461287A 1987-03-09 1987-03-09 Semiconductor substrate Pending JPS63220537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5461287A JPS63220537A (en) 1987-03-09 1987-03-09 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5461287A JPS63220537A (en) 1987-03-09 1987-03-09 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS63220537A true JPS63220537A (en) 1988-09-13

Family

ID=12975563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5461287A Pending JPS63220537A (en) 1987-03-09 1987-03-09 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS63220537A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143061A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Integrated circuit
JPS5740951A (en) * 1980-08-25 1982-03-06 Fujitsu Ltd Manufacture of semiconductor device
JPS5749247A (en) * 1980-07-11 1982-03-23 Western Electric Co Semiconductor wafer and method of producing same
JPS605537A (en) * 1984-05-11 1985-01-12 Nec Corp Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143061A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Integrated circuit
JPS5749247A (en) * 1980-07-11 1982-03-23 Western Electric Co Semiconductor wafer and method of producing same
JPS5740951A (en) * 1980-08-25 1982-03-06 Fujitsu Ltd Manufacture of semiconductor device
JPS605537A (en) * 1984-05-11 1985-01-12 Nec Corp Semiconductor device

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