JPH03198173A - One-chip microcomputer - Google Patents

Abstract

PURPOSE:To apply the one-chip microcomputer to the external memory whose processing speed is low, as well without enlarging a chip size by enlarging only a transistor for driving an internal data bus. CONSTITUTION:By enlarging the transistor size of an external data input buffer 3 for outputting to an internal data bus 2, comparing with the transistor size of an external input buffer 6 for outputting to the internal data bus 2, only the driving capacity of the transistor of the external data input buffer 3 is enlarged. Accordingly, the delay time can be shortened, and the minimum time(D +E) can be shortened. Therefore, since the time extending from the time point when data is defined to an external data bus 4 to C is shorter than the minimum time, even if that of a high processing speed is used for an external memory, or the processing speed of the external memory is low, the processing speed of the one-chip microcomputer is increased and the one-chip microcomputer can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a one-chip microcomputer that can be applied to an external memory with a slow processing speed without increasing the chip size.

[Conventional technology]

CMO8 (Complementary Metal-
Oxide-5emiconductor) one-chip microcomputer C is hereinafter referred to as one-chip microcomputer. ) will be explained as an example.

The one-chip microcomputer shall be used independently, C or lower, and shall be in single-step mode. ), as well as C that is used while exchanging data through external memory and data bus.
The following is referred to as extended mode. ) can also be done. For receiving data from external memory in extended mode, a portion of the input/output ports that were input/output ports in single-chip mode are allocated.

In FIG. 2, it is assumed that the data output from the external memory is processed by the central processing unit C or lower, such as the CPU. ) is a circuit block diagram illustrating the flow of data until it is taken into the device. In the figure, 1 is a CPU, 2 is an internal data bus, 3 is an external data input buffer 1.4 is an external data bus, 5 is an external memory, 6 is an external input buffer 17 is an external output buffer 1.8 is an external address bus It shows. Data output from the external memory 5 is taken into the Washi chip microcomputer through the external data bus 4. The data is sent to the internal data bus 2 through the external data buffer 13, and is sent to the CP
After being fetched into U, it is processed and output to external memory 5 via external output buffer 7 and external address bus 8. The following will explain two types of external memory, one with a fast processing speed and one with a slow processing speed, as an example.

FIG. 3 is a timing chart showing the process from when the one-chip microcomputer receives one piece of data outputted from the high-speed external memory by a command to the one-chip microcomputer's CPU. In the figure, - is the one-chip microcontroller clock, A
D is the address output by the one-chip microcomputer, A is the data timing on the external data bus 4, B is the data timing on the internal data bus 2, and C is the CP
U starts importing data - rises, D rises to C
The data set up time of the input buffer in the PU, E, is the delay time until the data is output from the external data input buffer 13 and is determined on the internal data bus 2, and F indicates the output enable signal of the external data input buffer 13.

D is determined by the structure of the logic circuit of the input buffer in the CPU, and E is determined by the load capacitance of the internal data bus 2 and the driving ability of the transistors of the external data input buffer 3.

Here, D is constant because the logic circuit is not changed. Also, the driving ability of a transistor is β or gm
It is. F is a signal output by a CPU instruction,
When the output is 'H', it is possible to output data from the external data manual buffer 13 to the internal data bus 2, and when the output is 'L', it is not possible to output data from the external data manual buffer 3 to the internal data bus 2. ing.

Since the CPU starts taking in data at the rising edge (C) of -, the data must be finalized on the internal data bus 2 by C. In this case, since the data has been determined by C, the CPU can take in the data.

FIG. 4 is a timing diagram showing the process until the CPU of the one-chip microcomputer receives data output from the one-chip microcomputer according to a command from the external memory 5, which has a slow processing speed. In the figure, - is the one-chip microcontroller clock, A
D is the address output by the one-chip microcomputer, A is the data timing on the external data bus 4, B is the data timing on the internal data bus 2, and C is the CP
U indicates the rise of - when data is taken in, E indicates the delay time until data is finalized on the internal data bus 2 after being output from the external data input buffer 3, and F indicates the output enable signal of the external data input buffer 13. .

Since the processing speed of the external memory 5 is slow, data is output to the external data bus 4 with a delay compared to the case in Figure @3. Due to the delay time and the delayed output of the data, the data is not output to the internal data bus 2 by C. Therefore, the CPU cannot take in data and malfunctions.

FIG. 5 shows an example of the configuration of the external data manual buffer 13 or the external data buffer 16. In the figure, input data is input to a NAND circuit and one terminal of the NAND circuit, and external data input The buffer output enable signal F is connected between the other terminal of this NAND circuit and the NO
It is branched and inputted to the other terminal of the NOR circuit via the T circuit. Then, the output of each of these NAND and NOR circuits is a P-channel transistor TP and an N-channel transistor T connected in series between the power supply Vcc and the ground Vss.
The signal is inputted to each gate of N, and outputted from the common drain of these transistors TP and TN. Transistors TN and TP shown inside the broken line are transistors for driving the internal data bus 2.

Hereinafter, the third transistor will be referred to as a transistor of the external data input buffer 13 or a transistor of the external input buffer 16.

[Problem to be solved by the invention]

Since the data set 7 time of the CPU student Kabuff 1 is constant unless the structure of the logic circuit of the input buffer in the CPU is changed, the external data bus The minimum time (minimum time=D+E) from when the data is determined in step 4 to step C is determined. External data bus 4
If the external memory 5 has such a slow processing speed that the time from when data is finalized to C exceeds the minimum time, it will malfunction because the data is not output to the internal data bus 2 as described above, and the external memory 5 It could not be used as a

One way to increase the driving ability of a transistor is to increase the size of the transistor. Here, increasing the transistor size means increasing the gate width.

β or gm is directly proportional to the gate width. In other words, increasing the transistor size means
β or g. This leads to increasing the size. As a result, increasing the transistor size increases the driving ability of the transistor. In a conventional one-chip microcontroller, the transistor size of the external data manual buffer 13 and the transistor of the external input rose 716 are the same, and if you try to shorten the delay time by increasing the transistor size of the external data manual buffer 3, The transistor size of buffer 16 also had to be increased. However, external data human power buffer 73
Simultaneously increasing the transistor size of the external input buffer 16 increases the load capacity of the internal data bus 2, which not only makes it impossible to significantly shorten the delay time but also increases the chip area. This leads to things. Therefore, increasing the size of both the transistors of the external data manual buffer 13 and the transistors of the external input buffer 16 will not only make it impossible to shorten the minimum time, but also increase the chip area.

From the above, in order to use a one-chip microcontroller, it is possible to use a high-speed external memory 5 to send data to the external data bus 4 quickly, or to lower the clock frequency of the one-chip microcontroller to The processing speed of the microcomputer had to be reduced.

This invention was made to solve the above-mentioned problems, and the purpose is to obtain a one-chip microcontroller that can be applied to external memory with slow processing speed without increasing the chip size. shall be.

[Means to solve the problem]

The present invention solves the above-mentioned conventional problems, and in order to enable a one-chip microcomputer to use an external memory with a slow processing speed, an external manual buffer 1 for outputting to an internal data bus is provided. By increasing the transistor size of the transistor of the external data input buffer 1 for outputting to the internal data bus compared to the transistor size of the transistor of the external data input buffer 1, only the driving capacity of the transistor of the external data input buffer 1 is increased. be.

[Effect]

According to the present invention, the delay time can be shortened,
The minimum time can be shortened.

Therefore, if the time from the time when data is finalized on the external data bus to C is shorter than the minimum time mentioned above, it is possible to use a fast processing speed external memory, or even if the processing speed of the external memory is slow, it is possible to use a single chip. It is possible to increase the processing speed of the microcontroller and use a one-chip microcontroller.

〔Example〕

FIG. 1 is a timing diagram when the present invention is implemented. In the figure, - is the one-chip microcontroller clock, A
D is the address output by the one-chip microcomputer, A is the data timing on the external data bus 4, B is the data timing on the internal data bus 2, and C is the CP
U starts importing data - rises, D rises to C
E represents the data set up time of the input buffer in the PU, E represents the delay time from when the data is output from the external data input buffer 13 until it is finalized on the internal data bus 2, and F represents the output enable signal of the external data input buffer 13.

The transistor size of the external input buffer 16 is the same as before, and in this invention, the external data input buffer 13
Only the transistor size of the chip is increased, and thereby the delay time can be shortened without increasing the chip size.

Since the delay time is shortened, the minimum time is also shortened. As a result, although the timing at which the data is determined on the external data bus 4 is the same as that shown in FIG. The process can be performed normally. In other words, even if the external memory 5 with a slow processing speed is used, data processing can be performed normally.

The above means that the scope of application of the processing speed of the external memory 5 of the one-chip microcomputer is expanded to include the external memory 5, which has a slow processing speed, without reducing the processing speed of the one-chip microcomputer. Further, since the load capacitance of the internal data bus 2 with respect to the transistors other than those mentioned above increases only slightly, the driving ability of the transistors other than those mentioned above does not change.

In the above embodiment, the external memory 5 is connected to the external data bus input of the one-chip microcomputer, but other integrated circuits may be used in the one-chip microcomputer. Further, although the embodiment uses an input-only bus, the same effect can be obtained even if a bidirectional bus is used.

In the above embodiment, the external memory 5 is connected to the external data input buffer 13 of the one-chip microcomputer, but other integrated circuits may be used for the one-chip microcomputer. Furthermore, although the input-only bus was used in the above embodiment, the same effect can be obtained even if a bidirectional bus is used.

〔Effect of the invention〕

As described above, according to the present invention, the drive capacity is increased by increasing the size of only the transistor of the external data manual buffer without increasing the chip size, so the delay time can be shortened, and the minimum time can be shortened. be able to. Therefore, without reducing the processing speed of the one-chip microcontroller, the application range of the one-chip microcontroller can be expanded in terms of the processing speed of external memory, and even when using slow external memory, the processing speed of the one-chip microcontroller can be increased and used. There is an effect that can be done.

Furthermore, since the load capacitance of the internal data bus for the target transistor does not change, it is possible to easily increase only the drive capacity of the target transistor, and the internal data bus for transistors other than those mentioned above can be easily increased. Since the load capacitance is only slightly increased, there is also the effect that the driving ability of transistors other than those described above is not changed.

[Brief explanation of drawings]

Figure 1 is a timing diagram when this invention is implemented, and Figure 2 is a timing diagram when this invention is implemented.
The figure is a circuit block diagram showing the data flow until the data output from the external memory is taken into the CPU. Figure 3 is a circuit block diagram showing the data flow from the one-chip microcontroller to the data output from the fast-processing external memory. Figure 4 is a timing diagram showing the process by which data is received by the one-chip microcontroller's CPU from an external memory with a slow processing speed.
FIG. 5, which is a timing chart until the PU receives the data, is a circuit diagram showing an example of the configuration of the external data input buffer 1 or the external manual buffer. In the figure, 1 is the CPU, 2 is the internal data bus, 3 is the external data manual buffer, 4 is the external data bus, 5 is the external memory, 6 is the external manual buffer, - is the clock of the one-chip microcomputer, and AD is the one-chip microcomputer A is the timing of the data on the external data bus 4, B is the timing of the data on the internal data bus 2, C is the rising edge of - when the CPU starts taking in data, and D is the timing of the internal buffer of the CPU. The data set up time, E, is the delay time from when the data is output from the external data manual buffer 3 until it is finalized on the internal data bus 2, and F is the external data manual buffer output enable signal. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] When receiving data from another integrated circuit, a transistor for driving the internal data bus inside the one-chip microcomputer is installed in the external input buffer of the port that becomes the data bus, and the input buffer of the port other than the port that becomes the data bus A one-chip microcomputer characterized in that the size of the transistor is larger than that of the transistor for driving the internal data bus.