JPH03196592A - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JPH03196592A
JPH03196592A JP33477789A JP33477789A JPH03196592A JP H03196592 A JPH03196592 A JP H03196592A JP 33477789 A JP33477789 A JP 33477789A JP 33477789 A JP33477789 A JP 33477789A JP H03196592 A JPH03196592 A JP H03196592A
Authority
JP
Japan
Prior art keywords
holes
wiring
board
row
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33477789A
Other languages
Japanese (ja)
Inventor
Yasuhiro Takebayashi
泰弘 竹林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP33477789A priority Critical patent/JPH03196592A/en
Publication of JPH03196592A publication Critical patent/JPH03196592A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/117Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To enable execution of wiring of high density with the cost reduced, by removing lands of through holes in a row in an outside area through which a wiring pattern passes and by passing the wiring pattern from the inside to the outside. CONSTITUTION:The surface and the rear of a board 1 are formed of a component mounting surface 1A and a soldering surface 1B respectively and a number of through holes 2 and 3 are bored in such a manner that they are juxtaposed in inside and outside areas in the shape of a zigzag arrangement and that they are spaced by a prescribed gap L1 with a half pitch shifted from each other. Wiring patterns 4 printed on the component mounting surface 1A of the board 1 are so designed that they are connected to lands 21 fitted to the through holes 2 in a row in the inside area and can be led outward through between the through holes 3 in a row in the outside area. Since the wirable width between the through holes is enlarged by this constitution, such waste as increasing the number of layers of the board or stretching around the wiring other than the wiring patterns is eliminated and the wiring of high density can be executed inexpensively and easily.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) 本発明は、例えばQFP (Quad  FlatPa
ckage)用ソケット等の電子部品を高密度配線によ
り実装するに用いられるプリント基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention is directed to, for example, QFP (Quad FlatPa
The present invention relates to a printed circuit board used for mounting electronic components such as sockets for electronic cages with high-density wiring.

(従来の技術) 従来、この種のプリント基板においては、部品装着面に
電子部品を装着するために、電子部品のピンが挿入され
る多数のスルーホールが穿設されている。
(Prior Art) Conventionally, in this type of printed circuit board, in order to mount electronic components on the component mounting surface, a large number of through holes are formed into which pins of the electronic components are inserted.

そして、このようなプリント基板にあっては、例えばQ
FP用ソケット等の部品を装着する場合のように、基板
の表裏両面間に多数のスルーホールが千鳥配列状に内外
2列の領域に並列させて穿設され、かつその内側領域の
スルーホールの列を外側領域のスルーホールの列で囲む
ような構成となっている。
In such a printed circuit board, for example, Q
When installing parts such as FP sockets, a large number of through holes are drilled between the front and back surfaces of the board in a staggered arrangement in two rows of areas, the outside and the outside, and the through holes in the inner area are The row is surrounded by a row of through holes in the outer region.

しかしながら、上記した従来摺造のものでは、特に高密
度配線により実装する際、外側領域の列のスルーホール
にランドが付いていると、各々のスルーホール間のラン
ド間隙が印刷せんとする配線パターンの幅よりも狭い場
合、基板の表裏面の最外層だけを使って内側領域の列の
スルーホールに接続した配線パターンを、外側領域のス
ルーホールの列の外に引出して配線することができない
However, with the above-mentioned conventional sliding structure, when mounting with high-density wiring, if lands are attached to the through-holes in the rows in the outer region, the land gaps between the through-holes will cause the wiring pattern to be printed. If the width is narrower than the width of the board, the wiring pattern connected to the through-hole row in the inner region using only the outermost layer on the front and back surfaces of the board cannot be routed outside the through-hole row in the outer region.

(発明が解決しようとする課題) このため、従来ではプリント基板を更に多層に増やし、
その増やした層を使って配線するか、あるいは配線パタ
ーンを使わずに、ジャンパ線によって引き回し配線しな
ければならなず、無駄な配線作業が必要となり、コスト
高になるという問題があった。
(Problem to be solved by the invention) For this reason, in the past, the number of printed circuit boards was increased by adding more layers.
Wiring must be done using the increased layer, or wiring must be routed using jumper wires without using a wiring pattern, resulting in unnecessary wiring work and increased costs.

本発明は、上記の事情のもとになされたもので、その目
的とするところは、安価にかつ容易に高密度配線を行な
うことができるようにしたプリント基板を提供すること
にある。
The present invention has been made under the above circumstances, and an object thereof is to provide a printed circuit board that allows high-density wiring to be easily performed at low cost.

[発明の構成コ (課題を解決するための手段) 上記した課題を解決するために、本発明は、部品装着面
と半田面とからなる表裏両面に配線パターンがそれぞれ
印刷された基板と、この基板の表裏両面間に千鳥配列状
に内外領域に並列させて穿設されかつその内側領域の列
を外側領域の列で囲むようにするとともにランド間隙が
前記配線パターンの幅よりも狭い多数のスルーホールと
を具備し、前記内側領域の列のスルーホールに接続した
配線パターンを、外側領域の列のスルーホール間を通し
て引き出すにあたり、この外側領域の列のスルーホール
のランドを除去してなる構成としたものである。
[Structure of the Invention (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a substrate having a wiring pattern printed on both the front and back surfaces, which are composed of a component mounting surface and a soldering surface, and A large number of through holes are formed between the front and back surfaces of the board in a staggered manner in parallel to the inner and outer regions, and the rows of the inner region are surrounded by the rows of the outer region, and the land gap is narrower than the width of the wiring pattern. holes, and when the wiring pattern connected to the through-holes in the row of the inner region is led out between the through-holes in the row of the outer region, the lands of the through-holes in the row of the outer region are removed. This is what I did.

(作 用) すなわち、本発明は、上記のような構成とすることによ
って、スルーホール間の配線可能幅が広がるために、基
板の暦数を増やしたり、配線パターン以外に配線を引き
回すなどの無駄が省ける。
(Function) In other words, the present invention has the above-described configuration, which widens the possible width of wiring between through-holes, thereby eliminating the need for unnecessary wiring such as increasing the number of circuit boards and routing wiring other than the wiring pattern. can be omitted.

(実 施 例) 以下、本発明を図示の一実施例を参照しながら詳細に説
明する。
(Example) Hereinafter, the present invention will be described in detail with reference to an illustrated example.

第2図に示すように、図中1は本発明に係る基板である
。この基板1の表裏両面は5部品装着面IAと半田面I
Bとからなり、これら各々の部品装着面IAと半田面1
8間には、第1図及び第3図に示すように、多数のスル
ーホール2・・・及び3・・・が互いに半ピツチずらせ
ながら所定の間隙L1を存して千鳥配列状に内外領域に
並列させて穿設されている。
As shown in FIG. 2, numeral 1 in the figure is a substrate according to the present invention. The front and back surfaces of this board 1 are the 5 component mounting surface IA and the soldering surface I.
B, each of which has a component mounting surface IA and a soldering surface 1.
8, as shown in FIGS. 1 and 3, a large number of through holes 2... and 3... are arranged in a staggered manner in the inner and outer regions with a predetermined gap L1 while being shifted by half a pitch from each other. The holes are drilled in parallel to each other.

この内側領域の列のスルーホール2・・・は、外側領域
の列のスルーホール3・・・で囲まれている。
The through holes 2 in the inner region row are surrounded by the through holes 3 in the outer region row.

また1図中4及び5は前記基板1の部品装着面IAと半
田面IBにそれぞれ印刷した配線パターンである。
Further, numerals 4 and 5 in FIG. 1 are wiring patterns printed on the component mounting surface IA and the soldering surface IB of the board 1, respectively.

前記基板1の部品装着面IAに印刷した配線パターン4
は、内側領域の列のスルーホール2・・・に付けたラン
ド21.21に接続されて、外側領域の列のスルーホー
ル3.3間を通して外側に弓き出し可能になっている。
Wiring pattern 4 printed on the component mounting surface IA of the board 1
are connected to the lands 21.21 attached to the through holes 2 in the row of the inner region, and can be projected outward through the through holes 3.3 in the row of the outer region.

すなわち、前記外側領域の列のスルーホール3は、ラン
ドが除去されていて、その分だけランド間隙L2よりも
スルーホール3,3間の間隙L工を大きくしている。こ
れによって、ランド間隙L2が、前記配線パターン4及
び5の幅L0よりも狭い場合でも、前記内側領域の列の
スルーホール2゜・・に接続した配線パターン4を、外
側領域の列のスルーホール3.3間を通して引き出し配
線することができるようになっているものである。
That is, the lands of the through holes 3 in the row in the outer region have been removed, and the gap L between the through holes 3 is made larger than the land gap L2 by that much. As a result, even if the land gap L2 is narrower than the width L0 of the wiring patterns 4 and 5, the wiring pattern 4 connected to the through-hole 2° in the row of the inner region can be connected to the through-hole of the row of the outer region. 3. Wiring can be drawn out through the space between 3 and 3.

一方、前記基板1の半田面IBに印刷した配線パターン
5は、第3図に示すように、外側領域の列のスルーホー
ル3に付けたランド31にそのまま接続されて、外側に
引出し配線されている。なお、図中22.22は前記基
板1の半田面IB側の内側領域の列のスルーホール2・
・・に付けたランドである。
On the other hand, as shown in FIG. 3, the wiring pattern 5 printed on the solder surface IB of the board 1 is directly connected to the land 31 attached to the through hole 3 in the row of the outer region, and is drawn out and wired to the outside. There is. Note that 22.22 in the figure indicates the through holes 2 and 22 in the inner region row on the solder surface IB side of the board 1.
It is a land attached to...

ところで、前記基板1の部品装着面IAに実装される部
品、例えばQFP型集型口積回路IC填されるQFP用
ソケットWは、第4図及び第5図に示すような構成とな
っている。
Incidentally, a QFP socket W into which a component mounted on the component mounting surface IA of the board 1, such as a QFP type integrated circuit IC, is inserted has a structure as shown in FIGS. 4 and 5. .

すなわち、このQFP用ソケットWの下面には、前記ス
ルーホール2及び3と同様な配列で多数のピンP□、P
2が互いに半ピツチずらせながら所定の間隙L3を存し
て千鳥配列状に内外領域に並列させて植設され、これら
内外領域の列各々のピンP□及びP2を前記スルーホー
ル2及び3にそれぞれ挿入して、基板1の半田面IB側
で半田付けされるようになっている。
That is, on the lower surface of this QFP socket W, there are many pins P□, P in the same arrangement as the through holes 2 and 3.
2 are planted parallel to each other in the inner and outer regions in a staggered arrangement with a predetermined gap L3 while being shifted by half a pitch from each other, and the pins P□ and P2 of each row of these inner and outer regions are inserted into the through holes 2 and 3, respectively. It is designed to be inserted and soldered on the solder surface IB side of the board 1.

このように、本発明に係るプリント基板は、内側領域の
列のスルーホール2・・・を両面ランド21.22とし
、外側領域の列のスルーホー3・・・は、半田面IBだ
けに配線パターン5を引出すためのラント31を付ける
。そして、配線パターン4が出ていない部品装着面IA
側の外側領域の列のスルーホー3・・・は、ランドを除
去し、これによって、内側領域の列のスルーホール2・
・・のラント21に接続した配線パターン4を、外側領
域の列のラントレスのスルーホール3.3間を通して引
き出し配線することができるようにしてなるものである
As described above, in the printed circuit board according to the present invention, the through-holes 2 in the rows in the inner region are made into double-sided lands 21, 22, and the through-holes 3 in the row in the outer region have wiring patterns only on the solder surface IB. Attach a runt 31 for drawing out 5. Then, the component mounting surface IA where wiring pattern 4 does not appear
The through-holes 3 in the rows of the outer region on the sides have their lands removed, thereby forming the through-holes 2 and 3 in the rows in the inner region.
The wiring patterns 4 connected to the runts 21 can be drawn out and routed through the through holes 3.3 of the runtless columns in the outer region.

[発明の効果] 以上の説明から明らかなように、本発明によれば、ラン
1−間隙か配線パターンの幅よりも狭くて。
[Effects of the Invention] As is clear from the above description, according to the present invention, the run 1 gap is narrower than the width of the wiring pattern.

外側領域の列のスルーホールで囲まれた内側領域の列の
スルーホールに接続された配線パターンを外側に引出す
において、配線パターンが通る外側領域の列のスルーホ
ールのランドを除去してなることから、内側からの配線
パターンを外側に容易に通すことができる。
This is because the land of the through-hole in the outer region column through which the wiring pattern passes is removed when the wiring pattern connected to the through hole in the inner region column surrounded by the through hole in the outer region column is drawn out. , the wiring pattern from the inside can be easily passed through to the outside.

これによって、従来のような基板の暦数を増やしたり、
配線パターン以外に配線を引き回すなどの無駄を省くこ
とができ、コストの低下と共に高密度配線を行なうこと
ができる。
This allows you to increase the number of calendars on the board as before,
It is possible to eliminate waste such as routing wiring other than the wiring pattern, and it is possible to perform high-density wiring while reducing costs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係るプリント基板の一実施例を示す配
線パターンが印刷された部品装着面の一部拡大説明図、
第2図は同じく部品装着状態を示す断面図、第3図は同
じく配線パターンが印刷されたプリント基板の半田面を
一部拡大して示す説明図、第4図はプリント基板に装着
される部品を上下逆にして示す外観図、第5図は同じく
部品に設けたピンの配列状態を示す説明図である。 1・・・基板、 1A・・・部品装着面、 IB・・・半田面、2・・・
内側領域のスルーホール列、 21、2 3 ・ ・ ・ 31 ・ ・ 4 ・ ・ ・ 5 ・ ・ ・ W ・ ・ ・ Lo ・ ・ ・ Ll・ ・ ・ L2・ ・ ・ L、・ ・ ・ 2・・・ランド、 外側領域のスルーホール列、 ・ランド、 部品装着面側の配線パターン、 半田面側の配線パターン、 部品、        P・・・ 配線パターンの幅、 スルーホール間の間隙、 ラント間隙。 ピン間隙。 ビン、
FIG. 1 is a partially enlarged explanatory diagram of a component mounting surface on which a wiring pattern is printed, showing an embodiment of a printed circuit board according to the present invention;
Figure 2 is a cross-sectional view showing how the parts are mounted, Figure 3 is an explanatory diagram showing a partially enlarged solder surface of the printed circuit board on which the wiring pattern is printed, and Figure 4 is the parts mounted on the printed circuit board. FIG. 5 is an explanatory diagram showing the arrangement of pins provided on the same component. 1... Board, 1A... Component mounting surface, IB... Soldering surface, 2...
Through hole row in inner area, 21, 2 3 ・ ・ 31 ・ ・ 4 ・ ・ 5 ・ ・ ・ W ・ ・ ・ Lo ・ ・ ・ Ll ・ ・ L2 ・ ・ L, ・ ・ 2... Land, through-hole row in the outer area, ・Land, wiring pattern on component mounting side, wiring pattern on soldering side, component, P... Width of wiring pattern, gap between through holes, runt gap. Pin gap. bottle,

Claims (1)

【特許請求の範囲】[Claims] (1)部品装着面と半田面とからなる表裏両面に配線パ
ターンがそれぞれ印刷された基板と、この基板の表裏両
面間に千鳥配列状に内外領域に並列させて穿設されかつ
その内側領域の列を外側領域の列で囲むようにするとと
もにランド間隙が前記配線パターンの幅よりも狭い多数
のスルーホールとを具備し、前記内側領域の列のスルー
ホールに接続した配線パターンを外側領域の列のスルー
ホール間を通して引き出すにあたり、 この外側領域の列のスルーホールのランドを除去したこ
とを特徴とするプリント基板。
(1) A board on which wiring patterns are printed on both the front and back sides, consisting of a component mounting surface and a soldering surface, and holes that are parallel to the inner and outer regions in a staggered pattern between the front and back surfaces of this board, and the inner and outer regions of the board. The column is surrounded by the column in the outer region and is provided with a large number of through holes having land gaps narrower than the width of the wiring pattern, and the wiring pattern connected to the through hole in the column in the inner region is surrounded by the column in the outer region. A printed circuit board characterized in that lands of the through holes in the row of the outer region are removed when the printed circuit board is drawn out between the through holes.
JP33477789A 1989-12-26 1989-12-26 Printed circuit board Pending JPH03196592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33477789A JPH03196592A (en) 1989-12-26 1989-12-26 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33477789A JPH03196592A (en) 1989-12-26 1989-12-26 Printed circuit board

Publications (1)

Publication Number Publication Date
JPH03196592A true JPH03196592A (en) 1991-08-28

Family

ID=18281118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33477789A Pending JPH03196592A (en) 1989-12-26 1989-12-26 Printed circuit board

Country Status (1)

Country Link
JP (1) JPH03196592A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016018207A (en) * 2014-07-11 2016-02-01 富士通オプティカルコンポーネンツ株式会社 Optical module and transmitter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016018207A (en) * 2014-07-11 2016-02-01 富士通オプティカルコンポーネンツ株式会社 Optical module and transmitter

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