JPH03196548A - Layout pattern verifying system - Google Patents

Abstract

PURPOSE:To simultaneously verify a plurality of wiring data and to shorten verifying time by incorporating only wiring information in another file to verify a layout pattern. CONSTITUTION:Layout pattern data 1 to be verified is input, and only wiring information is formed as another file 6 from other layout pattern information at the time of execution of an element recognition program 2. When a master/ slice is intended to be verified, the file 6 is formed for the number of wiring data by the program 2 and verified. Thus, a plurality of wiring information are all verified by one execution, and the capacity of a disk is reduced.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is a layerer for verifying LSI patterns. -Relates to pattern verification systems.

[Conventional technology]

Figure 4 is a flow diagram showing a conventional layout pattern verification system.・Layout pattern data created by the editor, (2) is an element recognition program that reads the layout pattern data (1) and performs element recognition, etc. (3) is a database 2 (4) created from the element recognition program (2) is a verification program that accesses the database (3) and performs verification processing, ■ is the internal information of the database (3), and (5) is a netlist file of logic diagram data required by the verification program (4).

Next, the operation will be explained. Database (
3) Create. The verification program (4) verifies the information (5) in the database (3) and the netlist file (5). Repeat the above steps for each type.

[Problem to be solved by the invention]

Conventional layout pattern verification systems were configured as described above, so layers related to element placement use the same data, only layers related to wiring have multiple layers, and are created using a method of creating multiple products with different functions. When verifying a layout pattern (hereinafter referred to as master/slice), there is a problem in that even if there is only one layout pattern data, all processes must be performed for the number of products. This invention was made in order to solve the above-mentioned problems, and provides a layout pattern verification system that can verify all of multiple pieces of wiring information in one execution and also enables reduction of disk capacity. With the goal.

[Means to solve the problem]

The pattern verification system according to this invention includes:
The wiring information is created as a separate file from other layout pattern information when the element recognition program is executed, with the layout pattern data to be verified as input.

[Effect]

In the wiring information file according to the present invention, when verifying a mask/slice, files for the number of wiring data are created and verified by an element recognition program.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a flowchart of a layout pattern verification system according to an embodiment of the present invention. In the figure, (1) is layout pattern data created by a layout editor, (
2) is an element recognition program that receives layout pattern data (1) as input and performs element recognition, (3j is a database created by the element recognition program (2), and (4)
) is a verification program that accesses database (3) and performs layout pattern verification, (5) is a netlist file of logic diagram data required by verification program (4),
(6) is a wiring information file created by the element recognition program (2).

FIG. 2 is a flowchart 1 for verifying according to FIG. 1. Step 1 is a data reading processing section that reads layout pattern data, Step 2 is an element/wiring recognition processing section for the data read by the data reading processing section (Step 1), and Step 3 is a judgment that determines whether it is a master/slice. The processing section, step 4, is a wiring information file creation processing section.

Step 5 is a wiring information file creation processing section when multiple wiring data are not included, step 6 is a database creation processing section, and step 7 is a processing section that uses a netlist file (5), wiring information file (6), and database (3). A layout pattern verification processing unit that performs verification; step 8 is a determination processing unit that determines whether all verification is completed; step 9 is a wiring information card that specifies only layers with different wiring relationships in the case of master/slice; Step 10 is a number designation card that specifies up to which file to be executed when there are multiple wiring information files. FIG. 3 is a diagram of data showing the implementation state of data compatibility between the wiring information file and layout pattern information, and (7) is a diagram of element recognition information data of the layout pattern information;
(8) is a diagram of the data of the wiring information file (6).

Next, the operation will be explained. Layout pattern data (1) is read by a layout pattern data reading processing section (step 1). The read data is used by an element recognition program (2) to create a database (3) containing information necessary for verification. Also, here is the master/
Determination processing unit that determines whether it is a slice (step 3)
Create one or more wiring information files (6). At this time, the data from step 9 of the wiring information card is required, and the card specifies which layer is for which type of wiring among the wiring-related layers, which makes it possible to create multiple wiring information files [6] Become. Next, a verification program (4) performs verification using the database (3), netlist file (5), and wiring information file (6). Here, the connection between the wiring information file (6) and the database (3) is as shown in (8), which is a format example of the element recognition information data (7) in the database (3) and the wiring information file (6). held by Next, the determination processing section, step 8, determines whether all verifications have been completed, and if the verification of the specified file has not been completed according to the verification number designation card step 10,
Another one in the layout pattern verification processing section (step 8)
The verification program (4) is executed and verification is performed.

Note that although the above embodiment shows a case in which a wiring information file (6) is provided, a plurality of pieces of wiring information may be included in the database (3).

〔Effect of the invention〕

As described above, according to the present invention, when verifying a layout pattern including master/slice, by having only the wiring information in a separate file, multiple pieces of wiring data can be verified simultaneously, and the verification time is reduced. Leads to shortening. Furthermore, since only one piece of data is required other than the wiring information, there is an advantage that the disk capacity can be reduced.

[Brief explanation of drawings]

FIG. 1 is a flow diagram of a layout pattern verification system according to an embodiment of the present invention, FIG. m2 is a processing flowchart 1 of FIG. 1, and FIG.
FIG. 4 is a flow diagram of a conventional layout pattern verification system. In the figure, (1) is layout pattern data, (2) is element recognition program, (3) is database, (4) is verification program, (5) is netlist file, (6) is wiring information file, (7) is ) indicates element recognition information data, and (8) indicates wiring information file data. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A layout pattern verification system for verifying an LSI layout pattern, characterized in that the system has a function of storing wiring information used in verification in a file separate from other layout pattern information.