JPH0319359A - Input protective circuit - Google Patents

Abstract

PURPOSE:To improve a semiconductor integrated circuit in layout efficiency by a method wherein the gates of the MOS transistors of an input protective circuit is made externally controllable. CONSTITUTION:As the gate electrodes of a P-channel type MOS transistor P1 and an N-channel type MOS transistor N1 are connected to a power source VDD and a ground GND through capacitors C1 and C2 respectively, when external input terminals V and G are in an open state, the gate voltages of the MOS transistors P and N are fixed to a VDD level and a GND level respectively. However, when an anomalous voltage, for instance, higher than a power voltage VDD is applied to an external input terminal IN, the P-channel type MOS transistor P1 is turned ON. By this setup, the anomalous voltage is discharged to a power voltage VDD. When an anormalous voltage lower than a ground voltage is applied to the external input terminal IN, the N-channel type MOS transistor N1 is turned ON and the anormalous voltage is discharged to the ground GND.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input protection circuit that is provided in an input section of a semiconductor integrated circuit and protects input against internal memory.

[Conventional technology Is it used as an input protection circuit for semiconductor integrated circuits? A circuit shown in FIG. 3 is known.

As shown in FIG. 3, a P-channel MOS transistor PQI and an N-channel MOS transistor N21 are connected in series between the power supply vDD and the ground GND. The gate electrode of the P-channel MOS transistor P21 is connected to the power supply VD+), and the gate electrode of the P-channel MOS transistor P21 is connected to the power supply VD+), and the gate electrode of the P-channel MOS transistor P21 is
The gate electrode of transistor N21 is connected to ground GND. The external input terminal IN is these P channel type M
It is connected to the commonly connected drain electrodes of the OS transistor P■ and the N-channel type MOS transistor N21.

In the input protection circuit configured in this manner, a P-channel type MOS transistor P21 and an N-channel type MOS transistor M
Using the diode effect and punch-through effect at the drain of the OS transistor N21, the external input terminal I
It is possible to prevent abnormal voltage from being input from N into the internal circuit that is the protected circuit.

For example, when an abnormal voltage higher than the power supply voltage is applied to the external input terminal IN, the abnormal voltage is discharged to the power supply VDD via the P-channel type MOS transistor P21. Further, when an abnormal voltage lower than the ground voltage is applied, the abnormal voltage is discharged to the ground GND via the N-channel MOS transistor N2l. This results in
The gate oxide film of the internal circuit can be protected from abnormal voltages generated during the assembly process of semiconductor integrated circuit devices.

[Problems to be Solved by the Invention] However, in the conventional input protection circuit described above, it is necessary to use a transistor with an extremely large area in order to discharge abnormal voltage.

However, the probability that an abnormal voltage will occur after a semiconductor integrated circuit device is mounted on a printed circuit board or the like is extremely low. Therefore, in actual use, although the input protection circuit hardly functions, it requires a large area, resulting in a problem that the layout efficiency of the semiconductor integrated circuit is poor.

The present invention has been made in view of such problems, and includes:
To provide an input protection circuit that can improve the layout efficiency of a semiconductor integrated circuit by adding other functions to the input protection circuit that protects an internal circuit from abnormal voltage applied to an external input terminal. With the goal.

[Means for Solving the Problems] An input protection circuit according to the present invention includes a P-channel MOS transistor connected between a power source and an external input terminal and having a gate connected to a first external terminal; an N-channel MOS transistor connected between the terminal and ground and having a gate connected to a second external terminal; a first capacitor connected between the first external terminal and the power supply; It is characterized by having a second capacitor connected between the second external terminal and ground.

[Operation] According to the present invention, when the first and second external terminals are open, the gate electrodes of the P-channel MOS transistor and the N-channel MOS transistor are connected between the power supply and the ground, respectively. Each of the gate electrodes is biased to a power supply level and a ground level via a capacitor.

Therefore, similar to conventional input protection circuits, when an abnormal voltage higher than the power supply voltage is input to the external input terminal, P
The channel type MOS transistor is turned on and the abnormal voltage is discharged to the power supply. In addition, if an abnormal voltage lower than the ground voltage is input to the external input terminal, the N-channel M
The OS transistor turns on and the abnormal voltage is discharged to ground. This protects the gates of the transistors in the internal circuit.

Furthermore, in actual usage conditions where the function of the input protection circuit is not required, by applying a specific voltage to the first and second external terminals and controlling the gate voltage of the MOS transistor, it is possible to control the voltage from the external input terminal. The signal level input to the internal circuit can be arbitrarily fixed. For this reason,
In addition to the input protection function, the input protection circuit can also be used, for example, as a circuit for controlling set/reset of internal circuits.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

? FIG. 1 is a circuit diagram showing an input protection circuit according to a first embodiment of the present invention. As shown in Figure 1, P-channel type M
OS transistor P. The source electrode of P-channel type MOS transistor P is connected to the power supply VOO, and the drain electrode of P-channel type MOS transistor P, together with the drain electrode of N-channel type MOS transistor N, is connected to external input terminal IN.

The source electrode of the N-channel MOS transistor N is connected to ground GND. P channel type MOS transistor P. The gate electrode of is connected to an external input terminal Vl, and a capacitor CI is connected between the external input terminal VI and a power supply VDD. A gate electrode of the N-channel MOS transistor N1 is connected to an external input terminal G1, and a capacitor C2 is connected between the external input terminal G2 and the ground GND.

According to the input protection circuit configured in this manner, the gate electrodes of the P-channel MOS transistor P and the N-channel MOS transistor NI are connected to the power supply V through the capacitors C and C2. 0 and the ground GND, so when the external input terminals Vr and Gr are open, the gate voltages of the MOS transistors Pl and NI are V, respectively.
Since it is fixed at the DD level and the GND level, it maintains an off state under normal voltage. However, if the external input terminal IN is connected to the power supply ■, for example. If an abnormal voltage higher than D is applied, the P channel type MO
S transistor P1 turns on. As a result, the abnormal voltage is discharged to the power supply VOO. In addition, if an abnormal voltage lower than the ground voltage is applied to the external input terminal IN, the N
The channel type MOS transistor N1 is turned on and the abnormal voltage is discharged to the ground GND. This protects the gates of the transistors in the internal circuit.

On the other hand, since the gate electrodes of the P-channel MOS transistor PI and the N-channel MOS transistor Nl are connected to external input terminals V and G, respectively, low level or high level signals are applied to the external input terminals VI and G1. By applying a voltage, is it applied to the internal circuit from the external input terminal IN? The potential can be fixed at a high level or a low level. Therefore, after a semiconductor integrated circuit including this input protection circuit is mounted on a printed circuit board or the like, this input protection circuit can function as a control circuit for the input state of the external input terminal IN. In addition,
When not using this function, use external input terminals V and G.
1 can be connected to the power supply VDD and ground GND, respectively, or can be used as an oven. Especially in the latter case,
The potential of external input terminals Vl and G is the power supply V via capacitors C1 and C2. D and ground GND.

FIG. 2 is a circuit diagram showing an input protection circuit according to a second embodiment of the present invention.

This embodiment is a MOS transistor P in the first embodiment.
．． ,N. This is an input protection circuit that connects multiple in parallel. As shown in FIG. 2, the power supply VD[, and the external input terminal IN.
,... IN. A P-channel MOS transistor P■. ...+PIN are connected respectively, and the external input terminals IN. ．．・・・． IN. , and the ground GND, there is an N-channel MOS transistor Nll+...
+N1n are connected to each other.

P-channel MOs transistor P1,...,P
1. Each gate electrode is connected to an external input terminal V1, and a capacitor CI is connected between this external input terminal V1 and a power supply VDD. Each gate electrode of the N-channel MOS transistors Nlll...INtn is connected to an external input terminal GI, and these external input terminals G,
A capacitor C2 is connected between the GND and the ground GND.

According to this embodiment, by controlling the external input terminal v1lGI, the external input terminals INK, . . . , IN. can be fixed at a desired potential at the same time, so it can be used to set or reset data stored in memories, counters, etc., and addresses for these.
It can be effectively used in test mode, etc.

Therefore, by substituting the input protection circuit of this embodiment for the NAND element or NOR element that is generally required for setting data, etc., the number of gate elements can be reduced by the number of data signal lines. . Thereby, a semiconductor integrated circuit device with improved layout efficiency can be obtained.

[Effects of the Invention] As explained above, according to the present invention, the gates of each MOS transistor of the input protection circuit, which conventionally only had an input protection function, can be controlled from the outside, so that the input state to the internal circuit can be controlled from the outside. can be controlled. Therefore, by substituting the input protection circuit as a theoretical circuit element such as a NAND element or a NOR element after chip mounting, the area occupied by these elements can be reduced.

Therefore, the layout efficiency of the semiconductor integrated circuit is improved, the chip can be made smaller, and the cost of the chip can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an input protection circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of an input protection circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional input protection circuit. It is a circuit diagram of a circuit. IN, INI, INn, V. ,G,; External input terminal,
Cl H C2; Capacitor, P++P+++P1 p2,; P channel type MOS transistor, NI+
N+t+ N+. + N 21 ; N-channel MO
S transistor

Claims (1)

[Claims] (1) A P-channel MOS transistor connected between a power supply and an external input terminal and having a gate connected to a first external terminal, and a P-channel MOS transistor connected between the external input terminal and ground and having a gate connected to a second external terminal. an N-channel MOS transistor connected to the terminal; a first capacitor connected between the first external terminal and the power source; and a first capacitor connected between the second external terminal and ground. 2. An input protection circuit comprising: 2 capacitors.