JPH03191567A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the plane area of a memory cell by a method wherein the surface on the inside of a groove formed in a semiconductor substrate is used as an isolation insulating film between memory cells and two capacity parts are formed on the inside of the groove. CONSTITUTION:A desired pattern is formed on a P-type silicon semiconductor substrate 1; after that, a perpendicular groove is formed; and an insulating film 2 to be used as an insulating isolation layer is formed on the inside of the groove and in one part of the substrate 1. A first conductor layer 3 to be used as an electrode of a capacity part is formed on the insulating film 2; a first dielectric layer 4 is formed on the first conductor layer 3; a second conductor layer 5 to be used as a capacity electrode of a definite potential is formed on the first dielectric layer 4; a second dielectric layer 6 is formed on the second conductor layer 5; and a third conductor layer 7 to be used as an electrode of a capacity part is formed on the second dielectric layer 6. Thereby, it is possible to reduce the area of a memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a MOS dynamic random access type semiconductor memory device.

[Conventional technology]

FIGS. 3(a) and 3(b) are a plan view and a sectional view of an example of a conventional semiconductor device.

A P-type silicon substrate 1 is separated by a filled oxide film 22, and an MO8 type transistor serving as a basic component of a memory cell and a trench-type capacitor portion serving as a capacitor electrode are formed in each of the separated active regions.

On the surface of the substrate inside the groove, there is an N-type conductor layer 2 that becomes a capacitor electrode.
3, a dielectric layer 24 is formed thereon, and a constant potential capacitor electrode 25 is further formed thereon.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the field oxide film 22, which serves as an insulating isolation region, and the m portion, which serves as a capacitor, are separated and independent, and for this reason, only a capacitor portion for one bit of the memory element can be formed in the trench portion. However, there is a drawback that it poses a problem when reducing the memory cell area.

Furthermore, the gap between the grooves is a PN junction separation in the semiconductor substrate,
Shortening the distance between the grooves also has the disadvantage that the withstand voltage between the grooves decreases.

[Means to solve the problem]

The semiconductor device of the present invention includes: - a groove provided on a conductive type semiconductor substrate; an insulating film provided on the inner surface of the groove and serving as an insulation isolation region; and an electrode provided on the insulating film and serving as a capacitive part. a first conductor layer; a first dielectric layer provided on the first conductor layer; and a second conductor provided on the first dielectric layer and serving as a constant potential capacitor electrode. a second dielectric layer provided on the second conductor layer, and a third conductor layer provided on the second dielectric layer and serving as an electrode of a capacitor section. ing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(2) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention;
Figure 2 is a plan view of Figure 1.

First, as shown in FIG. 1(a), the impurity concentration is 10'''
~lo P-type silicon semiconductor substrate 1 with about 16 atoms/tan
After forming a desired pattern thereon using photoresist technology, vertical grooves are formed by anisotropic drying and etching.

Next, as shown in FIG. 1(b), using selective oxidation technology, an insulating film 2 that becomes an insulating isolation layer with a thickness of about 400 nm is formed inside the trench and a part of the substrate under high-temperature oxidation conditions of about 1000°C. form.

Next, as shown in FIG. 1(e), after forming a first N+-doped conductor layer, a desired pattern is formed using photoresist technology, and anisotropic dry etching is performed. The first conductor layer 3 is thereby formed. Thereafter, a desired pattern is similarly formed using a combination of photoresist technology and etching.

Next, as shown in FIG. 1(d), an oxide film with a thickness of about 5 nm is formed on the first conductive layer 3, and this is applied on the first dielectric layer 4 and the second A conductor layer 5 is formed, then a 20th dielectric layer 6 is formed on the second conductor layer 5, a third conductor layer 7 is formed thereon, and then the above first dielectric layer 6 is formed. ~
At the same time, the surface of the third conductive layer is oxidized at about 1000° C. to form an oxide film 8 of about 200 nm,
1. An N-type first region IO is formed by diffusing N-type impurities into the silicon substrate 1 through the third conductor layer.

Next, as shown in FIG. 1(f), after forming the gate electrode 9, arsenic was accelerated at 50 keys.

A dose of about 5×10/cd is implanted into the surface of the semiconductor substrate, and then heat treatment is performed at a high temperature to form an N-type second region.

Next, as shown in FIG. 1(g), after forming an interlayer insulating film 12 by vapor phase growth, a contact window is provided on the N-type second region 11. Then, a thin aluminum film with a thickness of 1 μm is deposited by sputtering and patterned to form a data line 13, and then a protective film 14 with a thickness of 1 μm is formed by CVD to protect the device. do.

Through the above steps, a semiconductor device of the present invention as shown in FIG. 1(g) is obtained.

FIG. 2 and FIG. 3(a) are patterns designed using almost the same design criteria, and the portion 35 surrounded by the two-dot chain line is one cell unit (two bits). According to this, it can be seen that the cell area has been reduced by 2 (l) (28 μm2 →
224μmz).

Note that this is only a case of using the same design criteria as above; by reducing the dimensions of each part, it is possible to realize a smaller cell area. This has the effect of making it possible to reduce the cell area by about %.

〔Effect of the invention〕

As explained above, in the present invention, the inner surface of the groove provided on the semiconductor substrate serves as an isolation insulating film between memory cells, and furthermore, two capacitive parts corresponding to 2 bits are provided inside the groove. This has the effect of making it possible to significantly reduce the planar area of the memory cell.

[Brief explanation of drawings]

FIGS. 1(a) to (2) are cross-sectional views shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention, FIG. 2 is a plan view of FIG. 1(2), and FIG. a) and (b) are a plan view and a cross-sectional view of an example of a conventional semiconductor device. 1... P-type silicon substrate, 2... Insulating film, 3... First conductor layer, 4... First dielectric layer, 5... Second conductor layer, 6...
...Second dielectric layer, 7...Third conductor layer, 8...Oxide film, 9...Gate electrode, IO... ...N-type first region, 11...N
Mold second region, 12... Interlayer insulating film, 13...
...Data line, 14...Protective film, 22.
...Filled oxide film, 23...N-type conductor layer, 24...Dielectric layer, 25...Capacitor electrode.

Claims (1)

[Claims] a groove provided in a semiconductor substrate of one conductivity type; an insulating film provided on the inner surface of the groove and serving as an insulation isolation region; and a first conductive layer provided on the insulating film and serving as an electrode of a capacitive part. ,
a first dielectric layer provided on the first conductor layer;
a second conductive layer serving as a constant potential capacitor electrode provided on the first dielectric layer; a second dielectric layer provided on the second conductive layer; A semiconductor device comprising: a third conductor layer provided on the dielectric layer and serving as an electrode of a capacitor section.