JPH03191546A - Inspection of disconnection and short circuit of wiring of board - Google Patents

Inspection of disconnection and short circuit of wiring of board

Info

Publication number
JPH03191546A
JPH03191546A JP32964089A JP32964089A JPH03191546A JP H03191546 A JPH03191546 A JP H03191546A JP 32964089 A JP32964089 A JP 32964089A JP 32964089 A JP32964089 A JP 32964089A JP H03191546 A JPH03191546 A JP H03191546A
Authority
JP
Japan
Prior art keywords
board
terminals
wiring
terminal
disconnections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32964089A
Other languages
Japanese (ja)
Inventor
Naoki Kato
直樹 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP32964089A priority Critical patent/JPH03191546A/en
Publication of JPH03191546A publication Critical patent/JPH03191546A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To inspect a disconnection and a short circuit of an electrode line in a state that a board wiring has been positioned accurately on a joint board by a method wherein a first terminal to a third terminal, for positioning use, which have been connected to an inspection apparatus via a changeover device are installed on the joint board. CONSTITUTION:A first terminal to a third terminal 151 to 153 for positioning use are arranged in respectively prescribed positions on the surface of a joint board 11. The terminals 151 to 153 for positioning use are connected to an inspection apparatus 14 via a changeover device 16; a dislocation in the horizontal direction and the rotation direction of a TFT board can be detected by using the inspection apparatus 14. When the terminals 151 to 153 for positioning use become electrically conductive, an electric current is made to flow to individual electrode wiring from the inspection apparatus 14 in order to inspect whether a disconnection and a short circuit exist or not. Thereby, it is possible to easily inspect the disconnection and the short circuit of the electrode wiring in a state that a board has been positioned accurately on the joint board 11.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は例えばアクティブマトリックス型液晶表示装置
の゛rFT基板などの基板配線に形成されている電極配
線(ライン)の断線や短絡を検査する方法に関するもの
である。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for inspecting disconnections and short circuits in electrode wiring (lines) formed on a substrate wiring such as an `rFT substrate of an active matrix liquid crystal display device, for example. It is related to.

〔従来の技術〕[Conventional technology]

一般に、アクティブマトリックス型液晶表示装置は第4
図に示すようにTPT基板1と対向基板2との間に液晶
3を封入し、TPT基板1の表面にマトリックス状に配
列された画素電極4を薄膜トランジスタ(図示せず)に
より選択的にオンオフさせて画像を表示するように構成
されている。
Generally, active matrix type liquid crystal display devices have a fourth
As shown in the figure, a liquid crystal 3 is sealed between a TPT substrate 1 and a counter substrate 2, and pixel electrodes 4 arranged in a matrix on the surface of the TPT substrate 1 are selectively turned on and off by thin film transistors (not shown). It is configured to display images using

したがって、このようなアクティブマトリックス型液晶
表示装置のTPT基板1には、第5図に示すように薄膜
トランジスタ5をスイッチング動作させるためのゲート
電極ライン6およびドレイン電極ライン7がそれぞれT
PT基板1の縦方向および横方向に一定間隔でかつ互い
に絶縁されて形成されている。そして、これらの各電極
ライン6゜7の両端部にはそれぞれ引き出し端子3a、
gbが設けられ、TPT基板1の縦方向および8a方向
に一定間隔で配列されている。
Therefore, as shown in FIG. 5, the TPT substrate 1 of such an active matrix type liquid crystal display device has a gate electrode line 6 and a drain electrode line 7 for switching the thin film transistor 5, respectively.
They are formed at regular intervals in the vertical and horizontal directions of the PT substrate 1 and are insulated from each other. And, at both ends of each of these electrode lines 6°7, there are lead terminals 3a,
gb are provided and arranged at regular intervals in the vertical direction of the TPT substrate 1 and in the direction 8a.

ところで、このようなTPT基板1の電極ライン6.7
は製造過程で断線したり、短絡したりすることがあり、
電極ライン6.7に#T線や短絡が生じると薄膜トラン
ジスタ5が正常に動作しなくなる。このため、従来では
第6図に示すようにTPT基板1をゴムコネクタ等を介
して中11!基板11の上に置いてTPT基板1の動作
検査を行なっていた。すなわち、例えばゲート電極ライ
ン6の両端部に設けられた引き出し端T−8a、8bを
中継基板11上に配設された検査用端′T−12に重ね
合せ、この状態で図示しない検査装置から検査用端子1
2を通じてゲート電極ライン6に電流を流して断線及び
短絡の有無を検査していた。また、ドレイン電極ライン
7についても同様な方法で断線及び短絡の有無を検査し
ていた。
By the way, the electrode lines 6.7 of such TPT substrate 1
may be disconnected or shorted during the manufacturing process.
If a #T line or a short circuit occurs in the electrode lines 6 and 7, the thin film transistor 5 will not operate normally. For this reason, conventionally, as shown in FIG. 6, the TPT board 1 is connected to the middle 11! The operation of the TPT substrate 1 was tested by placing it on the substrate 11. That is, for example, the lead-out ends T-8a and 8b provided at both ends of the gate electrode line 6 are overlapped with the test end 'T-12 provided on the relay board 11, and in this state, the lead-out ends T-8a and 8b provided at both ends of the gate electrode line 6 are overlapped with the test end 'T-12 provided on the relay board 11, and in this state, the lead-out ends T-8a and 8b provided at both ends of the gate electrode line 6 are placed on top of the test end 'T-12 provided on the relay board 11. Inspection terminal 1
2 to the gate electrode line 6 to check for disconnections and short circuits. Further, the drain electrode line 7 was also inspected for disconnections and short circuits using a similar method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記のような方法によると、TPT基板
1に水平方向及び回転方向の位置ずれが生じていた場合
には引き出し端子8a、8bと検査用端子12とが重な
り合わなくなったり、あるいは引き出し端子8a、8b
が隣りの検査用端子12に跨がるなどの不具合が生じ、
断線及び短絡の有無を正確に検査することが困難であっ
た。
However, according to the above method, if the TPT board 1 is misaligned in the horizontal and rotational directions, the lead terminals 8a, 8b and the inspection terminal 12 may no longer overlap, or the lead terminal 8a may not overlap with the test terminal 12. ,8b
Problems such as straddling the adjacent test terminal 12 may occur.
It was difficult to accurately inspect for disconnections and short circuits.

本発明は上記のような問題点に鑑みてなされたもので、
その目的はTPT基板等の基板配線を中継基板上に正確
に位置決めした状態で電極ラインの断線短絡検査を行な
うことのできる基板配線の断線短絡検査方法を提供する
ことにある。
The present invention was made in view of the above-mentioned problems.
The object of the present invention is to provide a method for inspecting disconnections and short-circuits of substrate wiring, which can inspect electrode lines for disconnections and short-circuits while accurately positioning the substrate wiring such as a TPT substrate on a relay board.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決するために本発明は、表面に複数本の電
極配線を一定間隔で形成し、各電極配線の両端に引き出
し端子を設けた基板を、検査装置と接続した中継基板の
上に置き、前記6引き出し端子を前記中継基板上に配設
された検査用端子に重ね合わせ、前記検査装置から前記
各電極配線に電流を流して断線及び短絡の有無を検査す
る基板配線の断線短絡検査方法において、前記基板に互
いに接続した第1ないし第3のダミー端子を前記電極配
線の一端側に配列された引き出し端子群の両端部と前記
電極配線の他端側に配列された引き出し端子群の端部に
設けると共に、前記中継基板上に前記検査装置と切換え
回路を介して接続された第1ないし第3の位置合せ用端
子をそれぞれ所定位置に設け、これらの位置合せ用端子
が電気的に導通したとき前記検査装置から前記各電極配
線に電流を流して断線及び短絡の有無を検査するもので
ある。
In order to solve the above problems, the present invention places a board on which a plurality of electrode wires are formed at regular intervals on the surface and lead terminals are provided at both ends of each electrode wire on a relay board connected to an inspection device. , a method for inspecting disconnections and short circuits of circuit board wiring, in which the six lead-out terminals are superimposed on inspection terminals arranged on the relay board, and a current is passed from the inspection device to each of the electrode wirings to inspect the presence or absence of disconnections and short circuits. , the first to third dummy terminals connected to the substrate are placed at both ends of a group of lead-out terminals arranged on one end side of the electrode wiring and at an end of a group of lead-out terminals arranged on the other end side of the electrode wire. In addition, first to third alignment terminals connected to the inspection device via a switching circuit are provided on the relay board at predetermined positions, and these alignment terminals are electrically conductive. At this time, a current is passed through each of the electrode wirings from the inspection device to inspect for disconnections and short circuits.

〔作 用〕[For production]

すなわち、本発明に係る基板配線の断線短絡検査方法は
、基板に互いに接続した第1ないし第3のダミー端子を
それぞれ所定位置に設けると共に、中1!基板上に検査
装置と切換え器を介して接続された第1ないし第3の位
置合せ用端子を設けることにより、基板が中継基板に対
して水平方向及び回転方向にずれているかどうかを検出
できる。したがって、中継基板上の位置合せ用端子が互
いに電気的に接続したときに検査装置から検査用端子を
通じて各電極配線に電流を流すことにより、基板に断線
や短絡があるかどうかを正確に検査することができる。
That is, in the method for inspecting disconnections and short circuits of board wiring according to the present invention, first to third dummy terminals connected to each other are provided on the board at predetermined positions, and the middle 1! By providing the first to third positioning terminals connected to the inspection device via the switching device on the board, it is possible to detect whether the board is shifted in the horizontal direction and rotational direction with respect to the relay board. Therefore, when the alignment terminals on the relay board are electrically connected to each other, a current is sent from the inspection device to each electrode wiring through the inspection terminal, thereby accurately testing whether there is a disconnection or short circuit on the board. be able to.

〔実施例〕〔Example〕

以下、第1図〜第3図を参照して本発明の一実施例を説
明する。なお、第5図および第6図に示したものと同一
部分には同一符号を付して説明する。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. Note that the same parts as those shown in FIGS. 5 and 6 will be described with the same reference numerals.

第1図はTPT基板の平面図であり、このTPT基板1
には薄膜トランジスタ5をスイッチング動作させるため
のゲート電極ライン6およびドレイン電極ライン7がそ
れぞれTPT基板1の縦方向および横方向に一定間隔で
かつ互いに絶縁されて形成されている。これらの各電極
ライン6゜7の両端部には引き出し端子8a、8bが設
置、すられ、TFT基板1の縦方向および横方向に一定
間隔で配列されている。
FIG. 1 is a plan view of the TPT substrate, and this TPT substrate 1
Gate electrode lines 6 and drain electrode lines 7 for switching the thin film transistor 5 are formed at regular intervals in the vertical and horizontal directions of the TPT substrate 1 and insulated from each other. Output terminals 8a and 8b are provided at both ends of each of these electrode lines 6.degree.7, and are arranged at regular intervals in the vertical and horizontal directions of the TFT substrate 1.

また、前記TPT基板1には第1ないし第3のダミー端
子91.92 *  93がそれぞれ所定位置に設けら
れている。これらのダミー端子919□、93は短絡ラ
イン10a、10bを介して互いに接続しており、第1
および第2のダミー端子91,9□はゲート電極ライン
6の一端側に配列された引き出し端子群(図では引き出
し端子8a側)の両端部に、また第3のダミー端子93
はゲート電極ライン6の他端側に配列された引き出し端
子群(図では引き出し端子8b側)の端部にそれぞれ設
けられている。
Furthermore, first to third dummy terminals 91, 92*93 are provided at predetermined positions on the TPT substrate 1, respectively. These dummy terminals 919□, 93 are connected to each other via short circuit lines 10a, 10b, and the first
The second dummy terminals 91 and 9□ are located at both ends of a group of lead-out terminals arranged on one end side of the gate electrode line 6 (the lead-out terminal 8a side in the figure), and the third dummy terminal 93
are respectively provided at the ends of a group of lead-out terminals arranged on the other end side of the gate electrode line 6 (the lead-out terminal 8b side in the figure).

なお、TPT基板1には図ボを省略したが、互いに接続
した第4ないし第6のダミー端子がドレイン電極ライン
7の一端側に配列された引き出し端子群の両端部とドレ
イン電極ライン7の他端側に配列された引き出し端子群
の端部にそれぞれ設けられている。
Although the figure is omitted from the TPT substrate 1, the fourth to sixth dummy terminals connected to each other are arranged at both ends of a group of lead-out terminals arranged on one end side of the drain electrode line 7, and in addition to the drain electrode line 7. They are provided at each end of the pullout terminal group arranged on the end side.

第2図はTPT2!板の電極ラインに断線や短絡がある
かどうかを検査するための装置構成を示す図であり、中
継基板11の上面には複数個の検査用端子12がTFT
基板1の引き出し端子8a。
Figure 2 is TPT2! It is a diagram showing the configuration of an apparatus for inspecting whether there is a disconnection or short circuit in the electrode line of the plate, and a plurality of inspection terminals 12 are arranged on the top surface of the relay board 11.
Output terminal 8a of board 1.

8bと同一ピッチで配設されている。これらの検査用端
子12は中継基板11の両端部に設けられたコネクタ1
3a、13bを通じて検査装置14に接続しており、こ
の検査装置14でTFT基板1に断線や短絡があるかど
うかを検査するように構成されている。
They are arranged at the same pitch as 8b. These test terminals 12 are connected to the connectors 1 provided at both ends of the relay board 11.
It is connected to an inspection device 14 through 3a and 13b, and the inspection device 14 is configured to inspect whether there is a disconnection or a short circuit in the TFT substrate 1.

また、中継基板11の上面には第1ないし第3の位置合
せ用端子151,152,153がそれぞれ所定位置に
配設されている。これらの位置合せ用端子15+ 、1
52,1.53は切換え器16を介して検査装置14と
接続しており、この検査装置14でTFT基板1の水平
方向及び回転方向の位置ずれを検出できるようになって
いる。
Furthermore, first to third alignment terminals 151, 152, and 153 are arranged at predetermined positions on the upper surface of the relay board 11, respectively. These alignment terminals 15+, 1
52, 1, and 53 are connected to an inspection device 14 via a switch 16, and this inspection device 14 can detect positional deviations of the TFT substrate 1 in the horizontal direction and rotational direction.

このような構成において、ゲート電極ライン6の断線及
び短絡検査を行なう場合は、第3図に示すようにTFT
I板1をゴムコネクタ等を介して中継基板11の上に置
き、ゲート電極ライン6の両端部に設けられている引き
出し端子8a、8bを中継基板11上に配設された検査
用端子12の上に重ね合わせる。そして、切換え器16
を操作してTPT基板1に水平方向及び回転方向の位置
ずれがあるかどうかを検査装置14で検査する。
In such a configuration, when inspecting the gate electrode line 6 for disconnections and short circuits, as shown in FIG.
The I board 1 is placed on the relay board 11 via a rubber connector etc., and the lead terminals 8a and 8b provided at both ends of the gate electrode line 6 are connected to the test terminals 12 arranged on the relay board 11. Lay it on top. And the switch 16
The inspection device 14 inspects whether there is any positional deviation in the horizontal direction and rotational direction in the TPT substrate 1 by operating the .

このとき、TPT基板1に水平方向及び回転方向の位置
ずれかない場合には、TPT基板1のダミー端子91,
9□、93が中継基板11上の位置合せ用端子15.,
152,153に重なり合うので、位置合せ用端子15
.,152,153は互いに接続状態となる。したがっ
て、このとき検査装置14から検査用端子12を通じて
各ゲート電極ライン6に電流を流すことにより、TPT
基板1に断線や短絡があるかどうかをi′FWに検査す
ることができる。
At this time, if there is no positional deviation in the horizontal and rotational directions of the TPT substrate 1, the dummy terminals 91 of the TPT substrate 1,
9□, 93 are alignment terminals 15. on the relay board 11. ,
152 and 153, so aligning terminal 15
.. , 152, and 153 are connected to each other. Therefore, at this time, by passing current from the testing device 14 to each gate electrode line 6 through the testing terminal 12, the TPT
It is possible to check i'FW whether there is a disconnection or a short circuit in the board 1.

なお、上記実施例ではゲート電極ライン6の断線短絡検
査について述べたが、TPT基板1に設けられた第4な
いし第6のダミー端子(図示せず)を中継基板11上の
位置合せ用端子15115z、15qに重ね合わすこと
により、ドレイン電極ライン7の断線短絡検査を行なう
ことができる。また、本発明方法はTPT基板だけでな
く単純マトリックス型液晶表示装置の電極基板に形成さ
れているストライブ状電極についても同様の方法で断線
短絡検査を行なうことができる。さらに、本発明はIC
2!板等の断線短絡検査についても適用することができ
る。
In addition, although the above embodiment described the disconnection/short circuit inspection of the gate electrode line 6, the fourth to sixth dummy terminals (not shown) provided on the TPT substrate 1 are connected to the alignment terminals 15115z on the relay substrate 11. , 15q, it is possible to inspect the drain electrode line 7 for disconnections and short circuits. Furthermore, the method of the present invention can be used to inspect not only TPT substrates but also striped electrodes formed on electrode substrates of simple matrix liquid crystal display devices for disconnections and short circuits. Furthermore, the present invention provides an IC
2! It can also be applied to inspection of disconnections and short circuits of boards, etc.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、表面に複数本の電極配線
を一定間隔で形成し、各電極配線の両端に引き出し端子
を設けた基板を、検査装置と接続した中継基板の上に置
き、前記6引き出し端子を前記中継基板上に配設された
検査用端子に玉ね合わせ、前記検査装置から前記各電極
配線に電流を流して断線及び短絡の有無を検査する基板
配線の断線短絡検査方法において、前記基板に互いに接
続した第1ないし第3のダミー端子を前記電極配線の一
端側に配列された引き出し端子群の両端部と前記電極配
線の他端側に配列された引き出し端子群の端部に設ける
と共に、前記中継基板上に前記検査装置と切換え回路を
介して接続された第1ないし第3の位置合せ用端子をそ
れぞれ所定位置に設け、これらの位置合せ用端子が電気
的に導通したとき前記検査装置から前記各電極配線に電
流を流して断線及び短絡の白゛無を検査するものである
As explained above, in the present invention, a board on which a plurality of electrode wirings are formed at regular intervals on the surface and lead-out terminals are provided at both ends of each electrode wiring is placed on a relay board connected to an inspection device. 6. In a method for inspecting disconnections and short circuits of circuit board wiring, the lead-out terminals are connected to inspection terminals arranged on the relay board, and current is passed through each of the electrode wirings from the inspection device to inspect the presence or absence of disconnections and short circuits. , first to third dummy terminals mutually connected to the substrate are arranged at both ends of a group of lead-out terminals arranged at one end of the electrode wiring, and at ends of a group of lead-out terminals arranged at the other end of the electrode wiring. and first to third alignment terminals connected to the inspection device via a switching circuit are respectively provided at predetermined positions on the relay board, and these alignment terminals are electrically conductive. At this time, a current is passed from the inspection device to each of the electrode wirings to inspect for disconnections and short circuits.

(、たがって、基板を中m基板上に正確に位置決めした
状態で電極配線の断線短絡検査を容易に行なうことがで
き、検査能率の向上等を図ることができる。
(Thus, it is possible to easily inspect for disconnections and short circuits of the electrode wiring while accurately positioning the substrate on the medium-sized substrate, and it is possible to improve the inspection efficiency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は本発明に係る基板配線の断線短絡検査
方法を説明するための図で、第1図はTPT基板の下面
図、第2図は断線短絡検査装置の概略構成図、第3図は
同装置の作用説明図、第4図はアクティブマトリックス
型液晶表示装置の概略構成を示す断面図、第5図はTF
T基板の断面図、第6図は従来方法の説明図である。 1・・・TFT基板、4・・・画素電極、5・・・薄膜
トランジスタ、6・・・ゲート電極ライン、7・・・ド
レイン電極ライン、8a、8b・・・引き出し端子、q
、+  92 +  93・・・ダミー端子、11・・
・中継基板、12・・・検査用端子、13a、13b・
・・コネクタ、4・・・検査装置、  51 15□  53 ・・・位置 合せ用端子、 6・・・切換え器。
1 to 3 are diagrams for explaining the method for inspecting disconnections and short circuits in board wiring according to the present invention, in which FIG. 1 is a bottom view of a TPT board, FIG. 2 is a schematic configuration diagram of a disconnection and short circuit inspection device, Fig. 3 is an explanatory diagram of the operation of the device, Fig. 4 is a sectional view showing the schematic structure of an active matrix type liquid crystal display device, and Fig. 5 is a TF
A cross-sectional view of the T-substrate, FIG. 6, is an explanatory diagram of the conventional method. DESCRIPTION OF SYMBOLS 1... TFT substrate, 4... Pixel electrode, 5... Thin film transistor, 6... Gate electrode line, 7... Drain electrode line, 8a, 8b... Output terminal, q
, +92 +93...dummy terminal, 11...
・Relay board, 12...Test terminal, 13a, 13b・
...Connector, 4...Inspection device, 51 15□ 53...Positioning terminal, 6...Switching device.

Claims (1)

【特許請求の範囲】[Claims] 表面に複数本の電極配線を一定間隔で形成し、各電極配
線の両端に引き出し端子を設けた基板を、検査装置と接
続した中継基板の上に置き、前記各引き出し端子を前記
中継基板上に配設された検査用端子に重ね合わせ、前記
検査装置から前記各電極配線に電流を流して断線及び短
絡の有無を検査する基板配線の断線短絡検査方法におい
て、前記基板に互いに接続した第1ないし第3のダミー
端子を前記電極配線の一端側に配列された引き出し端子
群の両端部と前記電極配線の他端側に配列された引き出
し端子群の端部に設けると共に、前記中継基板上に前記
検査装置と切換え回路を介して接続された第1ないし第
3の位置合せ用端子をそれぞれ所定位置に設け、これら
の位置合せ用端子が電気的に導通したとき前記検査装置
から前記各電極配線に電流を流して断線及び短絡の有無
を検査することを特徴とする基板配線の断線短絡検査方
法。
A board on which a plurality of electrode wires are formed at regular intervals on the surface and lead-out terminals are provided at both ends of each electrode wire is placed on a relay board connected to an inspection device, and each lead-out terminal is placed on the relay board. In the method for inspecting disconnections and short circuits of a board wiring, the first to third electrodes connected to each other on the board are superimposed on the arranged inspection terminals, and current is passed from the inspection device to each of the electrode wirings to inspect the presence or absence of breaks and short circuits. A third dummy terminal is provided at both ends of the pull-out terminal group arranged on one end side of the electrode wiring and at an end of the pull-out terminal group arranged on the other end side of the electrode wiring, and a third dummy terminal is provided on the relay board. First to third alignment terminals connected to the inspection device via a switching circuit are provided at predetermined positions, and when these alignment terminals are electrically connected, a signal is transmitted from the inspection device to each of the electrode wirings. 1. A method for inspecting disconnections and short circuits in board wiring, characterized by testing the presence or absence of disconnections and short circuits by passing a current.
JP32964089A 1989-12-21 1989-12-21 Inspection of disconnection and short circuit of wiring of board Pending JPH03191546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32964089A JPH03191546A (en) 1989-12-21 1989-12-21 Inspection of disconnection and short circuit of wiring of board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32964089A JPH03191546A (en) 1989-12-21 1989-12-21 Inspection of disconnection and short circuit of wiring of board

Publications (1)

Publication Number Publication Date
JPH03191546A true JPH03191546A (en) 1991-08-21

Family

ID=18223602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32964089A Pending JPH03191546A (en) 1989-12-21 1989-12-21 Inspection of disconnection and short circuit of wiring of board

Country Status (1)

Country Link
JP (1) JPH03191546A (en)

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