JPH03191509A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device of a uniform characteristic having an excellent circuit element by forming alignment marks every time a pattern is formed and then locating the patterns in the following process on the basis of the alignment marks formed in the previous process. CONSTITUTION:Alignment marks 3b for a first semiconductor device formed simultaneously with a first pattern consisting of a diffusion layer 2 and alignment marks 2a, which are arranged parallel with the alignment marks 3b, for a second semiconductor device formed simultaneously with a second pattern consisting of a wiring layer 3 are formed on a principal face of a semiconductor substrate 1. A third pattern consisting of contact holes 4 is formed on the basis of the alignment marks 3b and 2a for first and second semiconductor devices. If for example light or a laser beam is scanned and applied to two alignment marks 3b and 2a, position information from the reflection thereof is obtained. Thereby a semiconductor device of a uniform characteristic having an excellent circuit element is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to a pattern structure formed on one principal surface of a semiconductor substrate.

[Conventional technology]

Normally, this type of semiconductor device is manufactured by overlapping multiple circuit patterns on one main surface of a semiconductor substrate.
In recent years, as the degree of integration has increased, the positional accuracy of these patterns has become increasingly strict.

FIG. 3 is a partial plan view of a semiconductor substrate showing an example of a conventional semiconductor device. Conventionally, in this type of semiconductor device, as shown in the figure, a diffusion layer 2 is first formed on a semiconductor substrate 1 using a first pattern by, for example, a photolithography method.
, and alignment marks 3c are formed simultaneously with the wiring layer 3 made of a polysilicon layer. Next, using the alignment mark 3C as a reference, a second pattern is positioned and exposed to form a contact hole 4. In this way, a plurality of patterns are positioned using a single alignment mark and are sequentially stacked to form an integrated circuit, thereby manufacturing a semiconductor device.

[Problem to be solved by the invention]

FIG. 4 is a partial plan view of a semiconductor substrate for explaining the conventional problems. However, in the conventional semiconductor device described above, when superimposing these multiple patterns,
Because alignment is performed using a single alignment mark as a reference, positional errors for each pattern overlap, resulting in, for example, misalignment between the wiring and the diffusion layer, which may result in circuit elements not being formed.
This method has the disadvantage that circuit elements with poor characteristics are formed.

In order to make it easier to understand the second problem, I will explain it with specific numerical values. First, as shown in FIG. 4, it is assumed that, for example, a diffusion layer 2 and a wiring layer 3 made of polysilicon, which is the gate of a MOS transistor, are formed on a semiconductor substrate 1, and further,
A semiconductor device in which a silicon oxide film and a photoresist film are formed thereon will be described.

Here, in the design of the semiconductor device shown in FIG. 4, for example, the dimension of the contact hole 4 in the X direction is 2.0 μm,
The dimension from the wiring layer 3 to the boundary of the diffusion layer 2 in the X direction of the diffusion M2 in which the contact hole 4 is formed is 3.
If μm, the distance X between the contact hole 4 and the wiring layer 3 and the distance y between the contact hole 4 and the boundary of the diffusion layer 2
is the same 0.5 μm. In this manner, the contact hole 4 is designed to be formed in the center of the diffusion layer 2.

With the above design values, for example, the alignment mark 3C shown in FIG. 3 described above is formed at the same time as the wiring layer 3 shown in FIG. 4 is formed, and the contact hole 4 is formed by this alignment mark 3c. Sometimes, if the wiring layer 3 and the diffusion layer 2 are not shifted from each other, they are formed at the above-mentioned design values.

However, if the wiring layer 3 is
If the contact hole 4 is deviated by, for example, 0.4 .mu.m in the direction, the distance X will be 0.5 .mu.m if the contact hole 4 is formed using the conventional alignment mark 3C.

This means that the distance y between the contact hole 4 and the boundary between the diffusion layer 2 is 0.1 μm. In other words, the contact hole 4 is formed in a biased manner with respect to the diffusion layer 2.

Also, the wiring layer 3 is 0°5μ in the X direction with respect to the diffusion layer 2.
When the contact hole 4 is shifted by m, the contact hole 4 overlaps the boundary of the diffusion layer 2, and a transistor is no longer formed.

An object of the present invention is to provide a semiconductor device that eliminates such drawbacks.

[Means to solve the problem]

A semiconductor device of the present invention has an alignment mark for a semiconductor device that serves as a position reference when forming a plurality of patterns on one main surface of a semiconductor substrate in an overlapping manner. a second semiconductor device alignment mark formed in parallel with the first semiconductor device alignment mark and formed simultaneously with the second pattern;
and a third pattern formed based on the first and second semiconductor device alignment marks.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a partial plan view of a semiconductor substrate for explaining one embodiment of the present invention. As shown in FIG. 1, this semiconductor device includes alignment marks 3b for a first semiconductor device formed on one main surface of a semiconductor substrate 1 at the same time as a first pattern made of a diffusion layer 2 shown in FIG. A second semiconductor device alignment mark is formed parallel to and parallel to the first semiconductor device alignment mark 3b, and is formed simultaneously with the second pattern made of the wiring layer 3 shown in FIG. The mark 2a and the first and second semiconductor device alignment marks 3b
and a third pattern consisting of contact holes 4 in FIG. 4 formed based on and 2a.

In this way, when the two alignment marks 3b and 2a are scanned and irradiated with, for example, light or laser light, position information can be obtained from the reflected light. From this, contacts 1 to holes 4 can be exposed and formed at positions where the distances X and y from the wiring layer 3 and the diffusion layer 2 shown in FIG. 4 are the same.

FIG. 2 is a partial plan view of a semiconductor substrate for explaining another embodiment of the present invention. In addition, this alignment mark can be replaced with the same alignment mark 3 as shown in FIG.
There is an advantage that positioning accuracy is further improved by arranging the patterns b and 2a and forming each pattern each time.

〔Effect of the invention〕

As explained above, in the present invention, an alignment mark is formed for each pattern formation, and pattern positioning in the subsequent process is performed based on a plurality of alignment marks formed in the previous process. This has the effect that a semiconductor device having uniform characteristics and excellent circuit elements can be obtained.

[Brief explanation of drawings]

FIG. 1 is a partial plan view of a semiconductor substrate for explaining one embodiment of the present invention, FIG. 2 is a partial plan view of a semiconductor substrate for explaining another embodiment of the present invention, and FIG. 3 is a partial plan view of a semiconductor substrate for explaining another embodiment of the present invention. FIG. 4 is a partial plan view of a semiconductor substrate showing an example of a conventional semiconductor device. FIG. 4 is a partial plan view of a semiconductor substrate for explaining the problems of the conventional device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffusion layer, 2a, 3b, 3
C... Alignment mark, 3... Wiring layer, 4... Contact hole.

Claims (1)

[Claims] A first alignment mark for a semiconductor device formed simultaneously with a first pattern in a semiconductor device having an alignment mark for a semiconductor device that serves as a position reference when forming a plurality of patterns overlappingly on one principal surface of a semiconductor substrate. a second alignment mark for a semiconductor device that is formed in parallel with the first alignment mark for a semiconductor device and formed simultaneously with the second pattern; and the first and second alignment marks for a semiconductor device. and a third pattern formed with reference to the alignment mark.