JPH03190223A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03190223A
JPH03190223A JP33044589A JP33044589A JPH03190223A JP H03190223 A JPH03190223 A JP H03190223A JP 33044589 A JP33044589 A JP 33044589A JP 33044589 A JP33044589 A JP 33044589A JP H03190223 A JPH03190223 A JP H03190223A
Authority
JP
Japan
Prior art keywords
film
wiring
layer
forming
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33044589A
Other languages
Japanese (ja)
Inventor
Kazuhiro Hoshino
和弘 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP33044589A priority Critical patent/JPH03190223A/en
Publication of JPH03190223A publication Critical patent/JPH03190223A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent generation of a junction leakage current and to reduce a contact resistance by forming an opening in an insulating film on a semiconductor substrate, so sequentially forming a tungsten film and a copper alloy film including metal for forming a reaction preventive film as to cover the substrate exposed in the bottom of the opening, and then heat treating it. CONSTITUTION:A field insulating film 2 made of SiO is formed on a substrate 1, and an electrode contact window 3 is formed in the film 2. Then, a W film 5 is formed in the window 3, a copper alloy file containing metal except tungsten is formed as an electrode.wiring layer 6, and then annealed. A barrier layer is formed in a 2-layer structure of a conventional W layer and a diffused barrier layer containing W of high barrier effect by the heat treatment, and the contact of the substrate 1 and the electrode.wiring is silicified. Thus, an ohmic contact having low contact resistance is obtained, mutual diffusion of the wiring 8 and a field oxide film SiO2 at the sidewall of the window 3 can be prevented to prevent pn junction leakage current.

Description

【発明の詳細な説明】 〔概要〕 半導体基板と電極・配線とのコンタクト窓内にバリアメ
タルを形成してなる半導体装置の製造方法に関し、銅或
いは銅合金からなる配線とSi、5i02との相互拡散
を防ぐためにバリア効果の高い2層構造からなる反応防
止膜を容易にかつカバレッジよ(形成して接合リーク電
流の発生を防止しかつ低いコンタクト抵抗が得られる半
導体装置の製造方法を提供することを目的とし、銅合金
からなる電極・配線層を有する半導体装置において、半
導体基板上に開口部を有する絶縁膜を形成する工程と、
少なくとも該開口部底面に露出した該半導体基板を覆う
ようにタングステン膜を形成する工程と、該タングステ
ン膜上に該タングステン膜と反応して該半導体基板もし
くは該絶縁膜のうち少なくとも1つと電極・配線層との
反応を防止する反応防止膜を構成する金属を含む銅合金
膜を形成する工程と、該タングステン膜と前記金属とが
反応してなる反応防止膜を形成すると共に該半導体基板
と該タングステン膜とが反応してなる反応層を形成する
ように熱処理を行う工程とが含まれていることを特徴と
するように構成するか、またはこのような構成において
窒素を含有するガス雰囲気中で熱処理を行うことにより
、前記銅合金膜上に前記金属を含有する窒化膜を形成す
る工程を含むことを特徴とするように構成する。
[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device in which a barrier metal is formed in a contact window between a semiconductor substrate and an electrode/wiring, the interconnection between a wiring made of copper or a copper alloy and Si, 5i02 is To provide a method for manufacturing a semiconductor device in which a reaction prevention film having a two-layer structure with a high barrier effect to prevent diffusion is formed easily and with good coverage, thereby preventing the occurrence of junction leakage current and obtaining low contact resistance. In a semiconductor device having an electrode/wiring layer made of a copper alloy, a step of forming an insulating film having an opening on a semiconductor substrate;
forming a tungsten film so as to cover at least the semiconductor substrate exposed at the bottom of the opening; reacting with the tungsten film on the tungsten film to connect at least one of the semiconductor substrate or the insulating film to the electrode/wiring; forming a copper alloy film containing a metal constituting a reaction prevention film that prevents reaction with the tungsten layer; forming a reaction prevention film formed by reacting the tungsten film with the metal; and a step of performing heat treatment to react with the film to form a reaction layer, or in such a structure, heat treatment in a nitrogen-containing gas atmosphere. The method is characterized in that it includes a step of forming a nitride film containing the metal on the copper alloy film by performing the above steps.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体基板と電極・配線とのコンタクト窓内
にバリアメタルを形成してなる半導体装置の製造方法に
関する。
The present invention relates to a method for manufacturing a semiconductor device in which a barrier metal is formed within a contact window between a semiconductor substrate and an electrode/wiring.

近年のLSI(Large  5cale  Inte
gration)の高集積化の要求に伴い配線が微細化
されサブミクロン領域における電極・配線のエレクトロ
・マイグレーションが問題になっている。このためエレ
クトロ・マイグレーション耐性の高い配線材料が求めら
れている。銅(CU)あるいは銅合金からなる電極・配
線は従来のアルミニウム(AI)配線に比べてエレクト
ロ・マイグレーション耐性が2桁以上高くかつ電気抵抗
も約1/2と低いので次世代の半導体装置における電極
・配線材料として有望視されている。しかし、従来のア
ルミニウム配線を形成する際に用いたプロセスを銅配線
形成の際に用いるとプロセス中の熱処理によって配線の
Cuが半導体基板のシリコン(Si)やフィールド酸化
膜の二酸化シリコン(SiOz)と容易に反応してしま
いCuもしくはCu合金とSi基板及びフィールド酸化
膜5in2との相互拡散のためpn接合を破壊すること
が懸念される。Cuはシリコン基板の拡散層中で正孔・
電子対発生の核となるため接合リーク電流を発生させる
原因になり、素子特性を劣化させてしまう。また、銅は
酸化され易いという問題もある。そこで、かかる不都合
を生しることなく銅または銅合金からなる電極・配線を
形成する方法が待望されている。
In recent years, LSI (Large 5cale
Along with the demand for higher integration in semiconductor devices, interconnections have become finer, and electromigration of electrodes and interconnections in the submicron region has become a problem. Therefore, a wiring material with high electromigration resistance is required. Electrodes and wiring made of copper (CU) or copper alloys have electromigration resistance that is two orders of magnitude higher than conventional aluminum (AI) wiring, and their electrical resistance is about 1/2 as low, making them suitable for electrodes in next-generation semiconductor devices.・It is seen as promising as a wiring material. However, when the process used to form conventional aluminum wiring is used to form copper wiring, the heat treatment during the process causes the Cu in the wiring to mix with silicon (Si) in the semiconductor substrate and silicon dioxide (SiOz) in the field oxide film. There is a concern that the Cu or Cu alloy reacts easily and the pn junction is destroyed due to interdiffusion between the Cu or Cu alloy, the Si substrate, and the field oxide film 5in2. Cu absorbs holes in the diffusion layer of the silicon substrate.
Since it becomes a nucleus for the generation of electron pairs, it becomes a cause of junction leakage current and deteriorates the device characteristics. Another problem is that copper is easily oxidized. Therefore, a method of forming electrodes and wiring made of copper or copper alloy without causing such disadvantages has been desired.

〔従来の技術〕[Conventional technology]

このため銅あるいは銅合金を配線材料として用いる場合
には銅あるいは銅合金とシリコン基板及びフィールド酸
化膜5i02との相互拡散を防止するために配線と基板
の間にタングステン(W)等の反応防止膜、すなわちバ
リア層を介在させ、また配線とシリコン半導体基板との
コンタクト界面にはチタン(Ti)膜等を形成してコン
タクト抵抗の低減を図っていた。
Therefore, when copper or copper alloy is used as a wiring material, a reaction prevention film such as tungsten (W) is formed between the wiring and the substrate to prevent mutual diffusion between the copper or copper alloy and the silicon substrate and field oxide film 5i02. That is, a barrier layer is interposed, and a titanium (Ti) film or the like is formed at the contact interface between the wiring and the silicon semiconductor substrate to reduce the contact resistance.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、バリア層としてWを用いた場合、配線材鋼ある
いは銅合金と基板St、フィールド酸化膜5i02との
バリア効果が充分に得られにくかった。なぜならば、W
膜は電極コンタクト窓内にスパッタリング法を用いて形
成されるが、特に電極コンタクト窓側壁に被着されるW
膜は薄くなってしまい、ここにおいて銅とフィールド酸
化膜Sio2との相互拡散が生じると、電極・配線はこ
の薄く形成された側壁W膜からフィールド酸化膜を通っ
て基板と電気的に接合してしまい、すなわち接合リーク
電流が発生し、素子特性を劣化させてしまう。このため
反応防止膜をTiN膜、ついでW膜と順次形成してバリ
ア性を上げる方法がとられていた。しかし、この方法は
工程が増えてしまう欠点を持っていた。特に、TiN膜
をスパッタ法で形成した場合、ステップカバレッジは悪
くなる。また、1層ずつスパッタリングを用いて形成す
るので、シャドウィング効果によって、しだいにステッ
プカバレッジが劣化してゆくため、やはりコンタクト窓
側壁からの接合リーク電流を防止できないという課題が
残されていた。
However, when W is used as the barrier layer, it is difficult to obtain a sufficient barrier effect between the wiring material steel or copper alloy, the substrate St, and the field oxide film 5i02. Because, W
The film is formed within the electrode contact window using a sputtering method, and in particular W is deposited on the side wall of the electrode contact window.
The film becomes thin, and when interdiffusion between copper and the field oxide film Sio2 occurs, electrodes and interconnects pass from this thinly formed sidewall W film through the field oxide film and are electrically connected to the substrate. In other words, junction leakage current occurs, degrading device characteristics. For this reason, a method has been adopted in which a TiN film and then a W film are sequentially formed as a reaction prevention film to improve barrier properties. However, this method had the drawback of increasing the number of steps. In particular, when the TiN film is formed by sputtering, the step coverage becomes poor. Furthermore, since each layer is formed by sputtering, the step coverage gradually deteriorates due to the shadowing effect, so there still remains the problem that junction leakage current from the side walls of the contact window cannot be prevented.

本発明は銅あるいは銅合金からなる配線とSi、5in
2との反応を防ぐためにバリア効果の高い二層構造から
なる反応防止膜を容易にかつカバレッジよく形成して接
合リーク電流の発生を防止しかつ低いコンタクト抵抗が
得られる半導体装置の製造方法を提供することを目的と
する。
The present invention uses wiring made of copper or copper alloy and Si, 5in.
Provided is a method for manufacturing a semiconductor device in which a reaction prevention film having a two-layer structure with a high barrier effect is easily formed with good coverage to prevent a reaction with 2, thereby preventing the occurrence of junction leakage current and obtaining low contact resistance. The purpose is to

〔問題を解決するための手段〕[Means to solve the problem]

本発明は、銅合金からなる電極・配線層を有する半導体
装置において、半導体基板上に開口部を有する絶縁膜を
形成する工程と、少なくとも該開口部底面に露出した該
半導体基板を覆うようにタングステン膜を形成する工程
と、該タングステン膜上に該タングステン膜と反応して
該半導体基板もしくは該絶縁膜のうち少なくとも1つと
電極・配線層との反応を防止する反応防止膜を構成する
金属を含む銅合金膜を形成する工程と、該タングステン
膜と前記金属とが反応してなる反応防止膜を形成すると
共に該半導体基板と該タングステン膜とが反応してなる
反応層を形成するように熱処理を行う工程とが含まれて
いることを特徴とするように構成する。またはこのよう
な構成において窒素を含有するガス雰囲気中で熱処理を
行うことにより、前記銅合金膜上に前記金属を含有する
窒化膜を形成する工程を含むことを特徴とするように構
成する。
In a semiconductor device having an electrode/wiring layer made of a copper alloy, the present invention includes a step of forming an insulating film having an opening on a semiconductor substrate, and a step of forming an insulating film with tungsten to cover at least the semiconductor substrate exposed at the bottom of the opening. a step of forming a film, and a metal forming a reaction prevention film on the tungsten film that reacts with the tungsten film to prevent reaction between the semiconductor substrate or at least one of the insulating films and the electrode/wiring layer. A process of forming a copper alloy film, forming a reaction prevention film formed by the reaction between the tungsten film and the metal, and heat treatment to form a reaction layer formed by the reaction between the semiconductor substrate and the tungsten film. The method is characterized in that it includes a step of performing the method. Alternatively, in such a structure, the method may include a step of forming a nitride film containing the metal on the copper alloy film by performing heat treatment in a gas atmosphere containing nitrogen.

すなわち、熱処理によってバリア層を従来のW層に加え
てバリア効果のより高いWを含む拡散バリア層との二層
構造にすることによって、銅あるいは銅合金のSi、や
SiO□への拡散を防止している。そして同時にその熱
処理によって基板と電極・配線とのコンタクト部にシリ
サイド層をつくってコンタクト抵抗の低減を図り、また
電極・配線上に保護膜を形成して酸化を防止している。
In other words, the diffusion of copper or copper alloy into Si or SiO□ is prevented by heat-treating the barrier layer to create a two-layer structure consisting of a conventional W layer and a diffusion barrier layer containing W, which has a higher barrier effect. are doing. At the same time, through the heat treatment, a silicide layer is created in the contact area between the substrate and the electrode/wiring to reduce contact resistance, and a protective film is formed on the electrode/wiring to prevent oxidation.

(作用〕 本発明によれば基板と電極・配線との反応を防ぐバリア
層を熱処理を用いて2層構造としたので、1層ずつ別々
に形成するよりも製造工程を簡略化できる。また、コン
タクト窓側壁においても熱処理によってステップカバレ
ッジのよい2層構造バリア層を一定の厚さ形成できるの
で、従来問題となっていたコンタクト窓側壁での電極・
配線とフィールド酸化膜5iOzとの相互拡散を防止で
きpn接合リーク電流の発生を防止できる。また、この
熱処理によって同時に半導体基板と電極・配線とのコン
タクト部をシリサイド化するので、低いコンタクト抵抗
を有するオーミック接触が得られる。また、この熱処理
を窒素含有雰囲気下で行うことによって同時に表面に窒
化膜を形成すれば電極・配線の酸化を防げる。
(Function) According to the present invention, the barrier layer that prevents reactions between the substrate and the electrodes/wirings is made into a two-layer structure using heat treatment, so the manufacturing process can be simplified compared to forming each layer separately. Since a two-layer barrier layer with good step coverage can be formed to a certain thickness on the side wall of the contact window by heat treatment, it is possible to form a barrier layer with a constant thickness of two layers on the side wall of the contact window, which has been a problem in the past.
Mutual diffusion between the wiring and the field oxide film 5iOz can be prevented, and pn junction leakage current can be prevented from occurring. Furthermore, since this heat treatment simultaneously silicides the contact portion between the semiconductor substrate and the electrode/wiring, ohmic contact with low contact resistance can be obtained. Further, if this heat treatment is performed in a nitrogen-containing atmosphere and a nitride film is simultaneously formed on the surface, oxidation of the electrodes and wiring can be prevented.

〔実施例〕〔Example〕

第1図は本発明の一実施例を説明するための半導体装置
の要部断面図である。以下、この図を参照しつつ説明す
る。第1図(a)は熱処理を施す前の様子を示している
。まず、半導体基板1として例えばp型St基板上に5
i02からなる厚さ例えば4000人程度O7ィールド
絶縁膜2を熱酸化法で形成する。次に、通常のフォトリ
ソグラフィ技術を用いてフィールド絶縁膜2の選択的ド
ライエツチングを行って電極コンタクト窓3を形成する
。尚、Si基板1には能動素子や受動素子などの一部を
なす不純物拡散領域が既に作りこまれているものとし、
記号4はオーミックコンタクトを採ることが必要な不純
物拡散領域を示している。次に、スパッタ法を用いて厚
さ例えば1000人程度0W膜5を形成し、引き続きス
パッタ法を用いて電極・配線M6としてタングステン以
外の金属を含む銅合金膜、例えばCu−チタン(Ti)
合金を厚さ例えば5000人形成する。尚、この場合の
Cu−Ti合金における組成はCuに対してTiが10
〔重量%〕である。この際、タングステン以外の金属と
してTiだけでなく他の金属を用いてもよい。例えば、
モリブデン(MO)が掲げられる。この後、窒素雰囲気
で600°C130分のアニールを行う。この様子を示
したものが第1図(b)である。この熱処理によってC
u−Ti合金膜6から界面に拡散したTiがW膜5と反
応し、バリア効果がWli5より高い拡散バリア層T 
i W 7が厚さ700〜800人形成される。この過
程においてCu−Ti合金IA6に含まれるTiは消費
されCu−Ti合金膜6は、はぼ純Cu膜8に変わる。
FIG. 1 is a sectional view of a main part of a semiconductor device for explaining one embodiment of the present invention. This will be explained below with reference to this figure. FIG. 1(a) shows the state before heat treatment. First, as a semiconductor substrate 1, for example, a p-type St substrate with 5
An O7 field insulating film 2 made of iO2 and having a thickness of, for example, about 4,000 layers is formed by thermal oxidation. Next, the field insulating film 2 is selectively dry etched using a conventional photolithography technique to form an electrode contact window 3. It is assumed that impurity diffusion regions forming part of active elements and passive elements have already been formed in the Si substrate 1.
Symbol 4 indicates an impurity diffusion region that requires ohmic contact. Next, a 0W film 5 having a thickness of, for example, about 1000 layers is formed using a sputtering method, and then a copper alloy film containing a metal other than tungsten, such as Cu-titanium (Ti), is formed as an electrode/wiring M6 using a sputtering method.
The alloy is formed to a thickness of, for example, 5000. In this case, the composition of the Cu-Ti alloy is such that Ti is 10% of Cu.
[% by weight]. At this time, other metals than Ti may be used as the metal other than tungsten. for example,
Molybdenum (MO) is listed. Thereafter, annealing is performed at 600° C. for 130 minutes in a nitrogen atmosphere. FIG. 1(b) shows this situation. By this heat treatment, C
Ti diffused from the u-Ti alloy film 6 to the interface reacts with the W film 5, forming a diffusion barrier layer T with a higher barrier effect than Wli5.
i W 7 is formed with a thickness of 700-800 people. In this process, Ti contained in the Cu--Ti alloy IA6 is consumed and the Cu--Ti alloy film 6 turns into a nearly pure Cu film 8.

これで電極・配線層6の抵抗を下げることができる。尚
、この反応でW層5の厚さはTiWの形成のためWが消
費されるので300人程度に減少する。この熱処理によ
って、TiW層7が形成されると同時に電極コンタクト
窓3内のシリコン基板1の表面ではシリコンとタングス
テンの反応が進行してタングステンシリサイド(WSi
x)膜9が形成されコンタクト抵抗を下げられる。この
ように、基板1とのコンタクトではCu層8とSt基板
1の間にTiW層7/W層5/WSix1i9がセルフ
ァラインで形成される。本発明では、アニールによって
TiW膜7形成とシリサイド化(WSix膜9形成)を
同時に行っているので製造工程を増やさずにすむ。また
、2Nバリア層を1層ずつ形成するよりもカバレッジの
よい反応防止膜を形成できる。また、この熱処理を窒素
雰囲気中で行えばCu−Ti合金膜6は雰囲気をなして
いる窒素とも反応し、Cu−Ti合金膜6表面に窒化チ
タン膜(図示せず)を形成できる。この膜で銅の電極・
配線層の酸化を防止できる。尚、窒化膜を形成する必要
がなければ、熱処理を真空中或いは不活性ガス雰囲気中
で行ってもよい。最後に、ドライエ・ンチング技術を用
いてW膜5、TiW膜7、Cu膜8のパターニングを行
い配線形状に加工する。この際、パタニングは熱処理前
に行ってもよい。尚、本発明では半導体基板1は必ずし
もシリコン基板に限定されるものではなく電極・配線材
となる銅或いは銅合金と反応を起こして銅が基板中に拡
散する可能性のある基板すべてに適用される。尚、本発
明において、エレクトロマイグレーション耐性の強い銅
からなる電極・配線を形成するのに出発材料としてCu
−Ti合金を採用した理由は、TiがWと反応してバリ
ア効果の高いTiW膜を形成し易いことに依るものであ
る。また、電極・配線層上に酸化防止膜としてTiNを
生成し易いことに依るものである。従って、バリア効果
の優れたTiW以外の層が形成できるのであれば電極・
配線材はCu−Ti合金に限定されない、もちろん、C
u−Ti合金膜にさらに他の元素を追加することも可能
である。また、Cu−Ti層6の下地にW層5を採用し
たのは不純物拡散層4と良好なオーミックコンタクトを
とるとともに基板Stと反応してWSixを生成し易い
ことに依るものである。また、本発明では反応防止膜7
とWSix膜9と表面の窒化膜を1回の熱処理で同時に
形成しているが、これらは別々に形成してもよい。例え
ば、まず、600°Cで反応防止膜とWSix膜を形成
した後、少し温度を上げて800°Cで熱処理を行い、
表面に窒化膜を形成する。こうすれば、それぞれの膜を
最適温度で形成できるので素子特性の向上が見込める。
This allows the resistance of the electrode/wiring layer 6 to be lowered. In this reaction, the thickness of the W layer 5 is reduced to about 300 because W is consumed to form TiW. Through this heat treatment, the TiW layer 7 is formed, and at the same time, a reaction between silicon and tungsten progresses on the surface of the silicon substrate 1 within the electrode contact window 3, resulting in tungsten silicide (WSi).
x) Film 9 is formed to reduce contact resistance. In this way, in contact with the substrate 1, the TiW layer 7/W layer 5/WSix1i9 is formed between the Cu layer 8 and the St substrate 1 in a self-aligned manner. In the present invention, the formation of the TiW film 7 and the silicidation (formation of the WSix film 9) are performed simultaneously by annealing, so there is no need to increase the number of manufacturing steps. Furthermore, a reaction prevention film with better coverage can be formed than by forming 2N barrier layers one by one. Further, if this heat treatment is performed in a nitrogen atmosphere, the Cu--Ti alloy film 6 reacts with nitrogen in the atmosphere, and a titanium nitride film (not shown) can be formed on the surface of the Cu--Ti alloy film 6. With this film, copper electrodes and
Oxidation of the wiring layer can be prevented. Note that if there is no need to form a nitride film, the heat treatment may be performed in a vacuum or in an inert gas atmosphere. Finally, the W film 5, TiW film 7, and Cu film 8 are patterned using dry etching technology to form a wiring shape. At this time, patterning may be performed before heat treatment. In the present invention, the semiconductor substrate 1 is not necessarily limited to a silicon substrate, but can be applied to any substrate in which there is a possibility that copper may react with copper or a copper alloy used as an electrode/wiring material and diffuse into the substrate. Ru. In addition, in the present invention, Cu is used as a starting material to form electrodes and wiring made of copper, which has strong electromigration resistance.
The reason for using the -Ti alloy is that Ti easily reacts with W to form a TiW film with a high barrier effect. This is also due to the fact that TiN is easily formed as an anti-oxidation film on the electrode/wiring layer. Therefore, if a layer other than TiW with excellent barrier effect can be formed, the electrode and
The wiring material is not limited to Cu-Ti alloy, of course, C
It is also possible to add other elements to the u-Ti alloy film. The reason why the W layer 5 is adopted as the base of the Cu--Ti layer 6 is that it has good ohmic contact with the impurity diffusion layer 4 and is easy to react with the substrate St to generate WSix. Further, in the present invention, the reaction prevention film 7
Although the WSix film 9 and the surface nitride film are formed simultaneously in one heat treatment, they may be formed separately. For example, first, after forming a reaction prevention film and a WSix film at 600°C, the temperature is slightly raised and heat treatment is performed at 800°C.
A nitride film is formed on the surface. In this way, each film can be formed at the optimum temperature, so that the device characteristics can be expected to be improved.

尚、本発明は多層配線にも応用可能である。なぜならば
、窒素雰囲気の熱処理によって形成された窒化膜が層間
絶縁層との反応防止膜としての役割を果たすからである
Note that the present invention can also be applied to multilayer wiring. This is because the nitride film formed by heat treatment in a nitrogen atmosphere serves as a reaction prevention film with the interlayer insulating layer.

〔効果〕〔effect〕

以上、説明したように本発明によれば銅合金からなる電
極・配線を有する半導体装置の製造において容易な工程
でカバレッジの良好な2層構造の反応防止膜を形成でき
るので半導体装置の製造・工程の簡略化に寄与し、また
半導体装置の信頼性向上にも寄与する。
As explained above, according to the present invention, a reaction prevention film having a two-layer structure with good coverage can be formed in a simple process in manufacturing a semiconductor device having electrodes and wiring made of a copper alloy. This contributes to the simplification of the semiconductor device, and also contributes to improving the reliability of the semiconductor device.

また、基板と電極・配線とのコンタクト抵抗を下げ、か
つ電極・配線の酸化を防ぎ酸化による高抵抗化を防止で
きるので半導体装置の高速化にも寄与する。
Furthermore, it reduces the contact resistance between the substrate and the electrodes/wirings, prevents oxidation of the electrodes/wirings, prevents high resistance due to oxidation, and contributes to speeding up semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明するための半導体装置
の要部断面図である。 図中、 に半導体基板 2:絶縁膜 3:電極コンタクト窓 4:不純物拡散領域 5:タングステン(W)層 6:電極・配線層 7:反応防止膜 8ニアニール後の電極・配線層 9:半導体基板とタングステン層との反応層/−57〉
FIG. 1 is a sectional view of a main part of a semiconductor device for explaining one embodiment of the present invention. In the figure, semiconductor substrate 2: insulating film 3: electrode contact window 4: impurity diffusion region 5: tungsten (W) layer 6: electrode/wiring layer 7: reaction prevention film 8 electrode/wiring layer after near-annealing 9: semiconductor substrate Reaction layer between and tungsten layer /-57〉
\

Claims (1)

【特許請求の範囲】 1、銅合金からなる電極・配線層を有する半導体装置に
おいて、半導体基板上に開口部を有する絶縁膜を形成す
る工程と 少なくとも該開口部底面に露出した該半導体基板を覆う
ようにタングステン膜を形成する工程と該タングステン
膜上に該タングステン膜と反応して該半導体基板もしく
は該絶縁膜のうち少なくとも1つと電極・配線層との反
応を防止する反応防止膜を構成する金属を含む銅合金膜
を形成する工程と 該タングステン膜と前記金属とが反応してなる反応防止
膜を形成すると共に該半導体基板と該タングステン膜と
が反応してなる反応層を形成するように熱処理を行う工
程とが含まれていることを特徴とする半導体装置の製造
方法。 2、窒素を含有するガス雰囲気中で熱処理を行うことに
より、前記銅合金膜上に前記金属を含有する窒化膜を形
成する工程を含むことを特徴とする請求項1記載の半導
体装置の製造方法。
[Claims] 1. In a semiconductor device having an electrode/wiring layer made of a copper alloy, a step of forming an insulating film having an opening on a semiconductor substrate and covering at least the semiconductor substrate exposed at the bottom of the opening. A step of forming a tungsten film, and a metal forming a reaction prevention film on the tungsten film that reacts with the tungsten film and prevents reaction between the semiconductor substrate or at least one of the insulating films and the electrode/wiring layer. a step of forming a copper alloy film containing the tungsten film, a reaction prevention film formed by the reaction between the tungsten film and the metal, and a heat treatment to form a reaction layer formed by the reaction between the semiconductor substrate and the tungsten film. A method for manufacturing a semiconductor device, comprising the steps of: 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a nitride film containing the metal on the copper alloy film by performing heat treatment in a gas atmosphere containing nitrogen. .
JP33044589A 1989-12-20 1989-12-20 Manufacture of semiconductor device Pending JPH03190223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33044589A JPH03190223A (en) 1989-12-20 1989-12-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33044589A JPH03190223A (en) 1989-12-20 1989-12-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03190223A true JPH03190223A (en) 1991-08-20

Family

ID=18232697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33044589A Pending JPH03190223A (en) 1989-12-20 1989-12-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03190223A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340426A (en) * 1998-03-24 1999-12-10 Rohm Co Ltd Semiconductor device and manufacture of the semiconductor device
CN101728357A (en) * 2008-10-17 2010-06-09 日立电线株式会社 Wiring structure and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340426A (en) * 1998-03-24 1999-12-10 Rohm Co Ltd Semiconductor device and manufacture of the semiconductor device
CN101728357A (en) * 2008-10-17 2010-06-09 日立电线株式会社 Wiring structure and method for fabricating the same

Similar Documents

Publication Publication Date Title
JP2700103B2 (en) Improved integrated circuit structure and method of forming improved integrated circuit structure
JP2915828B2 (en) Semiconductor wiring structure and method of manufacturing the same
US5312772A (en) Method of manufacturing interconnect metallization comprising metal nitride and silicide
US6157082A (en) Semiconductor device having aluminum contacts or vias and method of manufacture therefor
JP3104534B2 (en) Semiconductor device and its manufacturing method.
JPH07193024A (en) Semiconductor device and its manufacture
JP2600593B2 (en) Semiconductor device and manufacturing method thereof
JPH03190223A (en) Manufacture of semiconductor device
JP3375460B2 (en) Semiconductor device
JPH06204218A (en) Manufacturing method of semiconductor device
JPH04116953A (en) Semiconductor device provided with plated wiring layer and manufacture thereof
JP2626927B2 (en) Semiconductor device
JPH05102154A (en) Semiconductor device
JP2563317B2 (en) Method for manufacturing semiconductor device
KR100303796B1 (en) Method for forming metal interconnection of semiconductor device
JP3337758B2 (en) Method for manufacturing semiconductor device
JP3120471B2 (en) Method for manufacturing semiconductor device
JPH05102148A (en) Semiconductor device
KR0139599B1 (en) Mechod of forming metal wiring in semiconducotr device
JP2714847B2 (en) Method for manufacturing semiconductor device
JPH03165038A (en) Manufacture of semiconductor device
JPH05102156A (en) Semiconductor device
JPH05167063A (en) Ohmic electrode, its formation method and semiconductor device
JPS62165342A (en) Semiconductor device
JP3034348B2 (en) Semiconductor device and manufacturing method