JP3120471B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3120471B2
JP3120471B2 JP03124168A JP12416891A JP3120471B2 JP 3120471 B2 JP3120471 B2 JP 3120471B2 JP 03124168 A JP03124168 A JP 03124168A JP 12416891 A JP12416891 A JP 12416891A JP 3120471 B2 JP3120471 B2 JP 3120471B2
Authority
JP
Japan
Prior art keywords
film
copper
titanium
wiring
oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03124168A
Other languages
Japanese (ja)
Other versions
JPH04350938A (en
Inventor
和弘 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP03124168A priority Critical patent/JP3120471B2/en
Publication of JPH04350938A publication Critical patent/JPH04350938A/en
Application granted granted Critical
Publication of JP3120471B2 publication Critical patent/JP3120471B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、更に詳しくは、半導体装置に形成される銅配線
の酸化防止方法に係わる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing oxidation of a copper wiring formed on the semiconductor device.

【0002】[0002]

【従来の技術】近年、ULSIの高集積化に伴い、電極
配線は微細化傾向にある。電極配線材料としてはアルミ
ニウムあるいはアルミニウム系合金が多用されてきた
が、配線の線幅が減少するにつれて、エレクトロマイグ
レーションが厳しく、信頼性を保証することが難しくな
ってきている。そこで、アルミニウムに代る配線材料と
してモリブデン(Mo),タングステン(W)などの高
融点金属が試されているが、その抵抗はバルクでアルミ
ニウムの2倍以上と高く、薄膜ではさらに高い。従って
エレクトロマイグレーションに強く、低抵抗な材料が求
められている。そこで、アルミニウムに代わる配線材料
として銅(Cu)を用いることが考えられる。銅は、低
抵抗でエレクトロマイグレーションに強く、微細デバイ
スへの形成を可能にする。
2. Description of the Related Art In recent years, electrode wiring has been miniaturized in accordance with high integration of ULSI. Aluminum or an aluminum-based alloy has been frequently used as an electrode wiring material. However, as the line width of the wiring decreases, electromigration becomes severe and it becomes difficult to guarantee reliability. Therefore, refractory metals such as molybdenum (Mo) and tungsten (W) have been tried as a wiring material in place of aluminum, but the resistance is as high as twice or more that of aluminum in bulk and even higher in thin films. Therefore, a material that is resistant to electromigration and has low resistance is required. Therefore, it is conceivable to use copper (Cu) as a wiring material instead of aluminum. Copper has low resistance, is resistant to electromigration, and can be formed into fine devices.

【0003】しかしながら、銅配線がこれまでにデバイ
スに適用されなかった理由は、Cuが酸素を数%でも含
む雰囲気において、200℃程度の温度で酸化されるた
めであった。即ち、ウエハプロセスにおいては、CVD
法による絶縁膜形成・アニール等、Cu膜が高温で酸素
雰囲気に晒される工程を経るため、そこで酸化されてし
まうという問題を生じていた。例えば、Cu配線形成後
に絶縁膜としてCVD法によりSiO2膜を形成する場
合には、ウエハは例えばSiH4+N2Oガス中で基板温
度300℃〜400℃に晒される。このとき、Cuは反
応ガスに含まれる酸素によってCuは酸化される。ま
た、Cu配線形成後にアニールを行なう場合は、通常の
電気炉でN2を流し400℃〜700℃で行なわれる
が、炉内に存在する微量の残留酸素やSiO2膜中の酸
素(O)でCuは酸化されてしまう。Cuは、Alと異
なり表面に安定な酸化膜を作らないため、表面が酸素と
反応すると膜中に酸素が拡散し、酸化銅となって電気抵
抗は急激に上昇し配線として実用に適さないものとなっ
てしまう。
However, the reason that copper wiring has not been applied to devices so far is that Cu is oxidized at a temperature of about 200 ° C. in an atmosphere containing even a few percent of oxygen. That is, in the wafer process, CVD
Since the Cu film is subjected to a process of exposing it to an oxygen atmosphere at a high temperature, such as formation and annealing of an insulating film by a method, there has been a problem that it is oxidized there. For example, when a SiO 2 film is formed as an insulating film by a CVD method after the formation of Cu wiring, the wafer is exposed to a substrate temperature of 300 ° C. to 400 ° C. in, for example, SiH 4 + N 2 O gas. At this time, Cu is oxidized by oxygen contained in the reaction gas. When annealing is performed after the formation of the Cu wiring, the annealing is performed at 400 ° C. to 700 ° C. by flowing N 2 in a normal electric furnace. However, a small amount of residual oxygen existing in the furnace and oxygen (O) in the SiO 2 film Then, Cu is oxidized. Cu, unlike Al, does not form a stable oxide film on the surface, so when the surface reacts with oxygen, oxygen diffuses into the film and becomes copper oxide, the electrical resistance of which rises rapidly and is not suitable for practical use as wiring. Will be.

【0004】特開昭63−299250号公報記載の従
来技術は、Cu配線上にシリコンを堆積させ、酸素雰囲
気中で熱処理を施して銅−二酸化シリコン(Cu−Si
2)合金とする方法であり、Cu配線の酸化の防止を
図ったものである。
In the prior art disclosed in Japanese Patent Application Laid-Open No. 63-299250, silicon is deposited on a Cu wiring and heat-treated in an oxygen atmosphere to form copper-silicon dioxide (Cu-Si).
O 2 ) alloy is used to prevent oxidation of the Cu wiring.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな従来技術を用いても、Cu配線中にSiO2が含ま
れる構造となることや、Cu配線上に堆積させたシリコ
ンを酸素雰囲気中で熱処理するため、Cuは酸素と反応
する機会が多くなり、完全にCuの酸化を防止し得るも
のでなかった。そのため、Cu配線の有効な酸化防止方
法が要望されていた。
[SUMMARY OF THE INVENTION However, even with such prior art, or to become a structure that contains SiO 2 in the Cu wiring, the silicon deposited on the Cu wiring in an oxygen atmosphere heat treatment Therefore, Cu has a greater chance of reacting with oxygen and cannot completely prevent oxidation of Cu. Therefore, an effective method for preventing oxidation of Cu wiring has been demanded.

【0006】本発明は、このような従来の問題点に着目
して創案されたものであって、Cu配線の酸化が防止さ
れる半導体装置の製造方法を得んとするものである。
The present invention has been made in view of such conventional problems, and has as its object to obtain a method of manufacturing a semiconductor device in which oxidation of a Cu wiring is prevented.

【0007】[0007]

【課題を解決するための手段】そこで、本発明は、下地
基板上にチタン層と銅のエッチングと同一条件でエッチ
ング可能なバリヤメタルとを形成し、該バリヤメタル層
上に銅配線を形成し、該銅配線表面にチタン(Ti)膜
形成する工程と、熱処理により上記銅配線とチタン膜
とを反応させて銅チタン合金膜を形成する工程と、前記
銅(Cu)−チタン(Ti)系合金膜が形成された銅配
線上に、酸素(O)を構成成分とする絶縁膜を形成する
工程とを備えたことを、その解決方法としている。
SUMMARY OF THE INVENTION Accordingly, the present invention provides a method of etching a base substrate under the same conditions as those for etching a titanium layer and copper.
And a barrier metal layer,
A copper wiring is formed thereon, and a titanium (Ti) film is formed on the surface of the copper wiring.
Forming a, the copper wiring and a titanium film by a heat treatment
Forming a copper-titanium alloy film, and forming an insulating film containing oxygen (O) on the copper wiring on which the copper (Cu) -titanium (Ti) -based alloy film is formed. And a solution to the problem.

【0008】[0008]

【作用】銅配線の表面に銅−チタン合金膜を存在させる
ことによって、酸素(O)を構成成分とする絶縁膜(例
えばSOG膜,プラズマSiO2膜等)と銅の反応を抑
制する。即ち、銅−チタン合金膜中のチタン(Ti)
は、酸素をゲッタリングする作用があるため、高温処理
を経ても絶縁膜中の酸素はチタンと結合し、内部の銅と
は反応をしない。
The presence of the copper-titanium alloy film on the surface of the copper wiring suppresses the reaction between the insulating film (for example, SOG film, plasma SiO 2 film, etc.) containing oxygen (O) and copper. That is, titanium (Ti) in the copper-titanium alloy film
Has an action of gettering oxygen, so that oxygen in the insulating film is combined with titanium and does not react with copper inside even after high temperature treatment.

【0009】[0009]

【実施例】以下、本発明に係る半導体装置の製造方法の
詳細を図面に示す実施例に基づいて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to embodiments shown in the drawings.

【0010】(第1実施例)図1〜図5は、本発明の第
1実施例を示している。
(First Embodiment) FIGS. 1 to 5 show a first embodiment of the present invention.

【0011】本実施例は、先ず、素子を形成したシリコ
ン基板(図示省略)上にSiO2で成る酸化膜11を形
成した後、この酸化膜11の所定の位置にコンタクトホ
ール(図示省略)を開孔する。続いて、DCマグネトロ
ンスパッタリング法を用いてコンタクトメタルとしての
チタン(Ti)膜12を例えばÅの厚さに形成し、次
に、バリアメタルとしての窒化チタン(TiN)膜13
を例えば1000Åの厚さに形成する。
In this embodiment, first, an oxide film 11 made of SiO 2 is formed on a silicon substrate (not shown) on which elements are formed, and a contact hole (not shown) is formed at a predetermined position of the oxide film 11. Open a hole. Subsequently, a titanium (Ti) film 12 as a contact metal is formed to a thickness of, for example, Å using a DC magnetron sputtering method, and then a titanium nitride (TiN) film 13 as a barrier metal is formed.
Is formed to a thickness of, for example, 1000 °.

【0012】さらに、窒化チタン膜13上に、銅(C
u)膜14をDCマグネトロンスパッタリング法を用い
て例えば5000Åの厚さに形成する。
Further, on the titanium nitride film 13, copper (C
u) The film 14 is formed to a thickness of, for example, 5000 ° using a DC magnetron sputtering method.

【0013】そして、この銅膜14を例えば反応性イオ
ンエッチング(RIE)法を用いてパターニングする。
このエッチング条件は、以下に示す通りである。
The copper film 14 is patterned using, for example, a reactive ion etching (RIE) method.
The etching conditions are as shown below.

【0014】○エッチングガス…四塩化炭素(CC
4)−80%窒素(N2) ○圧力…0.02Torr ○基板温度…350℃ ○エッチングマスク…SiO2 なお、このような銅膜14のエッチング条件で、更に下
地の窒化チタン(TiN)膜13,チタン(Ti)膜1
2をエッチングすることが出来る。エッチング後、銅膜
14,窒化チタン膜13,チタン膜12は図1に示すよ
うな断面形状に加工される。
O Etching gas: carbon tetrachloride (CC
l 4 ) -80% nitrogen (N 2 ) O Pressure 0.02 Torr O Substrate temperature 350 ° C O Etching mask Sio 2 Under these etching conditions for the copper film 14, titanium nitride (TiN) as an underlayer is further added. Film 13, titanium (Ti) film 1
2 can be etched. After the etching, the copper film 14, the titanium nitride film 13, and the titanium film 12 are processed into a sectional shape as shown in FIG.

【0015】次に、図2に示すように、DCマグネトロ
ンスパッタリング法を用いてチタン(Ti)膜15を全
面に例えば500Åの厚さに形成する。
Next, as shown in FIG. 2, a titanium (Ti) film 15 is formed on the entire surface to a thickness of, for example, 500.degree. By using a DC magnetron sputtering method.

【0016】その後、例えば450℃,60秒のランプ
アニールを行ない、銅膜14とチタン膜15とを反応さ
せ、図3に示すように、銅膜14の周囲に銅チタン合金
(CuTiX)膜16を形成する。
Thereafter, lamp annealing is performed, for example, at 450 ° C. for 60 seconds to cause the copper film 14 and the titanium film 15 to react with each other. As shown in FIG. 3, a copper-titanium alloy (CuTi x ) film is formed around the copper film 14. 16 are formed.

【0017】次に、アンモニア過水で酸化膜11上の未
反応のチタン膜15を除去して、図4に示すような構造
にする。
Next, the unreacted titanium film 15 on the oxide film 11 is removed with ammonia peroxide to form a structure as shown in FIG.

【0018】次に、図5に示すように、絶縁膜としてS
OG(Spin On Glass;例えば東京応化製
OCD−Type7 16000T)膜18をスピンコ
ートし、400℃のキュアリングを施す。
Next, as shown in FIG. 5, S
An OG (Spin On Glass; for example, OCD-Type7 16000T manufactured by Tokyo Ohka) film 18 is spin-coated and cured at 400 ° C.

【0019】この際、従来の銅配線では、銅とSOGの
反応が生じるため銅が酸化され、抵抗が上昇して配線と
して実用に供されないものになっていた。しかし、本実
施例においては、以下に説明する作用によって銅配線は
酸化されない。
At this time, in the conventional copper wiring, a reaction between copper and SOG occurs, so that the copper is oxidized and the resistance is increased, so that the wiring is not practically used as a wiring. However, in this embodiment, the copper wiring is not oxidized by the operation described below.

【0020】銅膜14の表面に、銅チタン合金膜16を
存在させることによって、酸素(O)を構成成分とする
絶縁膜と銅の反応を抑制することができる。即ち、銅チ
タン合金膜16中のチタン(Ti)は酸素をゲッタリン
グする作用があるため、高温熱処理を行なうと、絶縁膜
中の酸素はチタンと結合し、内部の銅膜14の銅とは反
応しない。
The presence of the copper-titanium alloy film 16 on the surface of the copper film 14 can suppress the reaction between the insulating film containing oxygen (O) and copper. That is, since the titanium (Ti) in the copper-titanium alloy film 16 has an action of gettering oxygen, when the high-temperature heat treatment is performed, the oxygen in the insulating film is combined with the titanium and the copper in the internal copper film 14 no response.

【0021】従って、絶縁膜としてSOG膜18をスピ
ンコートし、400℃のキュアリングを施すと、図5に
示すように、銅膜14の上部及び側部に銅−チタンの化
合物と酸化チタン(TiO)の混合相を持った安定層
(Cu−Ti−TiO)17が形成されるので、内部の
銅膜(銅配線)14が酸化されることはない。
Therefore, when an SOG film 18 is spin-coated as an insulating film and cured at 400 ° C., a copper-titanium compound and titanium oxide (TiN) are formed on the upper and side portions of the copper film 14 as shown in FIG. Since the stable layer (Cu-Ti-TiO) 17 having the mixed phase of (TiO) is formed, the internal copper film (copper wiring) 14 is not oxidized.

【0022】(第2実施例)本実施例は、酸素(O)を
構成成分とする絶縁膜としてプラズマCVD法によって
形成されたSiO2を用いた例である。
(Second Embodiment) This embodiment is an example in which SiO 2 formed by a plasma CVD method is used as an insulating film containing oxygen (O) as a constituent.

【0023】先ず、本実施例においては、上記第1実施
例と同様の手順で、銅膜14の表面に銅チタン合金膜を
形成した後、プラズマCVD法によってSiO2膜19
を例えば7000Åの厚さに形成する。
First, in this embodiment, after a copper-titanium alloy film is formed on the surface of the copper film 14 in the same procedure as in the first embodiment, the SiO 2 film 19 is formed by plasma CVD.
Is formed to a thickness of, for example, 7000 °.

【0024】このSiO2膜19の形成条件は、以下に
示す通りである。
The conditions for forming the SiO 2 film 19 are as follows.

【0025】○反応ガス及びその流量 シラン(SiH4)…500SCCM 酸素(O2)…120SCCM ヘリウム(He)…3800SCCM ○圧力…1.3Torr ○形成温度…380℃ このようにして、SiO2膜19を形成した場合、図6
に示すような断面形状が得られる。ここでも、上記第1
実施例と同様の効果が得られる。
Reaction gas and its flow rate Silane (SiH 4 ): 500 SCCM oxygen (O 2 ): 120 SCCM Helium (He): 3800 SCCM Pressure: 1.3 Torr Formation temperature: 380 ° C. When the second film 19 is formed, FIG.
The cross-sectional shape as shown in FIG. Again, the first
The same effect as that of the embodiment can be obtained.

【0026】即ち、銅膜14の表面に銅チタン合金膜を
存在させることによって、SiO2と銅の反応を抑制す
ることができる。銅チタン合金膜中のチタン(Ti)は
酸素をゲッタリングする作用があるため、高温熱処理を
行なってもSiO2中の酸素はチタンと結合し、内部の
銅膜14とは反応しない。
That is, the presence of the copper-titanium alloy film on the surface of the copper film 14 can suppress the reaction between SiO 2 and copper. Since titanium (Ti) in the copper-titanium alloy film has an action of gettering oxygen, even in a high-temperature heat treatment, oxygen in SiO 2 is combined with titanium and does not react with the internal copper film 14.

【0027】従って、絶縁膜としてSiO2膜19を形
成したのち、図6に示すように銅膜(銅配線)14の上
部及び側面に銅−チタンの化合物と酸化チタン(Ti
O)の混合相をもった安定層17が形成される。
Therefore, after forming the SiO 2 film 19 as an insulating film, a copper-titanium compound and titanium oxide (Ti) are formed on the upper and side surfaces of the copper film (copper wiring) 14 as shown in FIG.
The stable layer 17 having the mixed phase of O) is formed.

【0028】以上、2つの実施例について説明したが、
本発明は、これらに限定されるものではなく、各種の銅
配線の構造に適用し得るものである。
The two embodiments have been described above.
The present invention is not limited to these, but can be applied to various copper wiring structures.

【0029】[0029]

【発明の効果】本発明においては、下地基板上にチタン
層と銅のエッチングと同一条件でエッチング可能なバリ
ヤメタルとを形成し、該バリヤメタル層上に銅配線を形
成し、該銅配線表面にチタン(Ti)膜を形成する工程
と、熱処理により上記銅(配線)膜とチタン膜とを反応
させて銅チタン合金膜を形成する工程と、前記銅(C
u)−チタン(Ti)系合金膜が形成された銅配線上
に、酸素(O)を構成成分とする絶縁膜を形成する工程
とを備えたものであるから、銅配線の表面に銅−チタン
系合金膜を存在させることによって、酸素(O)を構成
成分とする絶縁膜と銅の反応を抑制する効果がある。即
ち、銅−チタン系合金膜中のチタンが酸素をゲッタリン
グするため、高温熱処理を経ても絶縁膜中の酸素はチタ
ンと結合し内部の銅とは反応しない。このため、本発明
は銅配線を超LSIの配線として実用化させ得る効果が
ある。
According to the present invention, titanium on a base substrate
Burr that can be etched under the same conditions as layer and copper etching
And a copper wiring on the barrier metal layer.
Forming a titanium (Ti) film on the surface of the copper wiring , and reacting the copper (wiring) film with the titanium film by heat treatment.
Forming a copper-titanium alloy film, and the copper (C
u)-forming an insulating film containing oxygen (O) on the copper wiring on which the titanium (Ti) -based alloy film is formed. The presence of the titanium-based alloy film has an effect of suppressing a reaction between copper and an insulating film containing oxygen (O) as a component. That is, since the titanium in the copper-titanium-based alloy film getster oxygen, the oxygen in the insulating film is combined with the titanium and does not react with the copper inside even after the high-temperature heat treatment. Therefore, the present invention has an effect that the copper wiring can be put to practical use as the wiring of the VLSI.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例の工程を示す断面図。FIG. 1 is a sectional view showing a process of a first embodiment of the present invention.

【図2】本発明の第1実施例の工程を示す断面図。FIG. 2 is a cross-sectional view showing the steps of the first embodiment of the present invention.

【図3】本発明の第1実施例の工程を示す断面図。FIG. 3 is a sectional view showing a step of the first embodiment of the present invention.

【図4】本発明の第1実施例の工程を示す断面図。FIG. 4 is a sectional view showing a step of the first embodiment of the present invention.

【図5】本発明の第1実施例の工程を示す断面図。FIG. 5 is a sectional view showing a step of the first embodiment of the present invention.

【図6】本発明の第2実施例の断面図。FIG. 6 is a sectional view of a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11…酸化膜、12…チタン膜、13…窒化チタン膜、
14…銅膜、15…チタン膜、16…銅チタン合金膜、
17…安定層。
11: oxide film, 12: titanium film, 13: titanium nitride film,
14: copper film, 15: titanium film, 16: copper-titanium alloy film,
17 ... stable layer.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 下地基板上にチタン層と銅のエッチング
と同一条件でエッチング可能なバリヤメタルとを形成
し、該バリヤメタル層上に銅配線を形成し、該銅配線表
面にチタン(Ti)膜を形成する工程と、熱処理により上記銅配線とチタン膜とを反応させて銅チ
タン合金膜を形成する工程と、 前記銅(Cu)−チタン(Ti)系合金膜が形成された
銅配線上に、酸素(O)を構成成分とする絶縁膜を形成
する工程とを備えたことを特徴とする半導体装置の製造
方法。
1. A method for etching a titanium layer and copper on an undersubstrate.
Forms a barrier metal that can be etched under the same conditions as
Forming a copper wiring on the barrier metal layer;
Forming a titanium (Ti) film on the surface , and reacting the copper wiring with the titanium film by heat treatment to form a copper film.
Forming a tungsten alloy film; and forming an insulating film containing oxygen (O) as a component on the copper wiring on which the copper (Cu) -titanium (Ti) -based alloy film is formed. A method for manufacturing a semiconductor device, comprising:
JP03124168A 1991-05-29 1991-05-29 Method for manufacturing semiconductor device Expired - Fee Related JP3120471B2 (en)

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JP03124168A JP3120471B2 (en) 1991-05-29 1991-05-29 Method for manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
JP03124168A JP3120471B2 (en) 1991-05-29 1991-05-29 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04350938A JPH04350938A (en) 1992-12-04
JP3120471B2 true JP3120471B2 (en) 2000-12-25

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0179822B1 (en) * 1995-04-01 1999-04-15 문정환 Interconnections structure of semiconductor device and method for manufacturing thereof
EP3028549B1 (en) * 2013-07-29 2018-06-13 Ferro Corporation Conductive trace and method of forming conductive trace

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