JPH03189991A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a memory device having high speed data transmission, and having a parallel/serial converting function by incorporating a first path outputting the data of a first bit, and a second path, etc., outputting the data of the second and subsequent bits, setting shorter the signal transmission time of the first path than the signal transmission time of the second path. CONSTITUTION:In a multiplexer 12a, the data D0-D14 of the least significant bit - a 14th bit among the output data of a memory part 9 are conducted out to an output terminal 70, respectively through the four gate circuits from any one among NAND gates 32-46 to the NAND gate 83. On the other hand, the data D15 of the least significant bit through the NAND gate 82 and the NAND gate 83 is conducted out to the output terminal 70. Consequently, the time until the data D15 of the least significant bit is transmitted to the output terminal 70 is shortened compared with usual time. In such a manner, the semiconductor memory device having the parallel/serial converting function and increasing the operation speed without complicating the internal constitution of the device is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that serially outputs data read out in parallel from a memory section.

[Prior Art] Semiconductor storage devices having a parallel/serial conversion function for converting parallel input data into serial data and outputting the serial data are often used in line memories used in page printers and the like. Line memory is for both TV images 1
The image of the scanning line is temporarily stored, and the stored data is read out for each scanning line at a predetermined cycle in order to reproduce the image.

FIG. 4 is a schematic block diagram of a conventional semiconductor memory device that serially outputs data read out in parallel from a memory section.

Referring to FIG. 4, this semiconductor memory device includes an input clock terminal 1 to which an input clock signal CKIN is input, an output clock terminal 2 to which an output clock signal CKoUT is input, the input clock terminal CKIN and the output clock. The clock selection circuit 3 selectively outputs one of the signals CKOUT. This semiconductor storage device is
Further, in synchronization with the output of the clock selection circuit 3, a 4-bit counter 4 outputs a data select signal and a carry signal, and an m-bit counter 7 (m is any natural number) outputs an address signal. an input data terminal 10 to which 16-bit parallel data is input; a write control input terminal 11 to which a write control signal is input;
It includes a memory section 9 in which input and output data are both in parallel format.

The write control signal has two levels, high level and low level.
Take two logical levels. When the write control signal takes one of the two logic levels, this semiconductor storage device enters a write mode in which data can be written into the memory section 9, and the write control signal takes one of the two logic levels. When taking the other level, this semiconductor memory device can read data from the memory section 9.
mode.

The memory section 9 includes a memory cell array, and when the write control signal indicates write mode, the 16-bit parallel data from the manual data terminal 10 corresponds to the address signal from the m-bit counter 7. When the write control signal indicates the read mode, the 16-bit notators D15 to Do stored there are read from the address corresponding to the address signal from the m-bit counter 7 and output in parallel. .

This semiconductor memory device further includes 16-bit parallel data D1 read from the memory section 9 in the read mode.
A multiplexer 12b serially outputs 5 to Do one bit at a time in response to a data select signal from a 4-bit counter 4, and an output clock signal CKOUT from a tarok selection circuit 3 to output the data output from the multiplexer 12b. A D-type flip-flop circuit 13 (abbreviated as FF in the figure) that captures and outputs in response to
It includes a serial data output terminal 14 for outputting the data outputted by the flip-flop circuit 13 to the outside.

Specifically, the 4-bit counter 4 uses 4-bit data F as an initial count value. (H indicates hexadecimal), and the input clock signal CK from the clock selection circuit 3
IN or output clock signal CKOUT is counted, and the count value is counted down one by one from the initial value. The 4-bit counter 4 then outputs the count value in parallel as 4-bit data. This 4-bit data is the data select signal. Furthermore, when the 4-bit data becomes Oll, that is, when the clock signal is counted 16 times, the 4-bit counter 4 resets the count value to FH the next time the clock signal is counted, and the m-bit counter 7
Set the logic level of the carry signal to high level.

Therefore, the data select signal applied to the multiplexer 12b is 4-pit I. data that repeats FH-Q. Multiplexer 1.2 in read mode
b corresponds to the input data selector signal so that the 4-bit data configuring the data select signal and the data of each bit configuring the data D15 to DO in the memory section 9 correspond one-to-one. bit data (D
15 to DO). on the other hand,
The carry signal becomes high level every time the data select signal becomes data 0H.

Specifically, the m-bit counter 7 counts the clock signal from the clock selection circuit 3 and outputs the count value in parallel as m-bit data. This m-bit data is the address signal. Further, when the carry signal from the 4-bit counter 4 is at a high level, the m-bit counter 7 is activated by the clock selection circuit 3.
The address signal is incremented by one in response to a clock signal from. That is, the address signal specifying the address of the memory section 9 is incremented each time the 4-bit data, which is the data select signal, returns to F.

As a result, in the read mode, 16 bits of data are sequentially read out from each address specified by the address signal in the memory section 9, and in the write mode, the data input from the data input terminal 10 is read out in the memory section 9 in 16 bits.
Each bit is allocated to one address and stored.

In the read mode, the multiplexer 12b performs parallel/serial conversion on 16-bit data read from each address specified by the address signal in the memory section 9.

Note that the clock selection circuit 3 operates in accordance with changes in the write control signal from the write control input terminal 11.
Controlled by a predetermined circuit section (not shown), when the write control signal indicates the write mode, the input clock signal CK1. Outputs
When the write control signal instructs the read mode, the output clock signal CI (OUT
Output. Therefore, in the read mode, the data of the data select signal and the data of the address signal change in synchronization with the output clock signal CI (OUT.Similarly, in the write mode, the data of the address signal changes in synchronization with the input clock signals CK and H. and change.

FIG. 5 is a circuit diagram showing the internal configuration of multiplexer 12b. Referring to FIG. 5, this multiplexer consists of 4
Inverters 21, 22, 23, . and 24, and five-manpower NAND gates 31 to 46 (NAND gates 35 to 45 are omitted in the figure).

The NAND gate 31 receives the four bits of data and the 16 bits of data DO output from the memory section 9.
The data D15 of the most significant bit of ~D15 is received as input.

The NAND gate 32 outputs the inverted data of the least significant bit of the data select signal, the data of the first, second, and most significant bits of the data select signal, and the output data DO to D15 of the memory section 9. my first
The data of the third bit D14 is received as input.

Similarly, the NAND gate 33 outputs the inverted data of the first bit of the data select signal, the data of the least significant bit, second bit, and most significant bit of the data select signal, and the output data DO~ of the memory section 9. The data D13 of the 13th bit of D1.5 is received as input.

In this way, each of the NAND gates 31 to 46 receives data of any one bit of the output data of the memory section 9 as is or in an inverted form. Therefore, the output of each of the NAND gates 31 to 46 remains unchanged.
Alternatively, if at least one of the bits of data of the inverted and inputted data select signal is at a low level, it becomes a high level regardless of the logical value of the data provided from the memory section 9. Therefore, NAND gate 3
Each of 1 to 46 can invert one bit of the output data of the memory section 9 only when all the data of each bit of the data select signal inputted as is or inverted is at a high level. Output.

For example, the NAND gate 31 can output D15, one of the output data of the memory section 9, when all the data of each bit of the data select signal is "1", that is,
This is when the data select signal is data F8. NAN
The D gate 32 can output D14, one of the output data of the memory 0 section 9, by using the most significant bit, the first bit, and the When the data of the second-order bits are all "1" and the data of the least significant bit of the data select signal that is inverted and input to the NAND gate 32 is also "1", that is, the data select signal is data E. It's time.

In this way, the 16 NAND gates 31 to 46 operate on the memory section 9 in response to mutually different data select signals.
The state is such that the output data can be output. The data select signal is 4-bit data that sequentially takes on 16 values as described above.

Therefore, the 16 NAND gates 31 to 46 select the output data D of the memory section 9 according to the data select signal.
The data of each bit of O to D15 is sequentially output. In this example, the data select signal is data FH+EH
*...+(Since it changes in the order of 1H, 16 NA
The ND gates are NAND gate 1 31, 32. The data output from the memory unit 9 is inverted and output in the order of 3B, . . . , 46.

The multiplexer 12b further includes NAND gates 31 to 31 which respectively output data D15 to D12 from the most significant bit to the 12th bit of the output data of the memory 9.
4-person NAND gate 5 that receives 34 outputs as input
1, a four-man power NAND gate 52 which receives as input the outputs of NAND gates 35 to 38 which respectively output data D11 to D8 from the 11th bit to the 8th bit of the output data of the memory section 9; a four-man power NAND gate 53 which receives as input the outputs of NAND gates 39 to 42 which respectively output data D7 to D4 from the 7th bit to the 4th bit of the output data of the section 9;
A NAN that outputs data D3 to DO from the third bit to the least significant bit of the output data of the memory section 9.
4-person power N that receives the outputs of D gates 43 to 46 as input
AND gate 54 (in the figure, human input signal lines to NAND gates 52 to 54 are partially or completely omitted).

At least one of the outputs of the four NAND gates 31 to 3435 to 38, 39 to 42, and 43 to 46, which are human signal sources for the NAND gates 51 to 54, is at a low level ( Logical value “0”
), it becomes a high level (logical value "1") regardless of the output logical values of the other three NAND gates. However, each of the outputs of NAND gates 51-54 has a corresponding 4
If all three of the outputs of the two NAND gates are at high level, it is determined by one other logical value.

When the data select signal and the output data of the memory section 9 are applied to the multiplexer 12b, the NAND gates 31 to 46 operate as described above.
The gates 31 to 46 sequentially enter a state in which the output data of the memory section 9 can be outputted one by one. That is, the data select signal instructs the 16 NAND gates 31 to 46 to sequentially output data. Of the four NAND gates 31 to 46, all of the NAND gates that are not in a state where they can output the output data of the memory section 9 output a high level. Therefore, in the multiplexer 12b that receives the data select signal and the output data of the memory section 9, the NAND gates 51 to 54 operate as follows.

For example, the data select signal is data "1111"
(FH), the outputs of the NAND gates 32 to 46 other than the NAND gate 31 are all fixed at high level. Therefore, in this case NAN
The output of the NAND gate 31 is inverted and outputted from the NAND gate 51 which receives the output of the D gate 31 as an input.

Here, the output of the NAND gate 31 is the inverted data of one of the output data D15 of the memory section 9.

Therefore, the most significant bit data D15 of the output data of the memory section 9 is outputted from the NAND gate 51 in its original form without being inverted.

On the other hand, the other NAs among the four NAND gates 51 to 54
The outputs of ND gates 52-53 are all fixed at the low 4 level. Similarly, if the data selector signal is data "1110" (EH), the outputs of the NAND gates 31 and 33 to 46 other than the NAND gate 32 are always at high level.
NAND gates 51, 53 that do not receive the output of
．． and 54 are all fixed at low level.

Then, data D14 of the 14th-order bit of the output data of the memory section 9 is outputted from the NAND gate 52 which receives the output of the NAND gate 32 as an input.

In this way, each bit of data constituting the output data of the memory section 9, which appears sequentially in the outputs of the NAND gates 31 to 46, is transmitted to any one of the NAND gates 51 to 54.
appears in two outputs.

This multiplexer 12b further includes a four-person NOR gate 61 that receives the outputs of the NAND gates 51 to 54 as inputs, an inverter 62 that inverts the output of the NOR gate 61, and an output of the inverter 62 that is connected to the flip-flop circuit in FIG. 5) and an output terminal 70 for supplying the signal to the circuit 3.

If at least one of the three outputs of the NAND gates 51 to 54 supplied to the NOR gate 61 contains a high level, the output of the NOR gate 61 will be at a low level regardless of the logic level of the other one. becomes. However, N
If the logic levels of all three of the inputs to the OR gate 61 are low, the NOR gate 61 inverts the logic level of the other input and outputs it. Here, among the four NAND gates 51 to 54, the outputs of the three NAND gates that do not receive the output of the NAND gate (any one of 31 to 46) specified by the data selector signal are always at a low level. Become. Therefore, the NOR gate 6 always selects one of the NAND gates 31 to 46 specified by the data selector signal.
The output of the AND gate, that is, the bit data corresponding to the data of the data select signal among the output data DO to D15 of the memory section 9 is inverted and output.

6. Since the output of the NOR gate 61 is inverted by the inverter 62, the data of the bit corresponding to the data of the data select signal among the output data of the memory section 9 is output from the inverter 62 in an unchanged form (non-inverted). state)
Output. As a result, the output of the inverter 62 is the same as the one output from the memory section 9 according to the data select signal.
Data of each bit of 6-bit parallel data DO~D
15 in sequence. In other words, the data output from the memory section 9 in parallel is output from the inverter 62 in serial.

The serial data output from the inverter 62 as described above is applied to the flip-flop circuit 13 in FIG. 4 via the output terminal 70.

[Problems to be Solved by the Invention] FIG. 6 is a timing chart showing the operation of the semiconductor memory device shown in FIG. 4 in a read mode.

In the following, problems with conventional semiconductor memory devices that perform parallel/serial conversion will be explained in detail with reference to FIGS. 4 to 6. Clarify by explaining.

In the read mode, the output clock signal CKo applied from the clock selection circuit 3 to the output clock terminal 2
UT is output. This output clock signal CI(O
UT is a repetitive pulse that rises at a constant cycle, as shown in FIG. 6(a).

The rise of this pulse is counted by a 4-bit counter 4. Therefore, each time the 4-bit counter 4 counts the rise of this pulse once, the data select signal output from the 4-bit counter 4 is set to the data F.
It changes repeatedly in the order of H, EH, ..., oH. That is, the data indicated by the data select signal is switched in response to the rise of the output clock signal CKoUo, as shown in FIG. 6(c). Furthermore, every time the 4-bit counter 4 counts the rising edge of the pulse 16 times,
When the carry signal output from the bit counter 4 becomes high level, the address signal from the m-bit counter 7 is incremented. Therefore, the address indicated by the address signal is the output clock signal CKO as shown in FIG. 6(b).
In response to every 16th rising edge of UT, ie, data OH to F of the data select signal. At almost the same timing as the change to , the previous address A is changed to the next address A+1, the address A+1 of the garment is further changed to the next address A+2, and so on.

The memory section 9 outputs 16-bit data D15 to DO in parallel from the address indicated by the address signal from the m-bit counter 7. Therefore, the most significant bit data D15 of the output data of the memory section 9 is shown in FIG.
As shown in d), in response to the switching of the address signal, the addresses A and A indicated by the address signal before switching are
+1. The most significant bit data DA15, DA+, 15 . . . , the address A+1 . . . indicated by the address signal after switching, respectively. A+2.
The most significant bit data DA+- stored in ...
115, DA Ya 215. It switches to... Similarly, data D]4 to DO from the 14th bit to the least significant bit of the output data of the memory 9 section 9 also responds to the switching of the address signal, as shown in FIG. 6(e). Then, the addresses A, A+1 .・
Those corresponding to DA 14 to DA O, DA++
14~DA++ 0. -IJ', etc., respectively, address A+1. A+2.・・・
・Corresponding to DA Ya, 14 to Dh++ 0. D.A.B.
14~DA+20. - Switch to Badu.

On the other hand, the multiplexer 12b selects the 4-bit data (F) indicated by the data select signal among the output data of the memory section 9, as described above.

.about.O1, I) is selectively output. Referring to FIGS. 6(b), (C), and (f), for example, during a period when the data select signal is data OH, the output data of multiplexer 12b is sent to address A indicated by the address signal at that time. This becomes data DAo of the least significant bit of the stored data. Thereafter, the data selector signal is switched from data oH to data 0-data FM, and the address signal is switched from one indicating address A to one indicating address A+1 almost simultaneously. In response, the data D15-DO applied from the memory section 9 to the multiplexer 12b are switched from DA15-D^0 corresponding to address A to DAAl115'-DA+IO corresponding to address A+1, respectively.

On the other hand, in the multiplexer 12b, when the data select signal is switched from data OH to FH, the multiplexer 12b immediately selects the data select! - The NAND gate directed by the signal switches from 46 in FIG. 5 to 31. As a result, the data applied to the inverter 62 is switched from the least significant bit data DO to the most significant bit data D15. However, memory section 9
The data D15 inputted to the multiplexer 12b from the NAND gate 31. NAND gate 51° and NO
R gate 61. The signal is supplied to the flip-flop circuit 13 through four stages of gate circuits such as the inverter 62 and the inverter 62. Therefore, even if the NAND gate instructed by multiplexer 1 buffer 12b is switched, the output of multiplexer 1.2b does not immediately change to the data corresponding to address A+1 indicated by the address signal after switching. . That is, the output of the multiplexer 12b is as shown in FIG. 6(f).
In response to switching of the address signal and data select signal, the most significant bit data D^15 corresponding to the address A indicated by the address signal before switching becomes data D^15 for a while, and then the address signal after switching becomes address A indicated by
The data DA corresponding to +1 is switched to 15.

Thereafter, the output data of the multiplexer 12b is switched one by one from data D^+114 of the 14th-order bit corresponding to address A+l to data DA+10 of the least significant bit in response to switching of the data select signal.

Then, when the address signal further switches to one indicating the next address A+2, the output data of the multiplexer 12b changes from the least significant bit data DOh12 to the most significant bit data D15 in response to the switching of the data selector signal. As a result of the switching, the input data to the multiplexer 12b is switched to that corresponding to the next address A+2. For this reason, multiplexer 12b
The output data becomes data DAya, 15 corresponding to the previous address A+1 for a while, and then switches to data D^+2]5 corresponding to the next address A+2.

As described above, due to the configuration of the multiplexer 12b, after the address signal is switched, the output data of the multiplexer 12b returns to the most significant bit data D15 corresponding to the address before switching, and then after switching. The data changes to the data corresponding to the address.

On the other hand, in FIG. 4, the flip-flop circuit 13 takes in and outputs the output data of the multiplexer 12b in response to the rise of the output clock signal CKOUT. Therefore, the output clock signal CK. The rising cycle of UT is set so that the output data of multiplexer 12b at the rising edge of output clock signal CKOUT always corresponds to the address indicated by the address 3 signal after switching. In other words, the output clock signal cK.

, □ rise period is determined by the flip-flop circuit 13,
The length is set so that the data at the address indicated by the address signal before switching, which is output for a while from the multiplexer 12b immediately after the address signal is switched, is not taken in. As a result, the output data of the flip-flop circuit 13 is changed from the most significant bit data D15 to the least significant bit data D15 in address order, as shown in FIG. 6(g).
Switches to O.

As described above, in conventional semiconductor memory devices that serially output data read in parallel, the data conversion speed of the multiplexer that converts parallel data into serial data is slow. The data at the previous address is output from the multiplexer. However, semiconductor memory devices must output data at an address corresponding to an address signal. For this purpose, the data acquisition timing of the flip-flop circuit that takes in the output data of the multiplexer as the output data of the device is selected so that the data of address 4 before switching is not outputted to the outside as the output of the device. There is a need. Therefore, it has not been possible to make the rising cycle of the output clock signal, which determines the data acquisition cycle of the flip-flop circuit, so short. The operating frequency of such a conventional semiconductor memory device in read mode is from the rise of the output clock signal that changes the address signal until the data at the address indicated by the changed address signal is taken into the flip-flop circuit. determined by the time of In other words, the data transmission rate, which is inversely proportional to the operating frequency, is
The shorter the "time to capture" is, the faster it is. However, in conventional semiconductor memory devices, since the period during which the data at the address before switching is output from the multiplexer is long, the rising cycle of the output clock signal becomes long, and the period is determined by the "time until the data is captured." Data transmission speed was slow. For this reason, such conventional semiconductor memory devices could not be used as high-speed line memories.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor memory device that can be used as a high-speed line memory, has a high data transmission speed, and has a parallel/serial conversion function.

[Means for Solving the Problems] In order to achieve the above-mentioned objects, a semiconductor memory device according to the present invention includes a storage means that has an address and stores data of a plurality of bit lengths for each address. and addressing means for specifying an address of the storage means for reading or writing data to the storage means; serial data output means for serially outputting data of a plurality of bit lengths read by the serial data outputting means bit by bit; regulation means for defining the data output order of the serial data outputting means; and addressing means. control means for switching the output data of the serial data output means from the data of the last bit in the output order specified by the specifying means to the data of the first bit in response to switching the address specified by the specifying means; Equipped with. As in the past, the serial data output means has a first path for outputting the data of the first bit in the output order specified by the specifying means, and a second path for outputting the data of the first bit in the output order specified by the specifying means. and a second path for outputting each of the subsequent bits of data. Further, unlike the conventional art, the signal transmission time of the first path is set shorter than the second signal transmission time.

[Operation] The semiconductor memory device according to the present invention is configured as described above, and can serially output data read out in parallel. In the serial data output means for converting parallel data into serial data, the signal transmission time of the first path for outputting the data of the first bit in the data output order is 7 second in the data output order. The second bit for outputting the data of bits after the th bit.
is set to be shorter than the signal transmission time of the route. Therefore, when the serial data output means is set by the control means to output the data of the first bit in the data output order when the address specified by the address designation means is switched, the signal transmission time is reduced. short second
The data of the first bit is output from the serial data output means via the path. In other words, the period from when the data corresponding to the address after switching is read from the storage means by the serial data outputting means until the data at the address after switching is output from the serial data output means is 1.
17 minutes will be shortened.

[Embodiment] FIG. 1 is a schematic block diagram of a semiconductor memory device showing an embodiment of the present invention.

Referring to FIG. 1, this semiconductor memory device is a parallel/serial conversion type dry conductor memory device that outputs data input in parallel serially and has a configuration similar to that shown in FIG. be.

8 However, multiplexer 1 in this semiconductor memory device
．． 2a has a configuration different from that of the conventional one shown in FIG. In this embodiment, it is assumed that the configuration and operation of other functional sections of this semiconductor memory device are the same as those in FIG. 4.

FIG. 2 is a circuit diagram showing the configuration of the multiplexer 12a.

Referring to FIG. 2, this multiplexer 12a and the fifth
The difference from the multiplexer 1.2b shown in the figure is that this multiplexer 12a is a 4-person AND gate that receives each bit of data included in the 4-bit data, which is the data select signal from the 4-bit counter 4, in a non-inverted state. 81, a two-man NAND gate 82 which receives the output of the AND gate 81 and the most significant bit data D1.5 of the output data of the memory section 9; and the NAN
The difference is that a two-man power NAND gate 83 receiving the output of the D gate 82 and the output of the four-man power NOR gate 61 is provided in place of the NAND gate 31 and inverter 62 in FIG.

9 AND gate 81 indicates that the data select signal is data FM.
A high level signal is output only when the data select signal is other data, and a low level signal is output when the data select signal is other data. On the other hand, the output of the NAND gate 82 is
If the output of the ND gate 81 is low level, the memory section 9
The logic level is high regardless of the logic value of the data D15 outputted from the memory section 9, but if the output of the AND gate 81 is high level, the logic level becomes the logic level corresponding to the inverted data of the output data D15 of the memory section 9. Therefore, when the data select signal becomes data FH, the NAND gate 8
2, the most significant bit data D15 of the output data of the memory section 9 is inverted and output. In other words, A
The ND gate 81 detects that the multiplexer 12B is switched to output the most significant bit data D15 of the 16-bit parallel data from the memory section 9, and sends the most significant bit data D15 to the NAND gate 82. Bit data D15 is output.

On the other hand, each of the NAND gates 32 to 46 has a data select signal of data E as in the prior art. ~OH only, the 15th bit data D14 to the most significant bit data DO from the memory unit 9 are inverted and output. The outputs of the NAND gates 32-46 are then distributed to four NAND gates 51-54 for manual input. However, unlike the conventional case, the output of the NAND gate 82 which outputs the inverted data of the most significant bit data D]5 is not applied to the NAND gate 51. Therefore, the NAND gate 51 becomes a three-man powered NAND gate.

The NAND gates 51 to 54 sequentially output data D14 of the 14th bit to data DO of the least significant bit in accordance with the data select signal.

If the data select signal is one of the data EH to OH, one of the NAND gates 51 to 54 outputs the data of the bit corresponding to the data select signal among the output data of the memory section 9. (DO-D14
) is output. The outputs of the other three NAND gates 51 to 514 are fixed at low level. As a result, from the NOR gate 61,
Data DO to D14 are each inverted and output.

However, if the data select signal is data F, the output of the NOR gate 61 is fixed at a high level due to the outputs of the NAND gates 51 to 54, which are fixed at a low level. In other words, none of the data DO to DI4 appears at the output of the NOR gate 61. On the other hand, at this time, N
At the output of the AND gate 82, the inverted data of the most significant bit data D1.5 appears as described above. Now, the NAND gate 83 can invert and output the other input logic level only when one input logic level is high level. Therefore, the data select signal is data F. When , NAND gate 8
3 to the most significant bit data D15 is further inverted, that is, the most significant bit data D]5 is output in a non-inverted state.

2. Conversely, when the data select signal is other than data F□, the output of the NAND gate 82 is
It is fixed at high level by the low level output of 1. In other words, the most significant bit data D]5 does not appear at the output of the NAND gate 82. Therefore, from the output of the NAND gate 83, the inverted data of any one of the data DO to D14 appearing at the output of the NOR gate 61 is further inverted and output. That is, in this case, the output of the NAND gate 83 has data DO to D1.
Data of any one of 4 appears in a non-inverted state.

As described above, in this multiplexer 12a, among the output data of the memory section 9, the data DO to D14 from the lowest bit to the 14th bit are each sent to one of the NAND gates 32 to 46 as before. , NAND gate 5
1 to 54, the NOR gate 61 and the NAND gate 83 to the output terminal 70, while the most significant bit data D315 is output to the output terminal 70 through the NOR gate 61 and the NAND gate 83. NAND gate 83
is led out to the output terminal 70 via. Therefore, when the data select signal becomes data FH, the time until the most significant bit data D 1.5 is transmitted to the output terminal 70 is shorter than in the conventional case. As a result, in response to a change in the address signal, the most significant bit data D15 corresponding to the address indicated by the changed address signal appears at the output of the multiplexer 12a more quickly than in the conventional case.

FIG. 3 is a timing chart showing the operation of the semiconductor memory device of FIG. 1. FIG. 3(a) is a timing chart of the output clock signal CKoUT, FIG. 3(b) is a timing chart showing the switching timing of the address signal, and FIG. 3(C) is a timing chart showing the switching of the data select signal. Timing chart diagram, Figure 3 (d) and (
e) is a timing chart showing the switching timing of the most significant bit data D15 and the 14th bit to least significant bit data D14 to DO read from the memory section 9, and FIG. FIG. 3(g) is a timing chart showing the switching timing of the output data of the flip-flop circuit 3. FIG.

Referring to FIGS. 1 to 3, the address signal and data select signal are shown in FIGS. 3(b) and (3), respectively.
The output clock signal (Fig. 3(a)
)) Switches in response to the rising edge of The address signal is
The data select signal is incremented almost simultaneously with switching from data OH to FH. Therefore, the most significant bit data D15 and the least significant bit data DO to 14th bit data D14 output from the memory unit 9 are also as shown in FIGS. 3(d) and (e), respectively. Every time the address signal is incremented, it switches to the one corresponding to the incremented address signal.

For example, when the address signal is incremented from one indicating address A to one indicating the next address A-1, the switching of the data select signal causes AND gate 81 in multiplexer 12a to
The AND gate 82 is caused to output the most significant bit data D15 output from the memory section 9. That is, the NAND gate 82 is designated by the data select signal, and the other 15 NAND gates 32 to 46 are not designated. As a result, the output terminal 7 of the multiplexer 20a
0, the most significant bit data DA, 15 corresponding to the next address A+1 is transmitted with a delay time t due to the NAND gates 82 and 83 from the switching time of the output data of the memory section 9. (See Figure 3(f)). Then, during the period from the switching time of the output data of the memory unit 9 until the most significant bit data DA+15 corresponding to the next address A+1 is transmitted to the output terminal 70, the most significant bit data DA+15 corresponding to the previous address A is transmitted to the output terminal 70. Upper bit data DA15 is output from the multiplexer 12a.

However, in this embodiment, the delay time is reduced by two stages of gate circuits compared to the conventional case (see comparison between FIG. 3 and FIG. 66). Therefore, multiplexer 12a
Immediately after the address signal is incremented, the output (FIG. 3(f)) becomes data corresponding to the address before being incremented for a shorter time than in the conventional case.
Switches to data corresponding to the incremented address. Thereafter, until the next address signal is incremented, the output of the multiplexer 12a is changed from the 14th bit of data D14 to the least significant bit corresponding to the incremented address in response to switching of the data select signal. The data changes sequentially up to the data DO.

The flip-flop circuit 13 receives an output clock signal CKO
In synchronization with the rising edge of UT, the output of the multiplexer 12a is taken in and output. Therefore, the output clock signal C
The rising cycle of KoU□ must also be set to a value such that the most significant bit data corresponding to the address before being incremented is not taken into the flip-flop circuit 13. However, as described above, when the address signal 7 is switched, the period during which the most significant bit data corresponding to the address before switching appears at the output of the multiplexer 12a is shorter than in the past, so the output clock signal CKoU The rising cycle of □ can be made shorter than before. Therefore, Fig. 3(a) and Fig. 6(a)
The output clock signal CKO in this embodiment is compared with
The rising cycle of the UT is set shorter than that of the conventional one.

The short rising cycle of the output clock signal CKoLIT means that the data acquisition cycle of the flip-flop circuit is shortened. On the other hand, the output clock signal CI (
The short rising cycle of OLIT also means that the switching cycle of the output data of the memory section 9 is shortened by shortening the switching cycle of the address signal and the data select signal. This further means that the switching cycle of the output data of the multiplexer 12a is shortened. In other words, the data acquisition cycle of the flip-flop circuit 13 is also shortened to follow the shortening of the switching cycle of the output data of the multiplexer 1'2a. As a result, the flip-flop circuit 13
As shown in FIG. 3(g), the switching cycle of the output data is shortened compared to the conventional one (see FIG. 6(g)).

The data transmission speed of this semiconductor memory device is determined by the output clock signal cK, which changes the address signal.

The shorter the time from the rise of UT until the flip-flop circuit 13 takes in the first data of the address indicated by the changed address signal (in this embodiment, the most significant bit data D15), the shorter the time. This time is shorter in this embodiment than in the conventional case as described above. As a result, the data transmission speed of this semiconductor memory device is improved compared to the conventional one without complicating the configuration of the multiplexer.
It becomes possible to continuously output high-speed data. Therefore, the semiconductor memory device of this embodiment can also be used as a high-speed line memory.

Incidentally, the flip-flop circuit 13 also functions to make the output time width of each bit of data from the device equal to three when this semiconductor memory device is used as a line memory. When 16 bits of data are read from the memory section 9, the data of each bit is actually not output from the memory section 9 at the same time. This is because in the memory cell array in the memory section 9, each bit of data is stored in memory cells arranged at physically different positions. In other words, the time (access time) from when the address signal is incremented until each of the 16 bits of data corresponding to the incremented address signal is output from the memory unit 9 is
The difference depends on the delay time in the data transmission path of each bit. Therefore, in read mode,
The output time of each bit of data from the memory section 9 differs depending on the bit.

Therefore, each bit of data output from the memory unit 9 is sequentially outputted from the memory unit 9 for the same period of time as the output time of the line memory, which requires the output time of each bit of data to be equal to each other. It is not possible to output to . Therefore, by providing a flip-flop circuit (3) in the data output stage that takes in data in synchronization with the lock pulse with a constant rising cycle, the output time of each bit of data from the device can be adjusted to Make equal. Note that in this embodiment, the first output from the multiplexer 12a is the most significant bit data D15, so the output clock signal CI is output. The rising cycle of UT is such that after the address signal is incremented, the most significant bit data D15 input to the multiplexer is completely determined to correspond to the incremented address, and then the flip-flop circuit 1'3 is incremented. It is set to capture data from PiI.

Note that in this embodiment, the output order of the data of each bit constituting the parallel data read from each address specified by the address signal was from the most significant bit to the least significant bit. A similar effect can be obtained by using any order. In this case, in the output order, the delay time in the path until the first bit of data is transmitted to the output terminal of the multiplexer is equal to the delay time until the other 1 bit of data is transmitted to the output terminal of the multiplexer. so that the delay time on the path is shorter than
In addition, the multiplexer may be configured such that the former path is activated in response to a data select signal that selects the data of the first bit in the multiplexer.

By the way, after the address signal is incremented, the time required for each bit of data input to the multiplexer to be determined to correspond to the incremented address differs depending on the bit. Therefore, in this embodiment, if the bit with the minimum access time is set first in the data output order from the multiplexer, the output of the multiplexer 12a will be incremented from the rising edge of the output clock signal that increments the address signal. The time T (see figure m3) until the address is switched to the one corresponding to the address is minimized. As mentioned above, the data acquisition period of the flip-flop circuit 13,
That is, the rising cycle of the output clock signal CKoU
7 is set so that the flip-flop circuit 13 takes in data at least after the time T has elapsed since the rise of the output clock signal CKOLIT. Therefore, if the time T is shortened, the rising cycle of the output clock signal CKOUT can be further shortened. Therefore, the effects of this embodiment can be further enhanced by selecting the bit with the shortest access time as the first bit in the data output order. For example, in this embodiment, it is the most significant bit data that is output from the multiplexer to No. 1. It is desirable to minimize access time to data.

It is obvious that the same effect as in this embodiment can be obtained even if the bit length of the parallel data to be converted into serial data is other than the length (16 bits) in this embodiment.

[Effects of the Invention] As described above, according to the present invention, the operating speed of a parallel/serial conversion type semiconductor memory device can be shortened without complicating the internal configuration of the device. As a result, it becomes possible to use a parallel/serial conversion type semiconductor memory device, which has conventionally had a slow operating speed, as a high-speed line memory or the like.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the internal configuration of the multiplexer in FIG. 1, and FIG. 3 shows the operation of the semiconductor memory device of FIG. 1. The timing chart diagram shown in Fig. 4 for explanation is the conventional one! 1' is a schematic block diagram of a conductive memory device, FIG. 5 is a circuit diagram showing the internal configuration of the multiplexer in FIG. 4, and FIG. 6 is a timing chart diagram for explaining the operation of the semiconductor memory device in FIG. 4. be. In the figure, 1 is an input clock terminal, 2 is an output clock terminal, 3 is a clock selection circuit, 4 is a 4-bit counter,
7 is an m-bit counter, 9 is a memory section, 10 is a parallel data input terminal, 11 is a write control input terminal, 12a and 12b are multiplexers, 13 is a D-type flip-flop circuit, and 14 is an unreal data output terminal. , 21-24 and 62 are inverters, 81 is an AND gate, 31-46. 51-54
．． 82 and 83 are NAND gates, 61 is a NOR gate,
70 is an output terminal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A storage means having an address and storing data of a plurality of bit lengths for each address, and specifying an address of the storage means for reading or writing data to the storage means. addressing means; reading means for reading data of the plurality of bit lengths from the storage means in parallel in response to an address designated by the addressing means; and the plurality of bits read by the reading means. serial data output means for serially outputting long data one bit at a time; means for defining the data output order of the serial data output means; control means for switching the output data of the serial data output means from the data of the last bit in the output order specified by the specifying means to the data of the first bit in the output order specified by the specifying means; The serial data output means includes a first path for outputting the data of the first bit in the output order specified by the specifying means, and a second path and subsequent bits in the output order specified by the specifying means. a second path for outputting each bit of data, and a signal transmission time of the first path is shorter than a signal transmission time of the second path. .