KR100641914B1 - The device for generating internal column address - Google Patents

Abstract

The present invention relates to an internal column address generator used in a synchronous memory device, and more particularly, by designing an interleaved counter for generating least significant bit internal column addresses and a single flip-flop in a sequential counter. The present invention relates to an internal column address generator that simplifies and greatly reduces the design area burden.

Description

The device for generating internal column address

1 is a block diagram of an internal column address generator according to the present invention.

2 is a detailed block diagram of the interleaved counter shown in FIG.

3 is an operation timing diagram of FIG. 2.

4 is a detailed block diagram of the sequential counter shown in FIG.

<Description of Symbols for Major Parts of Drawings>

1 to 3: toggle flip-flop 4, 5: di flip-flop

10 to 60: 2 * 1 multiplexer 100: interleaved counter

110: counting unit 120: address generating unit

200: sequential counter

The present invention relates to an internal column address generator used in a synchronous DRAM, and more particularly, by using a single interleaved counter and a sequential counter for generating least significant bit (LSB) addresses, thereby simplifying a circuit and reducing design area burden. An internal column address generator which is greatly reduced.

Generally, synchronous DRAM (SDRAM) devices have arbitrary burst lengths and the first column-address is taken from the outside when performing read and write operations, starting with this column-address in an interleaved and sequential manner. This causes the internal column address to be generated continuously.

To this end, conventional internal column-address generators for synchronous DRAMs have separate address generation counters used in the interleave method and address generation counters used in the sequential method.

In addition, the interleave method and the sequential counters are typically implemented as flip-flops, and each flip-flop includes one flip-flop.

Therefore, the conventional internal column address generator has a counter flip-flop having the same number of bits as the maximum burst length for the interleave method and the sequential method, respectively. There is a problem that acts as a burden.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to unify a flip-flop for a counter used for least significant bit (LSB) address generation and to use it for both interleaved and sequential address generation. The present invention provides an internal column address generator that greatly reduces the area burden in design.

In order to achieve the above object, the internal column address generating apparatus according to the present invention comprises: a first counting means for generating an n-bit internal column address in an interleaved manner by performing an address counting operation on an n-bit column address input; second counting means for sequentially generating n-1 bit internal column addresses excluding the least significant bit (LSB) for n-bit column address inputs; First multiplexing means for receiving the least significant bit (LSB) column-address generated from the first counting means for both input terminals and generating the selected bit by a selection control signal; The internal column address for the remaining bits except the least significant bit (LSB) of the first counting means and the internal column address generated from the second counting means are inputted for each bit, and one internal column address is selectively generated by the selection control signal. And n-1 second multiplexing means.

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The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an internal column address generator according to the present invention. For convenience of understanding the present invention, a simple example of a 3-bit internal column address generation will be described.

Accordingly, the internal column address generator shown in FIG. 1 performs an address counting operation on the 3-bit column address (YA <0: 2>) input to obtain the 3-bit internal column address (ITL_YA <0: 2>). An interleaved counter 100 for generating in an interleaved manner; Sequential generation of sequentially generating two-bit internal column addresses S_YA <1: 2> except the least significant bit LSB (YA <0>) with respect to the three-bit column address YA <0: 2> input A counter 200; 2 * 1 multiplexer 10 which receives the least significant bit (LSB) column-address YA <0> generated from the interleaved counter 100 for both input terminals and generates it by the selection control signal sel 10. )Wow; Internal column addresses ITL_YA <1: 2> for the remaining bits except the least significant bit LSB of the interleaved counter 100 and internal column addresses S_YA <1: 2> generated from the sequential counter 200. ) Is inputted to each bit by one internal column address to the selection control signal (sel: this signal means a signal for controlling selection of an internal address generated sequentially by an interleaved method and an internal address generated sequentially). And two 2 * 1 multiplexers 20, 30 which are selectively generated.

In this case, the interleaved counter 100 includes three address counter flip-flops for generating 3-bit internal column addresses, and the sequential counter 200 is common from the interleaved counter 100. Since there is no need to provide a flip-flop for the address counter for generating the least significant bit (LSB) column address generated, the interleaved counter 100 has two fewer flip-flops for the address counter. Done.

According to the above configuration, the output signal of the flip-flop used for generating the internal least significant bit (LSB) column-address of the interleaved counter 100 includes both the least significant bit (LSB) address of the interleaved and sequential internal column addresses. Will be generated.

Hereinafter, the configuration and internal circuit operation of each of the interleaved counter 100 and the sequential counter 200 will be described in detail with reference to the accompanying drawings.

FIG. 2 is a detailed block diagram of the interleaved counter 100 shown in FIG. 1. FIG. 2 also shows an example of three-bit internal column address generation. Address counting operation consists of three toggle flip-flops (1 to 3) to toggle the output signal for each falling edge of the clock signal (received / clk, p1, and p2 signals) received and received. Counting unit 110 to perform; The bit-address (YA0 and / YA0, YA1 and / YA1, YA2 and / YA2) inputted with complementary potential values by the output signals p1 to p3 of the toggle flip-flops 1 to 3, respectively. And an address generator 120 that selects a potential of and generates an internal column address int_YA <0: 2> for each bit.

In the case of the figure, the counting unit 110 has a setting control signal (clear) is input to one input terminal, an external clock input with a predetermined period for generating an internal column address corresponding to the burst length (BL) A first toggle flip-flop 1 for toggling the output signal at each falling edge of the signal / clk; The setting control signal (clear) is applied to each input terminal, and receives the output signals (p1, p2) of the toggle flip-flop (1, 2) connected to the front end to toggle the output signal for each falling edge It has two toggle flip-flops (2, 3).

In addition, the address generator 120 receives a complementary potential signal of the least significant bit (LSB) column address YA0 and selectively generates the output signal p1 of the first toggle flip-flop 1. The output signal p2 and p3 of each of the toggle flip-flops 2 and 3 are received by receiving the complementary potential signals of the lexer 40 and the column addresses YA1 and YA2 for the remaining bits except the least significant bit LSB. ) And two multiplexers 50 and 60 selectively generated by a combination of the above and the selection control signal sel.

3 illustrates an operation timing diagram of the interleaved counter 100 shown in FIG. 2. Hereinafter, an interleaved address counting operation will be described in detail with reference to the drawing.

First, at the beginning of the burst operation, the external clock signal / clk for generating internal column address as much as the burst length BL is toggled with a certain period as shown in (a). In order to receive the input column address as it is, the output signals of the toggle flip-flops 1 to 3 are cleared and set.

To this end, as shown in (b), the setting control signal clear is enabled at the logic high level immediately after the first clock signal is applied, and the output signal p1 of the toggle flip-flops 1 to 3 is enabled. To p3).

Then, whenever the external clock signal / clk shown in (a) toggles, the output signal p1 of the first toggle flip-flop 1 is shown in (d) at its falling edge. Toggle as described above, and the output signal p2 of the second toggle flip-flop 2 receives the output signal p1 of the first toggle flip-flop 1 and toggles it for each falling edge (e). And generates an output signal p3 of the toggle flip-flop 3 connected to the front end, as well as the output signal p2 of the toggle flip-flop 2 connected to the front end. Each falling edge is toggled like the signal waveform shown in (f).

The output signal of each toggle flip-flop 1 to 3 generated by the above operation is first inputted to the output signal p1 of the first toggle flip-flop 1 as the selection signal of the 2 * 1 multiplexer 40. The output signals P2 and P3 of the remaining toggle flip-flops 2 and 3 are selected by the selection control signal sel, which is an internal address generated by an interleaved method and an internal address generated sequentially. The signal is controlled by the NOA combination with the signal of the 2 &lt; 1 &gt; multiplexers 50 and 60 for each of the corresponding bits.

As can be seen from the waveforms (g) to (i) in the figure, the output signal int_YA <0> is represented by (c) for each falling edge of the external clock signal (/ clk) shown in (a). And the next higher bit internal column address output signal int_YA <1> is received from the YA <1> signal shown in (c) for each falling edge of the p1 signal shown in (d). Toggle the YA <2> signal shown in (c) for each falling edge of the p2 signal shown in (e), as well as the next higher bit internal column address output signal int_YA <2>. You will receive a signal.

Therefore, when the internal column address signal int_YA <0: 2> generated by the interleaved counter 100 is displayed in decimal, the value '7 (111)' of the first input column address signal is first received as it is. Then, the value is changed at every falling edge of the external clock signal (/ clk) by address counting so that 7 (111), 6 (110), 5 (101), 4 (100), 3 (011), and 2 (010). ), 1 (001) and 0 (000) are counted in order.

FIG. 4 is a detailed configuration diagram of the sequential counter 200 shown in FIG. 1, and is turned on by the setting control signal clear so that the bit address of each column except the least significant bit LSB ( First transfer elements MT1 and MT3 for transmitting YA1 and YA2; The column addresses YA1 and YA2 for each bit transmitted from the first transfer elements MT1 and MT3 are constant by the burst length BL under the control of an external clock signal / clk input with a predetermined period. Two de-flip-flops 4 and 5 that time delay to generate an internal column address S_YA <1: 2>; The turn-on control complementary to the first transfer elements MT1 and MT3 is performed by the setting control signal clear, and an address counting sum of the de-flip-flop output signal of the previous external clock signal and the carry of the lower bit is added. And second transfer elements MT2 and MT4 for transmitting signals to respective bit flip-flops.

In the same figure, the transfer elements MT1 to MT4 are implemented as transfer gates. However, the transfer elements MT1 to MT4 are implemented as transfer gates. It can be said that the device can be implemented.

Looking at the address counting operation of the sequential counter 200 having the above configuration, first, the setting control signal (clear) used in the interleaved counter 100 to pass the external column address as it is when the first external clock signal is input. ) To 'logic high' level to turn on the first transfer elements MT1 and MT3, so that the bit-by-bit column addresses YA1 and YA2 except for the least significant bit are set at each falling edge of the first external clock. It is transferred to the internal address output through the corresponding flip-flops 4 and 5, and then the address counting signal obtained by adding the de-flop output signal of the previous external clock signal and the carry value of the lower bit is then transferred to the next external clock signal. By generating the falling edge of the, it performs a sequential address counting operation.

The output signals of the interleaved and sequential counters 100 and 200 that generate internal column addresses by the operation are transmitted to two input terminals of the multiplexers 10, 20, and 30 connected to the rear stages for each bit. In this case, in the case of the least significant bit (LSB) column address, the corresponding column address generated from the interleaved counter 100 is transmitted to both input terminals of the multiplexer 10). According to the state of the signal sel-for example, when the selection control signal sel is 'logic low', the internal column address generated from the interleaved counter 100 is selected and finally outputted, In contrast, in the case of 'logic high', the internal column address generated from the sequential counter 200 is selected and finally output.

By this internal address counting operation, the same internal column address can be generated even if the least significant bit counting flip-flop in the sequential counter 200 is removed.

As described above, according to the internal column address generating apparatus according to the present invention, by using a single interleaved counter and a sequential counter flip-flop for generating the least significant bit address, the circuit is simplified to greatly reduce the design area burden. It has a very good effect.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (6)

first counting means for performing an address counting operation on the n-bit column address input to generate an n-bit internal column address in an interleaved manner; Second counting means for sequentially generating n-1 bits of internal column addresses excluding the least significant bit (LSB) for the n-bit column address input; First multiplexing means for receiving the least significant bit (LSB) column address generated from the first counting means for both input terminals and generating the selected control signal by a selection control signal; The internal column address for the remaining bits except the least significant bit (LSB) of the first counting means and the internal column address generated from the second counting means are inputted for each bit, and one internal column address is received by the selection control signal. And n-1 second multiplexing means for selectively generating said internal column address generator. The method of claim 1, The first counting means includes: a counting unit configured to perform an address counting operation by n toggle flip-flops for receiving an output signal to an input terminal in a sequential structure and toggling the output signal at each falling edge of the input clock signal; ; And an address generator configured to generate an internal column address for each bit by selecting a potential of each column-address inputted with a complementary potential value by the output signal of each of the toggle flip-flops. Generator. The method of claim 2, The counting unit has a first control flip-flop to which a setting control signal is input to one input terminal, and toggles an output signal for each falling edge of the external clock signal input with a predetermined period to generate an internal column address corresponding to a burst length. and, The setting control signal is applied to one input terminal, and has n-1 second toggle flip-flops for receiving the output signal of the previous toggle flip-flop and toggling the output signal for each falling edge thereof. Internal column address generator. The method of claim 3, wherein The address generator may include: a first multiplexer configured to receive a complementary potential signal of a least significant bit (LSB) column address and selectively generate the output signal of the first toggle flip-flop; N−1 th inputs receiving complementary potential signals of column addresses for the remaining bits except the least significant bit (LSB) and selectively generated by a combination of an output signal of each of the second toggle flip-flops and the selection control signal 2. An internal column address generator, comprising: a multiplexer. The method of claim 1, The second counting means includes: n-1 first transfer elements which are turned on by a setting control signal to transfer the column address for each bit except for the least significant bit (LSB); N-1 de-flips generated by delaying a bit address transmitted from the first transfer element for a predetermined time under the control of an external clock signal input with a predetermined period to generate an internal column address corresponding to a burst length. Flop; The setting control signal is turned on to be complementary to the first transfer element, and the address counting signal obtained by adding the de-flip-flop output signal from the previous external clock signal and the carry of the lower bit is de- flipped for each bit. And n-1 second transfer elements for transferring to the flop. The method of claim 5, And said first and second transfer elements comprise transfer gates.

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