JPH03189989A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a multi-port memory which can writes at high speed accessing mode of a page mode etc. by providing a column address selecting ate to connect th gate to a column address decoder and a data line to connect it to both of the source of the drain of the column address selection gate and an SAM. CONSTITUTION:To partition the data of RAM at every column address, to transfer and to serial-output, a data line to connect the RAM with the bit line of the RAM through a column address selection gate and a serial accessing memory SAM to connect the bit line of the RAM and the column address selection gate through the data line are provided. By such constitution, time to write the data to be displayed on a screen in the RAM is shortened, screen display can be made high speed, and at the same time, on reading the data of the RAM in the screen, useless data transfer is not executed. Thus, since the data of the respective blocks of the screen can be written in the RAM by a page mode, the writing time can be shortened sharply. A multi-port memory can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memories, particularly multiport memories for raster scan graphics display.

2. Description of the Related Art In recent years, multiport memories have come into widespread use for image processing in graphic terminals and the like.

A conventional multiport memory will be explained below.

FIG. 3 shows a block diagram of a conventional multiport memory. WLI~wtn are random access memory (RAM) word lines, BLI~B L12 is RA
M bit lines, T1-T16 are column address transfer gates,
Dt+-Dt4 is a data line.

The operation of this multiport memory will be explained. Data input/output to/from the RAM is performed using data lines DLI to DL4. For example, data line DLI~
Consider the case where data on the data line DL4 is written to a memory cell on the word line WL+. Word line W L + is selected, and data is written into memory cells connected to the bit line and word line W L + selected by the column address decoder. In addition, in the case of reading, the data of the memory cell connected to the selected word line and the bit line selected by the column address decoder is transferred to the data line DLI~
It is read out through each line of DL4.

Next, when reading serial data from a serial access memory (SAM), the data in the memory cell connected to the selected word line in the RAM is transferred to the SAM through the bit line and output as serial data. Ru. When performing screen display, the data to be displayed on the screen is
The data was written to AM, transferred to SAM, serially output, and displayed on the screen.

Problems to be Solved by the Invention In the conventional configuration, when the data transferred to the SAM is continuously output in accordance with the movement of the scanning line according to the normal usage method, the data in the SAM is output on the word line selected at the time of transfer. Therefore, data on one word line is basically displayed on one scanning line or a portion thereof. Therefore, when writing a graphic that extends in the vertical direction and involves a plurality of scanning lines into the RAM, it is necessary to access a plurality of word lines with different row addresses. In general, in dynamic RAM, high-speed access modes such as page mode can be used when accessing memory cells with the same row address but different column addresses, but if the row addresses are different, the normal access mode takes about twice as long as page mode. Only the following access modes can be used. That is, when writing a graphic that extends in the vertical direction into the memory, the conventional multi-port memory has the disadvantage that only the slow normal access mode can be used, and the writing speed of the display graphic is slow.

Furthermore, even when using conventional multiport memory, 1
By making the data on the word line of a book correspond to a two-dimensional rectangular area that extends vertically on the display screen, it is possible to write a figure that extends vertically in the page mode. However, in that case, of the 1-word line data transferred to the SAM, the data that is actually continuously output along the scanning line and used for screen display is the data within the rectangular area. Only data located on the scanning line is included.

Even within the rectangular area, data located on another scanning line cannot be displayed unless it is transferred again in another transfer cycle. In other words, only a small portion of the transferred data is actually used for display, and most of the other data is wasted transfer. This wasteful transfer results in wasted power consumption and layout area of SA and M on the chip.

In order to solve the above problems, the present invention selects and transfers only the data of the necessary column address so that only the data on one scanning line within the rectangular area can be transferred to the SAM, thereby eliminating unnecessary data transfer. The purpose of the present invention is to provide a multi-port memory that can write in a high-speed access mode such as a page mode, even with graphics that extend in the vertical direction.

Means for Solving the Problems To achieve this object, the multiport memory of the present invention divides RAM data into each column address, transfers the data, and serially outputs the data. It has a data line connected via a selection gate, and a SAM connected to the RAM via a bit line of the RAM, a column address selection gate, and a data line.

Effect: With this configuration, the data displayed on the screen can be
It is possible to shorten the writing time and speed up screen display, and at the same time, it is possible to eliminate unnecessary data transfer when reading data from the RAM onto the screen.

EXAMPLE An example of the present invention will be described below with reference to the drawings. In the following explanation, for simplicity, we will discuss the case where the number of data lines is 4 and the number of column addresses is also 4. However, the present invention can be implemented even when the number of data lines and the number of column addresses are larger. Of course. Further, although two bit lines and data lines are used as a pair, this is also shown as one line for simplicity. FIG. 1 shows a block diagram of a multiport memory according to the present invention.

WLI-WLn are word lines of RAM, BLI-B Li
2 is a bit line of RAM, TI to TI6 are column address transfer gates, DLI to D+, and < are data lines. R.A.
Data input/output to/from M is performed using each data line DL1 to DL4. For example, consider a case where data on each data line DLI to D1.4 is written to a memory cell on word line WL+. The word line WL+ is selected and the bit line selected by the column address decoder and the word line W
Data is written to the memory cell connected to L+.

Further, in the case of reading, data of the memory cells connected to the selected word line and the bit line selected by the column address decoder is read through each data line DLI to DL4. Next, when reading serial data from the SAM, the data in the memory cell connected to the selected word line in the RAM is read onto the bit line, and the data at the column address selected by the column address decoder is transferred to the column address. Among the transfer gates T, to T16, the column address transfer gate and data line D1. I~D
The data is transferred to the SAM through either data line I or 4 and output serially. For example, word line WL+ is selected and column address transfer gates T9 to TI2 are turned on.
If the word line W L + and the bit lines BL9 to B
Data in each memory cell connected to L12 is transferred to the SAM and output as serial data.

As described above, the multiport memory of the present invention can transfer only data for one column address to the SAM, and the size of the SAM can be designed to match the size of data for one column address. Since this is possible, the layout area can be reduced.

Next, the operation when the multiport memory of the present invention is used for image processing of a graphic terminal will be explained. Second
The figure shows the screen of the GraphInk terminal. (
1) to (n) are each block obtained by dividing the screen into rectangles, A-
D is the scan line present within each block. In Figure 2, the case where there are four scanning lines A to D in a block is used, but the number of scanning lines in one block depends on the storage capacity of the multiport memory used for the graphic terminal and other factors. It is possible to implement the present invention in a similar manner even when the number of scan lines in a block is other than four, as it is determined by a number of factors. As shown in Figure 2, move the screen from (1) to (n
The amount of data in each block is equivalent to the amount of data that can be written into a memory cell connected to one word line of the RAM of the multiport memory of the present invention.

When writing data that is not to be displayed on the screen into the RAM of the multiport memory of the present invention, writing in page mode is possible within each block of the screen. next,
When outputting data written in RAM to the screen,
One RAM word line is selected, and among the memory cells connected to that word line, the data of four memory cells connected to the bit line selected by the column address decoder are transferred to the SAM and serially output, and the second It is displayed on the scanning line of block A in (1) of the figure. Then, the data to be displayed next is selected by selecting another word line of the RAM, and similarly, the memory cells connected to the selected word line are connected to the bit line selected by the column address decoder. Four pieces of data from the memory cells are transferred to the SAM, serially output, and displayed on the scanning line A of block (2) in FIG. In other words, the data to be displayed is displayed while repeating the data transfer from the RAM to the SAM along the scanning line and every time the block changes.

Effects of the Invention According to the multi-port memory of the present invention, when writing data to be displayed on the screen to RAM, data for each block of the screen can be written to RAM in page mode, so writing time can be significantly reduced. It can be shortened to

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiport memory according to an embodiment of the present invention, and FIG. 2 shows screens WLI to W of a graphic terminal. ...RAM word line, BLI to BL16...
...RAM bit line, T I "' - T I 6
...Column address 0 transfer gate, DLI to DL4 ...data line.

Claims (1)

[Claims] In a multi-port memory comprising a port containing a random access memory (RAM) and a port containing a serial access memory (SAM), a column whose source or drain is connected to a bit line of the RAM and whose gate is connected to a column address decoder. an address selection gate; a source or drain of the column address selection gate; and a source or drain of the SAM.
A semiconductor memory characterized in that it has a data line connected to both.