JPH03189845A - 階層メモリ・システムおよびキヤツシユ・メモリ・サブシステム - Google Patents

階層メモリ・システムおよびキヤツシユ・メモリ・サブシステム

Info

Publication number
JPH03189845A
JPH03189845A JP2307336A JP30733690A JPH03189845A JP H03189845 A JPH03189845 A JP H03189845A JP 2307336 A JP2307336 A JP 2307336A JP 30733690 A JP30733690 A JP 30733690A JP H03189845 A JPH03189845 A JP H03189845A
Authority
JP
Japan
Prior art keywords
cache
memory
data
buffer
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2307336A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0574103B2 (enExample
Inventor
Chiao-Mei Chuang
チヤオ・メイ・チユアン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH03189845A publication Critical patent/JPH03189845A/ja
Publication of JPH0574103B2 publication Critical patent/JPH0574103B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2307336A 1989-12-13 1990-11-15 階層メモリ・システムおよびキヤツシユ・メモリ・サブシステム Granted JPH03189845A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US450900 1982-12-20
US45090089A 1989-12-13 1989-12-13

Publications (2)

Publication Number Publication Date
JPH03189845A true JPH03189845A (ja) 1991-08-19
JPH0574103B2 JPH0574103B2 (enExample) 1993-10-15

Family

ID=23789981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2307336A Granted JPH03189845A (ja) 1989-12-13 1990-11-15 階層メモリ・システムおよびキヤツシユ・メモリ・サブシステム

Country Status (2)

Country Link
EP (1) EP0432524A3 (enExample)
JP (1) JPH03189845A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69319763T2 (de) * 1992-03-04 1999-03-11 Motorola, Inc., Schaumburg, Ill. Verfahren und Gerät zur Durchführung eines Busarbitrierungsprotokolls in einem Datenverarbeitungssystem
EP0567355B1 (en) * 1992-04-24 2001-09-19 Compaq Computer Corporation A method and apparatus for operating a multiprocessor computer system having cache memories
EP0607669A1 (en) * 1993-01-21 1994-07-27 Advanced Micro Devices, Inc. Data caching system and method
TW234174B (en) * 1993-05-14 1994-11-11 Ibm System and method for maintaining memory coherency
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ
US5687350A (en) * 1995-02-10 1997-11-11 International Business Machines Corporation Protocol and system for performing line-fill address during copy-back operation
US5715427A (en) * 1996-01-26 1998-02-03 International Business Machines Corporation Semi-associative cache with MRU/LRU replacement
US6052762A (en) * 1996-12-02 2000-04-18 International Business Machines Corp. Method and apparatus for reducing system snoop latency
US9367464B2 (en) * 2011-12-30 2016-06-14 Intel Corporation Cache circuit having a tag array with smaller latency than a data array
US9336156B2 (en) * 2013-03-14 2016-05-10 Intel Corporation Method and apparatus for cache line state update in sectored cache with line state tracker
CN116701246B (zh) * 2023-05-23 2024-05-07 合芯科技有限公司 一种提升缓存带宽的方法、装置、设备及存储介质
CN116543804B (zh) * 2023-07-07 2023-11-24 长鑫存储技术有限公司 驱动控制电路和存储器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189398A (en) * 1981-05-14 1982-11-20 Fujitsu Ltd Control system for memory system
JPS6145343A (ja) * 1984-08-09 1986-03-05 Fujitsu Ltd スワツプ制御方式
JPS63103343A (ja) * 1986-09-19 1988-05-09 アムダール　コーポレーション ムーブアウト待ち行列バッファ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE445270B (sv) * 1981-01-07 1986-06-09 Wang Laboratories Dator med ett fickminne, vars arbetscykel er uppdelad i tva delcykler
US4905188A (en) * 1988-02-22 1990-02-27 International Business Machines Corporation Functional cache memory chip architecture for improved cache access

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189398A (en) * 1981-05-14 1982-11-20 Fujitsu Ltd Control system for memory system
JPS6145343A (ja) * 1984-08-09 1986-03-05 Fujitsu Ltd スワツプ制御方式
JPS63103343A (ja) * 1986-09-19 1988-05-09 アムダール　コーポレーション ムーブアウト待ち行列バッファ

Also Published As

Publication number Publication date
EP0432524A2 (en) 1991-06-19
EP0432524A3 (en) 1992-10-28
JPH0574103B2 (enExample) 1993-10-15

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