JPH03189817A - Multiplying/dividing system in arithmetic unit - Google Patents

Abstract

PURPOSE:To execute the multiplying/dividing processing of a numerical value by a decimal number expression at a high speed by using a significant digit part of decimal number data of an inputted fixed point as a mantissa in a a state that it remains a decimal number expression, and normalizing and calculating the mantissa. CONSTITUTION:Data of an operand to be operated and an operand of a decimal number of a fixed point format stored on a memory 2 is inputted to a floating format converting means 3, converted to an operand to be operated and an operand of a floating point format, and stored on registers 11, 12. The operand to be operated and the operand on the registers 11, 12 are subjected to normalization processing so that a decimal point comes between the upper one digit and two digits of a mantissa by a normalization processing means 4, respectively. Subsequently, the operated number and the operand which are subjected to normalization processing are inputted to an operated number register 13 and an operand register 14, respectively and subjected to division processing or multiplication processing by an arithmetic processing part 15. In such a way, it does not occur that '0' is generated in the head part of a numerical value. a useless arithmetic processing for exerting no influence on a result of operation is eliminated, and the multiplying/dividing processing by a decimal number expression can be executed at a high speed.

Description

Detailed Description of the Invention [Summary] The present invention relates to a multiplication/division method that converts a decimal number in fixed point format into a normalized decimal number representation in floating point format and performs multiplication and division. Aiming at speeding up arithmetic processing, in a method that performs multiplication and division using fixed-point decimal data as an input means, the input fixed-point IO base data is converted into a mantissa with the number of significant digits expressed as a decimal number. a floating-point format conversion means for converting weights into data in a binary representation format, and a normalization processing means for normalizing the converted floating-point format data; It has a configuration that divides data into an exponent part and a mantissa part and performs multiplication and division in floating point format.

[Industrial application field]

The present invention relates to a multiplication/division method in which a fixed-point decimal number is converted into a floating-point normalized IO-adic representation using an arithmetic unit, and multiplication/division is performed.

[Prior art]

Conventionally, input data has been processed using denormalized numbers in fixed-point format using decimal representation such as binary coded decimal numbers.

FIG. 8(a) shows a block diagram of a conventional division method using decimal representation.

The processing procedure will be explained according to the numbers attached to the figure.

■ Set initial conditions (N=O).

■ Subtract the value obtained by multiplying the divisor by N from the dividend.

■ Determine whether the subtraction result is 0 or not, and if it is 0, use the obtained value of N as the quotient.

■ Determine whether it is negative or not.

(2), (2) If negative, it is subtracted too much, so the value of N-1 is stored as a one-digit value of the quotient.

(2) If the result of the judgment in (2) is NO, it is still possible to subtract, so N is increased by N+1 and the process from (2) onwards is repeated.

■ Identify the position of the digit of the quotient you found.

■ Store the obtained quotient in the register.

■ If the quotient is not calculated for the number of significant digits or the remainder is 0, repeat the division □ process again.

The process ends when the quotient of the number of effective digits is found or the remainder becomes 0.

FIG. 8(b) shows an example of a conventional multiplication method.

A case where the maximum number of significant digits of the arithmetic device is four digits will be explained.

For example, when calculating 23×14, fixed-point decimal representation data is stored in the register of the arithmetic unit as 4 digits with the leading O added, as shown in (1) in the figure. Next, as shown in (2), the multiplicand is multiplied by the value of each digit of the multiplier, and the intermediate multiplication result of each digit is shifted 4 bits at a time and stored in a register, and the values obtained from each digit are added. Find the multiplication result.

[Problem to be solved by the invention]

Conventional arithmetic processing using decimal numbers has problems such as not being able to obtain a large number of significant digits because processing is performed using denormalized numbers in fixed-point format as described above.

Since input numerical values when input using manual means such as a keyboard and numerical values displayed on a display means are decimal numbers, arithmetic processing using decimal numbers is converted into binary numbers when input/output is performed using such devices. Although it is advantageous compared to the arithmetic processing using the representation, it is about 4 times faster than the arithmetic processing using the binary representation.
The drawback was that it required ~6 times as many clocks and slow arithmetic processing.

Furthermore, in conventional division processing using IO base numbers, until a pollo is detected to calculate a one-digit quotient as described above,
Since it was necessary to perform subtraction up to 9 or 10 times, a large number of arithmetic operations were required.

In addition, since processing is performed using denormalized numbers, if the number is less than the maximum number of valid digits of the arithmetic unit, 0 is added to the beginning of the number. This process uses the total number of digits, so unnecessary processing that does not directly affect the calculation result is performed. There were many.

Therefore, conventional arithmetic processing using decimal representation requires a large number of clocks and is slow.
As mentioned above, since a large number of calculations are required, there is a problem in that the calculation time is significantly slower than in the case of binary representation.

This was particularly noticeable in the case of multiple-precision calculations.

[Means for Solving the Problems] In the calculation method of the present invention, the significant digit part of fixed-point decimal data is expressed as a decimal number such as a binary coded decimal number as the mantissa part, and the weight is expressed as a binary number. format data, and further normalizes the floating point format data. Then, multiplication and division are performed using the exponent part and the mantissa part in the normalized floating point format.

Furthermore, when performing division processing, a table is set up to store the values obtained by multiplying the divisor by 1 to 9, and the quotient can be calculated directly by comparing the dividend with the numerical value on the table and comparing the magnitude relationship. I asked for it. Therefore, unlike conventional division methods, subtraction is not repeated, and the number of operations can be significantly reduced.

In addition, when performing multiplication processing, create a table that stores the values obtained by multiplying the multiplicand by 1 to 9, and multiply the multiplicand by the value of each digit of the multiplier by referring to the table and calculate the multiplication for each digit. The intermediate multiplication value is calculated without any processing, so that the result can be obtained quickly. In addition, arithmetic processing is performed using normalized numbers, thereby eliminating unnecessary processing of parts that do not directly affect the calculation results of the leading numerical value O.

As described above, an object of the present invention is to speed up multiplication/division processing of numerical values expressed in decimal notation.

The basic configuration of the present invention will be explained using the basic configuration of the present invention shown in FIG. 1(a).

2 is a memory that stores operands and operands made of decimal numbers in fixed-point format; 3 is a memory that stores the input decimal numbers in fixed-point format as data in floating-point format; the mantissa part is expressed as a decimal number; the exponent part is The weight part is a floating point format conversion means for converting into binary representation, 4 is a normalization processing means for normalizing the data converted to floating point format,
5 is an arithmetic means for dividing or multiplying normalized operands and operations in floating point format; 6 is a memory for storing arithmetic processing result data; 10 is fixed-point data stored in the memory 2; 11 is the operand converted to floating point format, 12 is the operand converted to floating point format, 13 is a register that stores the operand converted to floating point format, and 14 is a register that stores the operand converted to floating point format. 15 is the operand register 1.
3 and the data stored in the arithmetic register 14.

FIG. 1(b) shows the data format of normalized floating-point numbers used in the present invention.

The mantissa is expressed as a decimal number, such as a binary coded decimal number in which one character of the decimal number is expressed in 4 pintos, and is normalized so that the decimal point is located between the first and second digits of the mantissa. Store data.

The exponent part stores the weight part in binary representation. Further, the signs of the mantissa part and the exponent part are stored as binary data in a 2-bit code part provided in the exponent part of the data format.

[Effect]

The operation of the basic configuration shown in FIG. 1 will be explained.

The data of the fixed-point format decimal operands and operands stored in the memory 2 is input to the floating-point format conversion means and converted to the floating-point format operands and operands. It is stored on 12.

The operands and the operands on the registers 11 and 12 are each normalized by the normalization processing means 4 so that the decimal point is between the first and second digits of the mantissa.

For example, if the operand is a decimal number 1 in fixed-point format,
Considering the case of 234, the normalization processing means converts the operand on register 11 into floating point format into 1.
Convert to 234X10' format. Then, the mantissa part is stored in the operand register 13 in decimal representation of a binary coded decimal number, for example, in a format in which two digits are punctured into one byte.

In addition, the exponent part is the weight data 3, if necessary,
For example, the weight data O is stored as a bias value expressed in binary hexadecimal 3fff.

The normalized operand and operand are input to the operand register 13 and the operand register 14, respectively, and are subjected to division processing or multiplication processing in the arithmetic processing section 15.

The calculation results are stored in the memory 6.

According to the present invention, since the mantissa part is normalized and the calculation is performed, 0 is not generated at the beginning of the numerical value, and unnecessary calculation processing that does not affect the calculation result can be eliminated. In addition, since the mantissa is processed using decimal representation, the decimal representation input by the input means can be used as is, and when outputting to the output means, the decimal representation format of the calculation result can be used as is. can be used.

〔Example〕

The present invention will be explained in detail with reference to FIGS. 2 to 7.

FIG. 2 shows the configuration of an embodiment centered on the calculation means of the present invention.

In the figure, 20 is a decimal input means such as a keyboard,
21 is an arithmetic unit that performs division or multiplication based on the operands and operands in decimal representation, which are normalized decimal numbers in floating point format, and 22 is a memory for storing the arithmetic results converted from floating point format to fixed point format. 23 is a display means for displaying the result of the arithmetic processing in fixed-point format in 24-decimal notation, and 24 stores the fixed-point format in 24-decimal notation inputted by manual means. Memory, 25, human power means 20
Floating-point format converting means takes out decimal input data in fixed-point format memory 24, divides it into a mantissa part and an exponent part, and converts it into floating-point format data; 26 is the upper two digits of the mantissa part; 27.28 Normalization processing unit that performs normalization processing so that the numbers after the th are decimal points.
29 is a register for storing a mantissa in floating point format normalized by the normalization processing unit 26 in a decimal format such as a binary coded decimal number, and stores a 2-digit decimal number per hide in a punctured format. an arithmetic processing unit that performs arithmetic processing using a binary coded decimal number in a puncture format on the second day and weight data of an exponent part; 30 is an intermediate result register that stores a dividend in division or an intermediate result in multiplication; 3I;
32 is a search unit that searches for a value that is an integral multiple of the divisor on the table in division and compares it with the value of the dividend, or extracts the value obtained by multiplying the multiplicand by the multiplier and inputs it into the intermediate result register in multiplication. 32 is the divisor in division. Or, a table for storing numerical values obtained by multiplying the multiplicand by 1 to 9 in multiplication; 33 is a search flag data storage section for storing a flag of 0 or 1 when the first numerical value of the quotient obtained in division is 0; 34 is a table for storing a flag of 0 or 1 in division; A generated digit number determination unit that determines the number of digits of the generated quotient; 35 is a final result register that stores the quotient in division or the operation result in multiplication; 36;
3 is a fixed-point format conversion unit that converts the operation result in normalized floating-point format into a decimal number in fixed-point format; 37 is a memory that stores the operation result converted to a decimal number in fixed-point format; and 38 is an operand or A table creation unit that creates a value that is 1 to 9 times the divisor in division or the multiplicand in multiplication based on the operation number and stores it in the table 32; 39 is an exponent calculation unit that performs arithmetic processing on the exponent part of data in floating point format; , 40 is a comparison unit for calculating a quotient by comparing the dividend with a value that is an integral multiple of the divisor on the table in division.

The operation of the embodiment shown in FIG. 2 will be explained with reference to FIGS. 3 to 7.

An example of the data format used in the multiplication/division method of the present invention is shown in FIGS. 3(a) and 3(b).

In Figure 3(a), 50 is the mantissa part of a 20-digit binary coded decimal number, etc., where two digits are banked into one byte.
1 is an exponent area that is expressed as a 16-bit binary number, 52 is an effective digit number area that expresses the number of effective digits of input data as a binary number, and 53 is a 1-byte identifier area.

FIG. 3(b) is an enlarged view of the 16-bit exponent region in FIG. 3(a).

In the figure, 54 is an exponent area that expresses the exponent in 16 bit binary numbers, 55 is a sign bit area that represents the sign of the exponent part,
56 is a sign bit area representing the sign of the mantissa.

The exponent area 54 is a binary number biased to 3fff with respect to the weight O with 10° as the reference value of decimal number 0. That is, for a weight of 0, 1 is stored in binary for each pI region in the exponential region. This allows a range of exponents up to ±16384 of 10 (2'4=16384).

The present invention converts the dividend and divisor in division and the multiplicand and multiplier in multiplication into normalized numbers in floating point format as described above, configures them into a data format as shown in FIG. 3(a), and performs arithmetic processing. conduct.

An embodiment of the division method using the data format according to the present invention will be described with reference to FIGS. 4 and 5.

FIG. 4 is a flowchart of the present invention, and FIG. 5 is a numerical example for explaining the division method of the present invention.

Refer to FIGS. 2 and 3 as necessary.

As shown in FIG. 5, operand P 1 =394117
1520 and the number of operations P 2 =80256, consider the case where P10P2 is processed.

Prior to division, a table of values obtained by multiplying the divisor P2 by an integer value from 1 to 9 is created.

Then, the quotient is determined by comparing the size of the dividend with the numerical value on the table.

This will be explained according to the flowchart shown in FIG.

■ Set initial conditions.

In other words, clear each operation register and write P to the operand register.
1, P2 is stored in the arithmetic register in normalized floating point format according to the data format shown in FIG.

(2) The search unit 31 sequentially retrieves values on the table from the table 32 and inputs them to the comparison unit 40. And comparison section 4
0 is the dividend (
(See Figure 5) and the value retrieved by the search unit, select a value smaller than the dividend and closest to the dividend, or the same value as the dividend, and from that table value, calculate the quotient and the dividend for the next calculation process. Calculate.

■ Confirm the position of the one-digit quotient obtained in ■ and store it in the final result register 35. ■ If the value of the quotient initially obtained is O (the first value of the quotient O), set a search flag and set the value. Set to 1.

■ Check the storage location of the quotient.

■ The search unit retrieves the dividend using ■ and subtracts the data on the table from which the quotient was obtained to obtain the remainder.

■ If the remainder value is 0, set the zero flag 1.

If the zero flag Zf=1, it means that the remainder is divisible by O, so the process ends.

(2) If the zero flag zr=o, it means that there is a remainder, so the division process is continued and the counter for the number of digits generated in the quotient is incremented by one.

(2) Check the search flag, and if the search flag data is not 0, the first numerical value of the quotient is not O, so judge whether the number of digits of the obtained quotient is greater or less than the number of effective digits, 20.

[Phase] If the number of generated digits exceeds 20, the quotient for the required number of digits has been obtained, and the process ends.

If the number is less than 20, the calculation process is further repeated.

(2) If the value of the search flag is 0 in the determination in (2), it means that the first numerical value of the quotient is 0, so it is determined whether the number of digits of the quotient is greater than or less than 21.

If the number of generated digits exceeds 21, the quotient for the required number of digits has been obtained, and the process ends. If the number is less than 21, the calculation process is further repeated.

(2) If the remainder is not 0 and the quotient is less than the required number of digits, the dividend is moved to a position to be compared with the divisor, and the division processing from (2) onwards is repeated.

■ If the leading numerical value of the quotient is O, the obtained quotient is normalized and the leading numerical value 0 is removed.

An embodiment of the multiplication method using the data format according to the present invention will be explained with reference to FIGS. 6 and 7.

FIG. 6 is a flowchart of the multiplication method of the present invention, and FIG. 7 is a numerical example for explaining the multiplication method of the present invention.

Refer to FIGS. 2 and 3 as necessary.

As shown in Figure 7, operand (multiplicand) P1 = 394
0629, the number of operations (multiplier) P 2 =80256, consider the case where P1×P2 is arithmetic processed.

Prior to multiplication, create a table 32 of integer multiples of the multiplicand P1 using integer values from 1 to 9, and search the numbers on the table for the value obtained by multiplying the multiplicand P1 by each digit of the multiplier P2. Obtain by drawing out.

Furthermore, in the method of the flow shown in the figure, the intermediate result register 30 stores the value obtained by multiplying the multiplicand P1 by the odd number digits of the multiplier P2 (see FIG. 7(b)).
AI, A3, A5) are respectively drawn from the table, A3 is an 8-bit intermediate result register, A5 is an odd-numbered intermediate result register that adds 16-bit left-shifted data, and the multiplicand P1 is multiplied by an even-numbered digit of the multiplier P2. Pull out the values (A2 and A4 in Figure 7(b)) from the table, and
4 is the result of using an intermediate result register of even number digits to which data shifted left by 8 bits is added, and the final multiplication result is obtained by shifting the addition result of even number digits to the left by 4 bits and adding it to the addition result of odd number digits. This is the flow when obtaining.

This will be explained according to the flowchart shown in FIG.

■ Clear the operand register 27 and the operand register 28 to zero, and store PL, which has a large number of digits in the mantissa part, in the operand register 2 as the multiplicand, as floating point format data in which Pl and P2 are normalized. Then, P2, which has a small number of digits in the mantissa part, is stored in the operation number register 28 as a multiplier.

■ Create a table of 1 to 9 times the multiplicand P1.

(2) Clear to zero the odd and even digit intermediate result registers 30 that store the value obtained by multiplying the multiplicand by the odd and even digits of the multiplier.

■ Determine whether the multiplicand is multiplied by all digits of the multiplier.

(2) If all the numbers have not been multiplied, the multiplication has not finished, so processing continues and it is determined whether the value of the lower digit (odd number digit) of the digits stored in one byte is 0.

■ If the result of ■ is not O, then the value (A1, A3, A5
), shift them to the left by a predetermined number of bits, and add them.

■ Determine whether the value of the upper bits (even number digits) of the multiplier byte area is 0. If it is 0, the next pie HE
Repeat the same process for the area.

(2) If it is not 0, extract the value multiplied by the value of the digit of the target multiplier from the table, shift it to the left by a predetermined bit and add it to the previous even-numbered digit calculation result.

Furthermore, the same process is repeated.

(2) Shift the operation result of the intermediate result register 30 of even number digits to the left by 4 bits.

[Phase] The operation result of the odd-numbered intermediate result register 30 is
Add the even-digit intermediate result register data obtained in .

■ Adjust the number of digits based on the calculation result of the exponent part to obtain the final result.

〔Effect of the invention〕

According to the present invention, since the mantissa part is normalized and the calculation is performed, 0 is not generated at the beginning of the numerical value, and unnecessary calculation processing that does not affect the calculation result can be eliminated. Furthermore, in multiplication and division processing, by providing a table of integral multiples of the divisor or multiplicand, it is possible to obtain the result of multiplying the multiplicand by each digit of the multiplier. The result of the arithmetic processing can be obtained at high speed despite the multiplication/division processing in decimal notation, which can be obtained without performing multiplication of the values contained in the data.

Further, the mantissa part can use the decimal representation entered by manual means as is, and also when outputting to the output means, the decimal representation format of the calculation result can be used as is.

[Brief explanation of drawings]

FIG. 1(a) is a basic configuration diagram of the present invention. FIG. 1(b) is a basic configuration diagram of the data format of the present invention. FIG. 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is an example diagram of the data format of the present invention. FIG. 4 is a flow diagram of the division method of the present invention. FIG. 5(a) is a diagram of an embodiment (1) of the table of the present invention. FIG. 5(b) is a diagram for explaining the division method of the present invention. FIG. 6 is a flow diagram of the multiplication scheme of the present invention. FIG. 7(a) is a diagram of Example (2) of the table of the present invention. FIG. 7(b) is a diagram for explaining the multiplication method of the present invention. FIG. 8(a) is an explanatory diagram of a conventional division method. FIG. 8(b) is an explanatory diagram of the conventional multiplication method. In FIG. 1(a), 2: memory, 3: floating point format conversion means, 4: normalization processing means, 5: calculation means, 6: 10 = 11. 13: ■ 4: 15: Memory, fixed-point data, 12: Register, operand register, operation register, arithmetic processing unit,

Claims (1)

[Scope of Claims] 1) In a method of performing multiplication and division using fixed-point decimal data as input, the input fixed-point decimal data is treated as a mantissa part with the number of significant digits expressed as a decimal number, A floating point format conversion means for converting weights into data in a binary representation format, and a normalization processing means for normalizing the converted floating point format data, the normalized floating point format data A multiplication/division method that performs multiplication/division in floating-point format by dividing the value into an exponent part and a mantissa part. 2) In the division method using the multiplication/division method according to claim 1, the calculation means includes a table for storing a value obtained by multiplying the divisor by 1 to 9, two registers for storing the operand and the operation number, and a division method for the division. A register to store the dividend in the arithmetic processing process, a register to store the quotient, and a register to store the quotient.To find the quotient, pull out the value on the table above, compare it with the dividend, and search for the closest value smaller than the dividend value or the same value. A division method characterized by comprising a search unit and performing division processing. 3) In the division method according to claim 2, as a result of the division process, a search flag data storage unit that identifies whether the leading numerical value of the quotient takes 0 or a value other than 0; and quotient generation. A generation digit number determination unit is provided to determine the number of digits, and the generation digit number determination unit refers to the search flag data, and if it is not divisible even after calculating the quotient of only the number of significant digits, the first numerical value of the quotient is not 0. If the first number is 0, the division process is performed until the quotient of the number of significant digits is obtained.If the leading number is 0, the division process is performed until the quotient of the number of digits is obtained by adding 1 to the number of significant digits. An arithmetic method characterized by the ability to 4) A method for performing multiplication using the multiplication/division method according to claim 1, comprising: a table for storing a value obtained by multiplying the multiplicand by 1 to 9; and two registers for storing the multiplicand and the multiplier; A search unit that extracts the value obtained by multiplying the multiplicand by the value of each digit of the multiplier, and an intermediate result storage register that stores the numerical value extracted by the search unit by shifting it by a predetermined bit and sequentially adding it, and storing the intermediate result of the multiplication. and a final result register for storing the final result of multiplication, and is characterized in that it performs multiplication.