JPH03188736A - Timing extraction system - Google Patents

Timing extraction system

Info

Publication number
JPH03188736A
JPH03188736A JP1328825A JP32882589A JPH03188736A JP H03188736 A JPH03188736 A JP H03188736A JP 1328825 A JP1328825 A JP 1328825A JP 32882589 A JP32882589 A JP 32882589A JP H03188736 A JPH03188736 A JP H03188736A
Authority
JP
Japan
Prior art keywords
timing
baud
baud timing
amplitude information
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1328825A
Other languages
Japanese (ja)
Inventor
Hideho Tomita
冨田 秀穂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1328825A priority Critical patent/JPH03188736A/en
Priority to US07/629,546 priority patent/US5122758A/en
Priority to EP19900313815 priority patent/EP0434355A3/en
Publication of JPH03188736A publication Critical patent/JPH03188736A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To extract a baud timing stably up to a low S/N by outputting amplitude information from a QPSK signal subject to n/4 shift modulation and extracting a timing component using a baud timing as a center frequency. CONSTITUTION:When the system is the n/4 shift modulation system and a signal point is transited at least to a position of + or -3/4n, since the amplitude is lowered considerably, a baud timing frequency component is generated. An envelope detection output by a rectifier circuit or an RSSI output whose envelope is subject to LOG transformation is used for an amplitude information detection means 1. The output passes through a narrow band filter 2 to extract the baud timing component.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、移動通信などに用いられるΠ/4シフトQP
SK信号のタイミング抽出において、比較的簡単な回路
構成で、低いS/Nまで安定にボー・タイミング抽出が
可能な方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to a Π/4 shift QP used in mobile communications, etc.
The present invention relates to a method for stably extracting baud timing down to a low S/N with a relatively simple circuit configuration in timing extraction of an SK signal.

(従来の技術) 陸上移動通信ではマルチ・パスによるフェーディングを
生じ、ランダムな搬送波位相変動をうける。このため低
速のデジタル通信では同期検波の採用は困難であり、通
常遅延検波が使用される。
(Prior Art) In land mobile communications, fading occurs due to multi-paths and is subject to random carrier wave phase fluctuations. For this reason, it is difficult to employ synchronous detection in low-speed digital communications, and delayed detection is usually used.

遅延検波をおこなうためには、あらかじめボー・タイミ
ングを知る必要がある。このためボータイミング抽出回
路は、搬送波復調以前に動作する必要がある。
To perform delayed detection, it is necessary to know the baud timing in advance. Therefore, the baud timing extraction circuit needs to operate before carrier demodulation.

従来Π/4シフト変調された搬送よりボー・タイミング
を抽出する方式てして第2図に示す方式が多く採用され
てきた。この方式は周波数弁別器101、整流回路10
2、狭帯域フィルタ103により構成されている。
Conventionally, the method shown in FIG. 2 has been widely adopted as a method for extracting baud timing from Π/4 shift modulated transport. This method includes a frequency discriminator 101, a rectifier circuit 10
2. It is composed of a narrowband filter 103.

この方式では入力搬送波信号を周波数弁別器101に通
し、周波数検出した後、整流回路102によりボー・タ
イミング成分を発生し、このタイミング成分を狭帯域フ
ィルタ103により抽出している。
In this method, an input carrier signal is passed through a frequency discriminator 101 to detect the frequency, a rectifier circuit 102 generates a baud timing component, and a narrow band filter 103 extracts this timing component.

(発明が解決しようとする課題) 前述した従来のΠ/4シフトQPSK変調信号よりのボ
ー、クロック抽出方式では入力S/Nが低下した場合、
ディスクリミネータによりスレッショルド効果を生じる
。さらにタイミング信号を発生させるための整流回路を
用いているためここでも同様にスレッショルド効果を発
生する。これら効果によリ、S/Nの低下時におけるボ
ー・タイミング抽出の安定性が大幅に低下してしまう。
(Problems to be Solved by the Invention) In the conventional baud and clock extraction method from the Π/4 shift QPSK modulation signal described above, when the input S/N decreases,
The discriminator creates a threshold effect. Furthermore, since a rectifier circuit is used to generate a timing signal, a threshold effect occurs here as well. These effects greatly reduce the stability of baud timing extraction when the S/N decreases.

本発明は、簡単な回路構成で、低いS/Nまで安定にボ
ー・タイミング抽出が可能な、方式を提供することを目
的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method capable of stably extracting baud timing down to a low S/N with a simple circuit configuration.

(課題を解決するための手段) Π/4シフト変調されたQPSK信号が入力されその振
幅情報を出力する振幅情報検出手段と、その出力からボ
ー・タイミングを中心周波数とするタイミング成分を抽
出する手段を有することを特徴とする。
(Means for Solving the Problems) Amplitude information detection means for inputting a QPSK signal subjected to Π/4 shift modulation and outputting its amplitude information, and means for extracting a timing component having a baud timing as a center frequency from the output thereof. It is characterized by having the following.

(作用) 本発明では搬送波振幅の情報を有する搬送波エンベロー
プ検出信号及びR85I(Recieved Sign
alStrength Indicator)出力信号
を入力し、この信号がボー・タイミング成分を有するこ
とがら、PLL(Phase Lock Loop)及
び、タンク回路等のような狭帯域のフィルタを用いて、
ボー・タイミングを伸出する。この方式により、少ない
付加回路で、比較的低いS/Hにおいても安定なタイミ
ング抽出が実現出来る。
(Function) In the present invention, a carrier wave envelope detection signal having carrier wave amplitude information and an R85I (Recieved Sign
alStrength Indicator) output signal, and since this signal has a baud timing component, a narrow band filter such as a PLL (Phase Lock Loop) and a tank circuit is used.
Extend bow timing. With this method, stable timing extraction can be achieved even at a relatively low S/H with a small number of additional circuits.

(実施例) 次に本発明の実施例について、図面を参照して説明する
。第1図は本発明の一実施例を示すブロック図である。
(Example) Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

実施例は振幅情報検出手段1、及び狭帯域フィルタ2と
を用いる。
The embodiment uses an amplitude information detection means 1 and a narrow band filter 2.

入力信号としてrr/4シフト変調されたQPSK搬送
波信号を入力し、振幅情報検出手段1によりボー・タイ
ミング信号成分を発生させる。Π/4シフト変調方式で
は少なくとも信号点が±374nの位置に遷移するとき
、振幅が大幅に低下するため、これによりポー、タイミ
ング周波数成分を発生する。振幅情報検出手段としては
整流回路によるエンベロープ検出出力、又はエンベロー
プがLOG変換されたR85I出力を用いる。この出力
を狭帯域フィルタ2に通過させることによりボー・タイ
ミング成分を抽出することが出来る。狭帯域フィルタと
しては、PLLまたはタンクによる方式が採用出来る。
A QPSK carrier wave signal subjected to rr/4 shift modulation is inputted as an input signal, and a baud timing signal component is generated by the amplitude information detection means 1. In the Π/4 shift modulation method, at least when the signal point transitions to a position of ±374n, the amplitude decreases significantly, thereby generating a po timing frequency component. As the amplitude information detection means, an envelope detection output from a rectifier circuit or an R85I output obtained by LOG-converting the envelope is used. By passing this output through the narrow band filter 2, the baud timing component can be extracted. As the narrowband filter, a PLL or tank system can be adopted.

ダイレクト・コンバージョン方式はAGC制御のために
振幅検出回路を有し、又、現在−膜内に用いられている
通常のスーパー・ヘテロダイン受信方式は受信電界強度
測定のため標準的にR85I信号を出力している。この
ため非常に少ない回路付加によりタイミング抽出機能を
実現出来る。
The direct conversion method has an amplitude detection circuit for AGC control, and the normal super-heterodyne reception method currently used in the membrane outputs an R85I signal as a standard for measuring received field strength. ing. Therefore, the timing extraction function can be realized with very little addition of circuits.

(発明の効果) 以上説明したように、本発明によれば比較的少ない回路
規模でボー・タイミング抽出機能を実現できる。また非
線形操作の次数が比較的少ないため、低S/Hにおいて
も安定なボー・タイミング抽出が期待出来る。
(Effects of the Invention) As explained above, according to the present invention, the baud timing extraction function can be realized with a relatively small circuit scale. Furthermore, since the order of nonlinear operation is relatively small, stable baud timing extraction can be expected even at low S/H.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す図、第2図は従来の方
式の一例を示す系統図である。 図において、1・・・振幅情報検出手段、2・・・狭帯
域フィルタ、101・・・周波数検出手段、102・・
・整流回路、103・・・狭帯域フィルタ・ 第1図
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a system diagram showing an example of a conventional system. In the figure, 1... amplitude information detection means, 2... narrowband filter, 101... frequency detection means, 102...
・Rectifier circuit, 103...Narrow band filter・ Fig. 1

Claims (1)

【特許請求の範囲】[Claims] (1)Π/4シフト変調されたQPSK信号が入力され
その振幅情報を出力する振幅情報検出手段と、その出力
からボー・タイミングを中心周波数とする成分を抽出す
る手段とを有するタイミング抽出方式。
(1) A timing extraction method comprising amplitude information detection means for inputting a QPSK signal subjected to Π/4 shift modulation and outputting its amplitude information, and means for extracting a component whose center frequency is the baud timing from the output.
JP1328825A 1989-12-18 1989-12-18 Timing extraction system Pending JPH03188736A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1328825A JPH03188736A (en) 1989-12-18 1989-12-18 Timing extraction system
US07/629,546 US5122758A (en) 1989-12-18 1990-12-18 Differential phase demodulator for psk-modulated signals
EP19900313815 EP0434355A3 (en) 1989-12-18 1990-12-18 Differential phase demodulator for psk-modulated signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1328825A JPH03188736A (en) 1989-12-18 1989-12-18 Timing extraction system

Publications (1)

Publication Number Publication Date
JPH03188736A true JPH03188736A (en) 1991-08-16

Family

ID=18214509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1328825A Pending JPH03188736A (en) 1989-12-18 1989-12-18 Timing extraction system

Country Status (1)

Country Link
JP (1) JPH03188736A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343502A (en) * 1991-11-29 1994-08-30 Nec Corporation Symbol timing detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343502A (en) * 1991-11-29 1994-08-30 Nec Corporation Symbol timing detecting circuit

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