JP3155285B2 - Slot timing synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a slot timing synchronization system in a radio communication system such as mobile communication and satellite communication.

[0003]

2. Description of the Related Art In recent years, the TDMA system has been widely used in wireless communication such as mobile communication and satellite communication. In particular, random access wireless packet communication is often used for control at the time of arrival and departure.

[0004] In these TDMA and wireless packet systems, data sent in bursts must be captured at high speed, and clock synchronization must be performed at high speed using a timing synchronization signal included in the captured data.

In general, the configuration of a burst used in these TDMA systems and the like is shown in FIG. That is, a BTR preamble 101, which is a preamble for timing phase synchronization, is arranged at the beginning of a burst, followed by the start of data 102 and a packet (burst).
Word (UW) 10 to clarify the attribute of
Three are arranged.

Conventionally, a method as shown in FIG. 8 has been used for such burst capture and clock synchronization. That is, the input signal is frequency-converted by the frequency conversion unit 111, and received signal strength I / S in the IF band.
The presence or absence of an input signal is detected by an input signal strength detector 112 called an ndicator). That is, when the input signal strength is equal to or more than a certain value, the input of the burst is detected. Further, when the input of the burst is detected, the received signal is detected by the detector 113.
And a clock extraction PLL 114 from its output.
The clock is extracted using the above. Then, the output of the detector 113 is determined and output by the determiner 115 according to the obtained clock timing.

[0007]

However, in the above-described conventional burst capture and clock synchronization, in the vicinity of the zone boundary of cellular mobile communication operating under low S / N or low C / I conditions or in satellite communication, RSSI
The number of erroneous detections when detecting the threshold value of the output is extremely large. Further, since the rise time of the RSSI is finite and the detection time of at least several symbols is required, the BTR preamble length needs to be longer than the clock phase detection time,
There was a problem that the frequency could not be used effectively.

[0008] In view of the above problems, an object of the present invention is to provide
An object of the present invention is to provide a slot timing synchronization system capable of detecting / capturing a burst and establishing clock synchronization with a short preamble in real time.

[Structure of the Invention]

[0010]

According to the present invention, in order to achieve the above-mentioned object, a reception signal is subjected to delay detection, and a timing reproduction signal included in the obtained detection signal is detected.
When TR detection signal output power of the timing detection filter having a narrow bandwidth than the received signal bandwidth to pass is larger than the predetermined value, a possibility that the burst signal is input is determined to be large, the filter Output power before
First, when the value exceeds the specified value, the filter
Is detected at the point where the output crosses the 0 level.
The timing synchronization is established based on the detection time . Then, an attempt is made to detect a unique word according to the established timing, and the unique word is detected as a result of the trial.
When it is issued, it is determined that the burst signal is truly input ,
If no unique word was detected as a result of the above trial
In this case, it is determined that the burst signal has not been input .

[0011]

According to the present invention, since a timing detection filter that passes only the BTR preamble signal in the input signal is used, when the BTR detection signal is input to this filter, the S / N ratio of the filter output is high. Value.
Therefore, the method of judging that the possibility that a burst signal has been input using the output of this filter has become large operates normally even under low S / N conditions. Therefore, clock synchronization can be obtained almost at the same time that the burst input probability is determined to be large, and burst capture determination including unique word determination can be performed. Therefore, high-speed input determination, synchronization, and capture can be performed under low S / N. Becomes At the same time, the loop enters the fine adjustment mode and has a small loop gain, thereby preventing the occurrence of pattern-dependent jitter of the reproduced clock at the time of receiving random data such as a unique word.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the slot timing synchronization system of the present invention will be described with reference to FIGS. FIG.
FIG. 3 is a functional block diagram illustrating a timing synchronization method. According to the figure, first, a received signal is subjected to delay detection by, for example, a delay detector 11 and then to a timing detection filter 1.
Enter 2 The output of the filter 12 is input to a burst peak threshold detector 13, and a burst (slot) signal is input by the burst peak threshold detector 13 depending on whether or not a received signal exceeds a threshold. Determine the magnitude of the possibility. Here, when it is determined that the possibility of the input of the burst signal is large, the output of the timing detection filter 12 has a sufficiently high S / N, and the clock phase is detected with extremely high accuracy and instantaneously from the output. You. Therefore, clock synchronization is obtained in the clock initial synchronization unit 14 using the output of the burst peak threshold value detection unit 13 and the output of the timing detection filter 12. The output of the delay detector 11 is sampled according to the timing thus obtained, and the determination is performed by the determination unit 15. This judgment value is input to the unique word judgment means 16 to judge the presence or absence of a unique word. Here, if the detection of the unique word is performed within a predetermined time from the time when it is determined that the possibility of the input of the burst signal is large, the burst capture determination unit 17 determines that the burst is truly captured, and Output the result.

According to the above method, the BTR in the input signal
A timing detection filter 12 is used that allows only the preamble signal to pass therethrough and does not allow other modulated signal wave components to pass. When a BTR detection signal is input to this filter 12, the S
The / N ratio has a considerably higher value than a detection signal obtained by detecting a general reception signal. Therefore, this filter 12
The method of judging that the possibility that a burst signal has been input by using the output of (1) is large operates normally even under a low S / N condition.

That is, as shown in FIG. 2, the spectrum 22 of the BTR detection signal is narrower than the spectrum 23 of the detection signal obtained by detecting a general reception signal. here,
The frequency characteristic 21 of the timing detection filter 12 is set to BT
By using a matched filter that matches the R detection signal spectrum 22, the output S / N of the filter 12 at the time of receiving the BTR preamble is maximized, and is therefore larger than the S / N of the reception filter output 24 as shown by the dashed line. Become.

As shown in FIG. 3, the signal format of the input signal is BTR preamble 31, unique word 3
2, data 33 are sequentially arranged, and are input to the timing detection filter 12. Then, when the output of the timing detection filter 12 exceeds the threshold value 34, it is detected that there is a high possibility that a burst has been input. Thereafter, a point at which the output of the timing detection filter 12 crosses the 0 level is detected for the first time, and the optimum timing is determined based on the point. Further, the detection output is sampled and determined according to the determined timing, and a unique word 3 is determined based on the data.
2 is detected. The unique word 32 is detected by the correlator, and it is determined that the burst has been completely captured. The above operation can be performed by software processing using a DSP or the like, digital signal processing configured by hardware, or analog processing.

When the Q value of the filter 12 is set to an appropriate value, the output of the BRT preamble 31 gradually increases. As the output increases, the S
The / N ratio gradually increases. When the output level of the filter 12 exceeds a predetermined threshold value 34, it is determined that there is a high possibility that a slot has been input. Since the output S / N of the filter 12 at this time is larger than the S / N of the input signal, if the optimum clock phase is instantaneously determined using the output of the filter 12 at this time, the optimum timing with high accuracy can be obtained. You can know the phase. That is, when the narrow-band output filter level exceeds a certain level, the arrival of a slot can be known at that time, and information about the clock phase can be extracted almost simultaneously. Therefore, since the slot synchronization and the clock synchronization are established at almost the same time,
These synchronizations can be established in a very short time. In other words, since the slot timing synchronization can be obtained with a short preamble, it is not necessary to add an unnecessarily long preamble to the transmission signal, and the frequency can be effectively used. The timing detection filter 1
2 is a BTR preamble 31
When the resonator resonates, B
Resonates at the same frequency as the TR preamble 31 while maintaining a constant phase relationship with the BTR preamble pattern.

Further, when the BTR preamble 31 is input to the timing detection filter 12,
Starts resonance and gradually increases its output. BTR
When the number of input symbols of the preamble 31 is about twice as large as the Q value of the filter 12, the output amplitude becomes substantially constant, and the output signal has a fixed phase relationship with the clock signal at half the clock rate. High S / N
Signal of the ratio.

As shown in FIG. 4, when the Q value is about half of the preamble length standardized by the number of symbols, the output is increased, the S / N ratio is increased, and the energy of the BTR signal is output without waste. Optimum for control and slot acquisition. As described above, slot synchronization is established.

However, there is a case where the same pattern as the BTR preamble 41 is included in the data 43 with a very low probability. In such a case, mere detection of the output of the timing detection filter 12 results in erroneous detection or erroneous synchronization. In order to prevent this, after performing burst detection and clock synchronization using the output of the timing synchronization filter, the unique word 42 is generated using this clock.
Is detected, and by detecting the unique word 42, it is determined that the synchronization of the slot has been normally performed, so that the probability of erroneous detection can be reduced and the synchronization process can be performed more reliably. Therefore, clock synchronization can be obtained almost at the same time when the burst input probability is determined to be large, and furthermore, burst capture determination including determination of the unique word 42 can be performed. Therefore, input determination and synchronization can be performed at high speed under low S / N. And capture is possible. At the same time, the loop enters the fine adjustment mode and the loop gain is small, so that the occurrence of jitter depending on the pattern of the reproduced clock at the time of receiving random data such as a unique word can be prevented.

As an example of the configuration of the timing detection filter 12, there is a secondary SSR filter as shown in FIG. This filter operates with a clock that is eight times the baud rate, and employs a modulation method such as π / 4 shift DQPSK and (10), (00), (10), (0)
When an alternating pattern such as 0), (10)... Is transmitted, a waveform obtained by delay detection of the transmitted pattern is input,
This is to extract a half frequency component of the baud rate clock. By setting the coefficients such as a and b as shown in the figure, a filter of about Q = 8 can be configured. Therefore, it is possible to cope with a preamble having a length of about 16 symbols using this filter.

FIG. 6 is a diagram showing an example in which the present invention is applied to a demodulator.

In the figure, a burst capture clock phase initial synchronization 48 is a part corresponding to claim 1 of the present invention, and includes a unique word det 46 and a burst input determination 4.
7 is a part corresponding to claim 2. In this system, after quadrature demodulation, both IQ quadrature signals are A / D converted, and thereafter all are performed by digital signal processing. In this method, following the clock phase synchronization method according to the present invention, clock phase error detection is further continued using the output of the detector, and fine adjustment is performed using this. This clock phase error detection circuit can perform a non-linear operation and a zero-cross detection of a narrow band filter and its output. The zero-cross position has a certain difference from the rising timing of the optimum clock, and it can be detected from how far the difference is from this difference.
The narrow band filter has a pass band in the baud rate clock component. If the signal is the input signal to the timing detection filter or the Q2 signal, both signals may be added and then input to the filter.

[0023]

As described above, according to the present invention, burst capture and clock synchronization can be instantaneously performed with a very short preamble even under low S / N conditions. Therefore, the preamble can be shortened and the frequency can be effectively used. In addition, it is possible to prevent the occurrence of jitter depending on the pattern of the reproduced clock.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a timing synchronization method according to the present invention.

FIG. 2 is an explanatory diagram of a spectrum of a BTR detection signal.

FIG. 3 is an explanatory diagram of a clock recovery and burst synchronization method according to the present invention.

FIG. 4 is an explanatory diagram of an input signal and a filter output of the present invention.

FIG. 5 is an explanatory diagram of a narrow band filter for a BTR.

FIG. 6 is a diagram illustrating an example in which the present invention is applied to a demodulation device.

FIG. 7 is a configuration diagram of a conventional burst.

FIG. 8 is an explanatory diagram of conventional burst capture and clock synchronization.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Delay detector 12 Filter for timing detection 13 Burst peak threshold detecting part 14 Clock initial synchronizing part 16 Uni-quad judging means 17 Burst capturing judging part

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/08

Claims (2)

(57) [Claims] 1. A method of delay detection of a received signal, and detection of a timing reproduction signal included in the obtained detection signal to obtain B
When TR detection signal output power of the timing detection filter having a narrow bandwidth than the received signal bandwidth to pass is larger than the predetermined value, a possibility that the burst signal is input is determined to be large, the filter The output power becomes larger than the predetermined value.
First, the output of the filter
A slot timing synchronization method characterized by detecting a point to be synchronized and establishing timing synchronization based on the intersection detection time . Wherein the timing recovery signal and a unique word signal to differential detection of including the received signal, the resulting detection signal
BTR obtained by detecting included timing reproduction signal
Has a bandwidth narrower than the reception signal bandwidth through which the detection signal passes
Output power of the timing detection filter
When the output power of the filter becomes larger than the predetermined value , it is determined that there is a high possibility that the burst signal has been input.
First, the output of the filter
The intersection point, and based on this intersection detection time,
Establish synchronization, and try to detect the unique word in accordance with the established timing.When the unique word is detected as a result of the trial , it is determined that a burst signal is truly input, and the unique word is detected as a result of the trial. Was not done
And a slot timing synchronization method for determining that a burst signal has not been input .