JP2540929B2 - Data transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention is applicable to wireless communication such as mobile communication, where the spread of the spectrum can be narrowed when a non-linear amplifier is applied on the transmitting side, and demodulation is performed by a simple method on the receiving side. The present invention relates to a possible wireless data transmission method.

(Prior Art) In mobile communication, from the viewpoint of effective use of limited frequencies and electric power, a modulation method in which the spread of the spectrum is narrow and a nonlinear amplifier can be applied is suitable. An offset QPSK method (OQPSK) has been conventionally known as one of the modulation methods that satisfy such conditions.

FIG. 4 is a diagram showing phase changes in the QPSK and OQPSK systems. The OQPSK method is a method in which the data of the quadrature component is delayed by one bit before the quadrature modulation and is modulated, and the change in the amplitude component is smaller than that of the QPSK method in which the quadrature modulation is performed without delaying the data. In QPSK, the amplitude once becomes 0 when the phase changes 180 °, but in OQPSK, the amplitude does not change 180 ° at a time, and the phase changes every 90 °, so the amplitude becomes 0.
And the change in amplitude is relatively small. Therefore, when a nonlinear amplifier is used, the spread of the spectrum is relatively small, and a signal with a narrow spectrum characteristic similar to QPSK can be obtained. Thus, OQPSK has an excellent point, but as disclosed in Japanese Patent Laid-Open No. 62-139450, unlike the QPSK system, the I and Q quadrature components are out of phase by π / 2. For this reason, it has been considered that only a synchronous detection method is applicable when a signal is demodulated and a carrier component is reproduced and divided into orthogonal components to determine a code.

(Problem to be solved by the invention) Therefore, the device for demodulation becomes complicated, and the pull-in time for carrier recovery is required, so that it is not suitable for a method of transmitting data in a short time such as burst transmission. There was a flaw.

In order to solve these drawbacks, an object of the present invention is to provide a data transmission method that enables simple demodulation on the receiving side when data transmission is performed by adopting the OQPSK method as a modulation method suitable for mobile signals. To provide.

(Means for Solving the Problem) A feature of the present invention for achieving the above-mentioned object is that the transmitting side performs a first sum / addition logical conversion on input data, and a cycle twice as long as the output and the clock. The second disjunction logical conversion is performed on the disjunctive logical sum with the signal having, and the output is sampled every 2 bits with a signal having a period twice the clock, and one of the 2-bit sample data is sampled. The signal delayed by one clock cycle and the other sample data are input as the in-phase and quadrature components of the quadrature modulator, and the offset QP
This is a data transmission method in which an SK signal is obtained and transmitted, and the receiving side demodulates by differential detection.

(Operation) The offset QPSK signal obtained by the above configuration can be easily demodulated on the receiving side, and can be demodulated by the combination of the differential detection, the full-wave rectification and the discrimination circuit used for demodulation of the conventional QPSK signal. The sum logical conversion and the disjunctive logical conversion on the transmitting side are important features of the present invention.

(Embodiment) FIG. 1 shows an embodiment of claim (1) of the present invention. The transmission data 1 is subjected to the sum logical conversion through the sum logical conversion circuit 3, the signal 2 having a period of twice the clock and the disjunctive logical sum are obtained, and again the sum logical conversion circuit 4 is performed. Then, the sampling circuit 5 samples 2 bits of a signal having a cycle twice that of the clock. The sum-and-logical conversion circuit is a circuit for performing an unconditional logical sum of the signal one bit before and the current signal.

Of the two bits, the previous 1 bit is directly input to the in-phase component of the quadrature converter 7, and the subsequent 1 bit passes through the delay circuit 6 to 1
It is delayed by a bit and input to the quadrature component of the quadrature modulator 7,
The signal is transmitted from the transmitting antenna 9 through the transmitter 8.

The transmitted wave 10 is received by the receiving antenna 11, and the receiver 12
And the reception signal 13 is output. Received signal 13 is delay circuit 14
Then, the signal is multiplied by the signal delayed by 1 bit and is subjected to delay detection through a low-pass filter 15 that removes high frequencies. This signal is input to the clock reproduction circuit 18 to reproduce the clock, rectified by the full-wave rectification circuit 16, identified by the identification circuit 17, and output as reception data 19.

The principle that the transmission data is reproduced on the receiving side by such a method will be described below. FIG. 2 shows an example of signals in each part of the embodiment of the present invention shown in FIG. The data that has been logically converted twice by sandwiching the disjunctive logical sum is 2
Each bit is sampled and one of the two bits is delayed by one bit to obtain the in-phase (I) component and the quadrature (Q), respectively.
It becomes a component and is modulated by the quadrature modulator. The phase of the modulated wave is I,
When the Q component is (1,1) it is 45 °, when it is (0,1) it is 135 °, (0,
It becomes 225 ° for 0) and 315 ° for (1,0). Differential detection output of the receiving side are output at SIN (ΔΦ _s) if the phase difference between the signal sent to 1 bit before and .DELTA..PHI _s. In other words, it outputs 1 when it increases by 90 °, -1 when it decreases by 90 °, and 0 when it does not change. When full-wave rectified, 1 is output when 1 or -1, and 0 is output when 0. In the discrimination circuit, when the rectified output is 1, the logical output 0 is output, and when the rectified output is 0, the logical output 1 is output, so that the transmission data can be reproduced on the receiving side as shown in FIG.

FIG. 3 shows another embodiment of the present invention. The transmission data 20 passes through a summation / logic conversion circuit 21 to undergo a summation / logic conversion to obtain a signal 22 having a double cycle of a clock and a disjunctive logical sum, and again passes through a summation / logic conversion circuit 23 to perform a summation / logic conversion. Then, the sampling circuit 24 performs 2-bit sampling with a signal having a cycle twice that of the clock. The first one bit of the two bits passes through the low pass filter 26 and is directly input to the in-phase component of the quadrature modulator 28, and the second one bit passes through the delay circuit 25 and is delayed by one bit, and passes through the low pass filter 27 and then the quadrature modulator. It is input to the quadrature component 28 and is transmitted from the transmission antenna 30 through the transmitter 29. The transmitted wave 31 is received by the receiving antenna 32, passes through the receiver 33, and outputs a received signal 34. The received signal 34 passes through a limiter 35, is multiplied by a signal delayed by 1 bit by a delay circuit 36, and is passed through a low-pass filter 37 for removing a high frequency and is subjected to delay detection. This signal is input to the clock reproduction circuit 38 to reproduce the clock, rectified by the full-wave rectification circuit 39, identified by the identification circuit 40, and output as reception data 41.

It is generally known that the transmission spectrum can be narrowed by passing a low-pass filter before inputting to the quadrature modulator. However, in such a signal that is band-limited and modulated at the base band, the phase fluctuates when the differential detection is performed on the receiving side, and the amplitude becomes small at the time when the amplitude is also determined, so that the data error rate characteristic with respect to the received signal level deteriorates. .
Therefore, the time response when the data of the low-pass filter that performs baseband band limitation is input is 1 at the time of judgment at the receiving side, that is, at the time of 1/2 bit before and after the center of the data input to the I and Q components. By taking a value and setting it to 0 in other cases, it is possible to obtain the same error rate characteristic as when band limitation is not performed. Further, since the information required for the differential detection is only the information on the phase difference, the data can be reproduced even if the received signal is passed through the limiter.

The differential detection output may be identified by two levels, and the logical output 0 may be output when 1 or −1 and the logical output 1 may be output when 0.

(Effects of the Invention) As described above, in the present invention, the OQPSK signal can be demodulated by differential detection to perform data transmission, so that the receiving device can be simplified and transmission of a short signal such as a burst signal can be performed. It has the advantage of being suitable. The present invention is not limited to wireless communication and can be applied to wired communication.

[Brief description of drawings]

FIG. 1 is an embodiment of claims (1) of the present invention, FIG. 2 is a diagram showing an example of signals of respective portions of the embodiment shown in FIG. 1, and FIG. 3 is another embodiment of the present invention. Example, FIG. 4 shows QPSK and OQ
It is a figure showing a phase change of a PSK modulation system. 1: Transmission data, 2: Signal with twice the cycle of clock, 3: Addition-and-deduction logic conversion circuit, 4: Addition-and-deduction logic conversion circuit, 5: Sample circuit, 6: Delay circuit, 7: Quadrature modulation circuit, 8: Transmitter, 9: transmit antenna, 10: transmit wave, 11: receive antenna, 12: receiver, 13: receive signal, 14: delay circuit, 15: low-pass filter, 16: full-wave rectifier circuit, 17: identification circuit, 18: Clock recovery circuit, 19: Received data, 20: Transmission data, 21: Addition / disjunction logic conversion circuit, 22: Signal with twice the cycle of clock, 23: Addition / disjunction logic conversion circuit, 24: Sample circuit, 25: Delay circuit, 26: Low-pass filter, 27: Low-pass filter, 28: Quadrature modulation circuit, 29: Transmitter, 30: Transmit antenna, 31: Transmit wave, 32: Receive antenna, 33: Receiver, 34: Receive signal, 35 : Limiter, 36: Delayed signal, 37: Low pass filter, 38: Clock recovery, 39: Full wave rectification, 40: Discrimination circuit, 41: Received data.

Claims (2)

(57) [Claims] 1. The transmitting side performs a first summation logical conversion on input data, and a second summation is performed on the output logical sum of its output and a signal having a cycle twice that of a clock. Logic exchange is performed, the output is sampled every 2 bits by a signal having a cycle of twice the clock, and one of the 2-bit sample data is delayed by 1 clock cycle and the other sample data is quadrature modulator. A data transmission method characterized by inputting as the in-phase and quadrature components of, obtaining and transmitting an offset QPSK signal, and demodulating by differential detection on the receiving side. 2. The transmitting side is passed through a low-pass filter before inputting the data to the quadrature modulator, and the time response of the data obtained by passing the low-pass filter is at a time point of 1/2 of the clock cycle before and after the center of the data. 2. The data transmission method according to claim 1, wherein the value becomes 1 every time, and the value becomes 0 each time a clock cycle is deviated from the time.