JPH0318778A - Integrated circuit element inspection device - Google Patents

Integrated circuit element inspection device

Info

Publication number
JPH0318778A
JPH0318778A JP1153434A JP15343489A JPH0318778A JP H0318778 A JPH0318778 A JP H0318778A JP 1153434 A JP1153434 A JP 1153434A JP 15343489 A JP15343489 A JP 15343489A JP H0318778 A JPH0318778 A JP H0318778A
Authority
JP
Japan
Prior art keywords
signal
analog
output
digital
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1153434A
Other languages
Japanese (ja)
Inventor
Shunichi Usui
臼井 俊一
Yoshitaka Sogo
十河 芳孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP1153434A priority Critical patent/JPH0318778A/en
Publication of JPH0318778A publication Critical patent/JPH0318778A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To facilitate the inspection by fetching an input waveform and an output waveform to the inside of a memory with an analog/digital converter, restoring the input waveform, based thereon as a reference, bringing an output signal to analog/digital conversion and comparing it with the data of the inside of the memory. CONSTITUTION:The input waveform and the output waveform of a DUT 2 are inputted to input/output signal memory devices 12, 13 by analog/digital converters 8, 9. As for a signal stored in the device 12, under the control of a controller 17, the input signal of the DUT 2 is restored and applied to an input terminal by a digital/analog converter 14. The output of the DUT 2 is brought to digital conversion by an analog/digital converter 15 under the control of the controller 17, compared with the signal of the part of the same operation as the output of the reference DUT stored in the device 13 by a comparator 16 and the propriety is decided by the controller 17. In such a manner, the evaluation and the inspection can always be executed easily in the same state as unitial setting.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、集積回路素子製造時の検査装置開発工程の効
率化を図った集積回路素子検査装置に関するものである
DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an integrated circuit device testing device that improves the efficiency of the testing device development process during integrated circuit device manufacturing.

従来の技術 第2図は、従来の集積回路素子の評価、検査装置の概念
図を示すものである。被測定集積回路素子(以下OUT
という)2には、信号源1、受信機e等で与えられる信
号が印加され、一方DUT周辺回路4からは電源、コン
デンサ、抵抗等の周辺部品が接続されている。DUTの
出力は信号処理装置3に接続されDUT2出力の復調、
信号処理を行いコントローラ6t*はモニタ7にその結
果を渡し、良否判定をコントローラ6が行い、方モニタ
7は音声、画像等を出力し、人による官能検査を行い良
否判定を行う。
BACKGROUND OF THE INVENTION FIG. 2 is a conceptual diagram of a conventional integrated circuit device evaluation and inspection device. Integrated circuit element under test (hereinafter referred to as OUT
) 2 is applied with a signal given by a signal source 1, a receiver e, etc., while a DUT peripheral circuit 4 is connected to peripheral components such as a power supply, a capacitor, and a resistor. The output of the DUT is connected to the signal processing device 3, which demodulates the output of the DUT2,
The controller 6t* performs signal processing and passes the result to the monitor 7, and the controller 6 makes a quality determination.The monitor 7 outputs audio, images, etc., and performs a sensory test by a person to determine quality.

発明が解決しようとする課題 この例で分るように、従来の評価、検査方法では、DU
T2の信号源1はDUT20種類、例えばラジオ用、T
V用、コンピュータ用等のように入力の信号は一種類で
はない。従って第2図の点線で示すようκ信号源1を、
例えばラジオ受信機やTV受信機のような受信機6とし
たりする必要がある。同様に信号処理装置3、モニタ7
についても同様でありDUT2の種類に依って、例えば
TVモニタとかスピーカとかに切換える必要がある。一
方この1筐では官能検査があり生産工程には向いていな
い。従って官能検査の部分については、自動判定の出来
る検査仕様を作或するため入力信号の設定基準、出力信
号の判定基準等を明確にする工程が必要となる。
Problems to be Solved by the Invention As can be seen from this example, in the conventional evaluation and inspection method, the DU
Signal source 1 of T2 has 20 types of DUTs, for example, for radio, T
There is not just one type of input signal, such as for V, computer, etc. Therefore, as shown by the dotted line in FIG. 2, the κ signal source 1 is
For example, the receiver 6 needs to be a radio receiver or a TV receiver. Similarly, signal processing device 3, monitor 7
The same goes for DUT 2, and depending on the type of DUT 2, it is necessary to switch to, for example, a TV monitor or a speaker. On the other hand, this one box requires sensory testing and is not suitable for production processes. Therefore, regarding the sensory test part, in order to create test specifications that allow automatic judgment, a step is required to clarify the setting criteria for input signals, the judgment criteria for output signals, etc.

課題を解決するための手段 この問題を解決するため、本発明はDUT2の入力波形
と出力波形とをアナログ・デジタル変換器でメモリ内に
取込み、それを基準にして被測定集積回路素子の入力彼
形を復元して与え、出力信号はアナログ・デジタル変換
して、前記メモリ内のデータと比較して良否判定する様
にすることで.この問題を解決する。即ち高価な入力信
号源を用意する必要もなく、出力モニタについても考え
る必要がない。一方官能検査についての検査仕様を明確
にする工程も必然的に省略出来る。
Means for Solving the Problem In order to solve this problem, the present invention captures the input waveform and output waveform of the DUT2 into a memory using an analog-to-digital converter, and uses the input waveform and output waveform of the integrated circuit device under test as a reference. By restoring the shape and giving it, the output signal is converted from analog to digital, and compared with the data in the memory to judge whether it is good or bad. Solve this problem. That is, there is no need to prepare an expensive input signal source, and there is no need to consider an output monitor. On the other hand, the process of clarifying test specifications for sensory tests can also be naturally omitted.

作用 との構戊により、従来の評価、検査方法の場合必要な多
種類の信号源、受信機、モニタが必要でな〈なる。筐た
この方法を用いることで当初の評価時の状態が常に復元
、維持され、製品品質の維持確保を図ることができる。
The combination of functions eliminates the need for multiple types of signal sources, receivers, and monitors, which are required with conventional evaluation and inspection methods. By using Kakitoko's method, the state at the time of initial evaluation is always restored and maintained, making it possible to maintain and ensure product quality.

実施例 第1図は、本発明による集積回路素子検査装置の概念図
である。第2図は従来の方法による概念図を示している
が、一方ではこの方法が検査の基準となる。従って以後
は基準の装置、基準DUT等は第2図で代行して以下の
説明をする。第1図において、アナログ・デジタル変換
器8の入力は基準DUTの複数の入力端子に、アナログ
・デジタル変換器9は、基準DUTの複数の出力端子に
夫々接続されている。コントローラ5のコントロール信
号で基準装置(第2図)と本発明による第1図のコント
ローラ17によって夫々の装置を起動する。基準装置は
従来どおりに基準動作を当然を行う。一方アナログ・デ
ジタル変換器8.9はコントローラ17の制御によって
基準DUTの入力,出力信号をデジタル変換し、データ
圧縮器10.11でデジタル信号をデータ圧縮して入力
信号,出力信号メモリ装置12.13に記憶させる。以
後同様の手順を繰り返し基準装置での基準1)UTでの
入力,出力の信号波形をメモリ装置12.13に取り込
む。(以後はこの基準装置は必要ない。) この入力信号メモリ装置12に記憶されている信号をコ
ントローラ17の制仰の下に、DUT周辺回路4を起動
し電源電圧C,R等をDUT2に接続し、デジタル・ア
ナログ変換器14で、DUT2の入力信号を復元し入力
端子に印加する。一方DUT2の出力は通常の場合、入
力信号に従って基準装置と同様の信号を出力する。この
出力はコントローラ17の制御の下でアナログ・デジタ
ル変換器15でデジタル変換し、出力信号メモリ装置1
3内に記憶されている基準DUTの出力と同じ動作の部
分の信号と比較器16で比較し良否判定をコントローラ
17で行う。コントローラ17は入力信号メモリ装置1
2を起動すると同時に、出力信号メモリ装置13を起動
する事で、DUT2の出力信号の出力するタイミングを
合せる事が出来るはずだが、実際には周辺回路、デジタ
ル、アナログ変換器、アナログ・デジタル変換器等の動
作遅延がある。一方DUT2の動作遅延、誤動作等があ
り同期合せが場合によっては必要になり、入力信号の再
入力等の同期合せ処理が必要となる。
Embodiment FIG. 1 is a conceptual diagram of an integrated circuit device testing apparatus according to the present invention. FIG. 2 shows a conceptual diagram of the conventional method, which on the one hand serves as the standard for inspection. Therefore, from now on, the reference device, reference DUT, etc. will be referred to in FIG. 2 for the following explanation. In FIG. 1, the input of the analog-to-digital converter 8 is connected to a plurality of input terminals of a reference DUT, and the analog-to-digital converter 9 is connected to a plurality of output terminals of the reference DUT. Control signals from the controller 5 activate the respective devices by means of the reference device (FIG. 2) and the controller 17 of FIG. 1 according to the invention. The reference device performs the reference operation as usual. On the other hand, the analog-to-digital converter 8.9 digitally converts the input and output signals of the reference DUT under the control of the controller 17, and the data compressor 10.11 compresses the digital signal and input and output signals are stored in the memory device 12. 13 to be memorized. Thereafter, the same procedure is repeated and the reference 1) input and output signal waveforms at the UT are captured in the memory device 12.13. (This reference device is not needed after this.) Under the control of the controller 17, the signal stored in the input signal memory device 12 activates the DUT peripheral circuit 4 and connects the power supply voltages C, R, etc. to the DUT 2. Then, the digital-to-analog converter 14 restores the input signal of the DUT 2 and applies it to the input terminal. On the other hand, the output of the DUT 2 normally outputs a signal similar to that of the reference device according to the input signal. This output is digitally converted by an analog-to-digital converter 15 under the control of a controller 17, and an output signal memory device 1
A comparator 16 compares the signal with a signal of the same operation as the output of a reference DUT stored in the DUT 3, and a controller 17 makes a quality determination. The controller 17 has an input signal memory device 1
By activating the output signal memory device 13 at the same time as activating the DUT 2, it should be possible to synchronize the output timing of the output signal of the DUT 2. However, in reality, peripheral circuits, digital, analog converters, and analog/digital converters There is a delay in operation. On the other hand, synchronization may be necessary in some cases due to operational delays, malfunctions, etc. of the DUT 2, and synchronization processing such as re-inputting input signals is required.

またDUT2の特性バラツキによるデータのバラツキが
生じた場合、比較器16での単なるデジタル信号の比較
では誤判定となり、上限,下限の値による判定が必要に
なる。これらの制御をコントローラ17が行う。
Furthermore, if data variations occur due to variations in the characteristics of the DUT 2, mere comparison of digital signals by the comparator 16 will result in an erroneous determination, and determination based on upper and lower limit values is required. The controller 17 performs these controls.

発明の効果 本発明の集積回路素子検査装置を用いる事で、当初設定
と常に同じ状態で評価、検査を容易に行う事が出来、官
能検査についての良否判定も容易に設定出来る。
Effects of the Invention By using the integrated circuit device testing device of the present invention, evaluation and testing can be easily performed in the same state as initially set, and pass/fail judgments regarding sensory tests can also be easily set.

【図面の簡単な説明】 第1図は本発明の集積回路素子検査装置を示す概念図、
第2図は従来例の概念図である。 1・・・・・・各種の信号波形を発生する信号源、2・
・・・・・被測定集積回路素子であるDtJT、3・・
・・・・D[TT2の出力信号の復調.変調等を行う信
号処理装置、4・・・・・・DUT2の電源.コンデン
サ,抵抗等の周辺回路部、6,17・・・・・・全体の
制御、良否判定等を行うコントローラ、6・・・・・・
信号源1で得られない信号を得るためのTV,ラジオ等
の受信機、7・・・・・・官能検査をするための画像,
音声等のモニタ、8・・・・・・DUT入力端子の信号
を読取るアナログ・デジタル変換器、9・・・・・・D
UT出力端子の信号を読取るアナログ・デジタル変換器
、10.11・・・・・アナログ・デジタル変換器8.
9の出力デジタル信号を圧縮するデータ圧縮器、12.
13・・・・・データ圧縮器10 .1 1で夫々圧縮
された入力.出力の信号を記憶するメモリ装置、14・
・・・・・入力信号復元用デジタル・アナログ変換器、
16・・・・DUT2の出力信号取込み用アナログ・デ
ジタル変換器、16・・・・・・アナログ・デジタル変
換器16の出力デジタル信号とメモリ装置13に記憶さ
れている基準DUTの出力デジタル信号とを比較する比
較器。
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a conceptual diagram showing an integrated circuit device testing apparatus of the present invention;
FIG. 2 is a conceptual diagram of a conventional example. 1... Signal source that generates various signal waveforms, 2.
... DtJT, 3, which is the integrated circuit element to be measured.
...D[Demodulation of the output signal of TT2. Signal processing device that performs modulation, etc., 4...Power source for DUT2. Peripheral circuits such as capacitors and resistors, 6, 17... Controller for overall control, quality judgment, etc., 6...
Receiver for TV, radio, etc. for obtaining signals that cannot be obtained from signal source 1, 7... images for sensory testing,
Monitor for audio, etc., 8... Analog-to-digital converter for reading signals from the DUT input terminal, 9...D
Analog-to-digital converter for reading the signal of the UT output terminal, 10.11...Analog-to-digital converter8.
a data compressor for compressing the output digital signal of 9; 12.
13...Data compressor 10. 1 Input compressed by 1 respectively. a memory device for storing output signals, 14.
...Digital-to-analog converter for input signal restoration,
16... Analog-to-digital converter for capturing the output signal of DUT 2, 16...... Output digital signal of the analog-to-digital converter 16 and output digital signal of the reference DUT stored in the memory device 13. Comparator to compare.

Claims (1)

【特許請求の範囲】[Claims] 基準となる評価装置に組み込まれた集積回路素子の複数
の入力端子、出力端子の信号波形を複数のアナログ・デ
ジタル変換器でメモリに取込み、そのメモリ内容を読み
出して複数のデジタル・アナログ変換器で前記入力信号
を復元して被測定集積回路素子の入力端子に印加し、そ
の被測定集積回路素子の出力信号を前記アナログ・デジ
タル変換器でデジタル変換した信号と、前記メモリ内の
出力信号相当の信号とを比較して良否判定する事を特徴
とする集積回路素子検査装置。
The signal waveforms of the multiple input terminals and output terminals of the integrated circuit element incorporated in the standard evaluation device are captured into memory using multiple analog-to-digital converters, and the memory contents are read out and processed using multiple digital-to-analog converters. The input signal is restored and applied to the input terminal of the integrated circuit element under test, and the output signal of the integrated circuit element under test is converted into a digital signal by the analog-to-digital converter, and the output signal equivalent to the output signal in the memory is converted into a digital signal. An integrated circuit device testing device characterized by comparing signals to determine pass/fail.
JP1153434A 1989-06-15 1989-06-15 Integrated circuit element inspection device Pending JPH0318778A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1153434A JPH0318778A (en) 1989-06-15 1989-06-15 Integrated circuit element inspection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1153434A JPH0318778A (en) 1989-06-15 1989-06-15 Integrated circuit element inspection device

Publications (1)

Publication Number Publication Date
JPH0318778A true JPH0318778A (en) 1991-01-28

Family

ID=15562438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1153434A Pending JPH0318778A (en) 1989-06-15 1989-06-15 Integrated circuit element inspection device

Country Status (1)

Country Link
JP (1) JPH0318778A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015017991A (en) * 2014-09-09 2015-01-29 株式会社半導体エネルギー研究所 Inspection method
KR20160085463A (en) * 2015-01-08 2016-07-18 김갑식 A device for wearing a key

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015017991A (en) * 2014-09-09 2015-01-29 株式会社半導体エネルギー研究所 Inspection method
KR20160085463A (en) * 2015-01-08 2016-07-18 김갑식 A device for wearing a key

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