JPH09261692A - Operation testing device for signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a simple test in the real operation cycle of the LSI of an actually mounted circuit by comparing the expected value of the operation result of a signal processing circuit for operation setting conditions with the test result of a test result detection means and testing the operation of the signal processing circuit. SOLUTION: A test timing control circuit 5 controls the operation timing of a test pattern generation circuit 7 and a test result detection circuit 9 based on synchronizing signals VD and HD supplied to a circuit 2 to be tested. A CPU 138 is provided with an expected value setting means, an operation setting and test mode setting means and a comparison means. Then, the CPU 138 sets a test mode by the optional operation setting conditions of the circuit 2 to be tested, compares the expected value EP of the operation result of the circuit 2 to be tested for the operation setting conditions with the test result DP of the test result detection circuit 9 and tests the operation of the circuit 2 to be tested. Thus, the test is performed by using actual synchronizing signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, an LSI.
The present invention relates to a signal processing circuit operation test device suitable for use in an operation test of (large-scale integrated circuit).

[0002]

2. Description of the Related Art Conventionally, in order to confirm whether or not a predetermined quality is maintained at the final stage of mass production shipment of LSI manufacturing processes, an operation test is individually performed on each LSI. Was doing. The operation test method for performing the operation test of the LSI includes a method of mounting the LSI on the LSI tester to perform the test and a method of having the tester mechanism inside the LSI and LS.
I itself is roughly divided into a method of checking the quality of the LSI.

First, the LSI tester will be described. L
The SI tester has a built-in CPU equivalent to a mini computer, controls to automatically generate various signals required for testing according to a test program, and measures electrical characteristics of large-scale integrated circuits. It is a device. The configuration of the LSI tester will be described below. The LSI tester
It has a test processor and tester hardware.
The tester hardware has a timing generation section, a test pattern generation section, a waveform control section, a station, and a DC parameter measurement section.

The test processor interprets the test program, appropriately transmits necessary test conditions to the tester hardware, and receives the test result to perform data processing and the like. The timing generator generates a test rate and a clock timing signal. The test pattern generator is
It has the function of generating a sequential pattern generator, an algorithmic pattern generator, or a composite pattern of these. The waveform controller receives the timing signal and the test pattern signal and generates various waveforms such as NRZ and RZ. The station has a pin mounting part for mounting an LSI as a sample, a comparator for comparing an output pattern and an expected value pattern, and a display part for a non-defective product and a defective product. The DC parameter measurement unit is a measurement circuit that can be connected to each pin of the sample and tests the DC characteristics such as the power supply current of the sample and the input leakage current.

The LSI tester configured as described above operates as follows. First, the LSI as a sample is mounted on the pin mounting portion of the station. When the test is started, the input test pattern, the expected value pattern, and the clock timing signal are supplied from the test pattern generator to the waveform controller at the test rate set by the timing generator. The expected value pattern is a response value when the operation of the LSI is normal. Here, since the input test pattern and the expected value pattern are used for the operation test of various functions of the LSI, they are called test vectors or function vectors and require 120,000 to 130,000 vectors. The waveform control unit formats the input test pattern and the expected value pattern into a predetermined waveform with the clock timing signal. The formatted input test pattern is applied to the LSI as a sample mounted on the pin mounting portion of the station. The output pattern output from the LSI as the sample is compared with the expected value pattern by the comparator. When the output pattern is different from the expected value pattern, the display unit displays the defective product, and when the output pattern is the same as the expected value pattern, the display unit displays the non-defective product. In this way,
Detailed tests can be performed using a large number of function vectors.

Next, a tester mechanism is provided inside the LSI and L
A built-in test device in which the SI itself checks the quality of the LSI will be described. Since the built-in test device is provided inside the LSI, it is necessary to have a small-scale and simple configuration. This built-in test method is called BIST (Built).
In Self Test). The built-in test device has a signal processing circuit inside the LSI, a test pattern generation unit, and an output pattern determination unit. The signal processing circuit is a circuit on which an internal operation test is performed. The test pattern generator is a random number test pattern that can be generated by simple hardware, a pseudo random pattern, an exhaustive pattern,
Or a pattern with a strong regularity is generated. The output pattern determination unit has a comparator that compares the output pattern with the expected value pattern.

The built-in test apparatus thus constructed operates as follows. When the test is started, the input test pattern, the expected value pattern, and the clock timing signal are supplied from the test pattern generating unit to the signal processing circuit of the LSI based on the control signal supplied from the outside. The input test pattern is a random signal such as a random number test pattern. The expected value pattern is a response value when the operation of the signal processing circuit of the LSI is normal. Here, the input test pattern and the expected value pattern are LS
Since it is used for the operation test of the specified signal processing circuit inside I, the test condition is only one state. The test conditions include the amplitude of the input / output pattern, the operating power supply voltage, the test timing, the test pattern, the operation setting of the signal processing circuit at the time of the test, the combination of these conditions, the test flow, and the like.

The input test pattern is applied via the bus line of the signal processing circuit of the LSI. The output pattern output from the signal processing circuit is compared with the expected value pattern by the comparator. When the output pattern is different from the expected value pattern, the defective product is displayed and displayed, and when the output pattern is the same as the expected value pattern, the good product is displayed and displayed on the external display unit. In this way, a simple test can be performed.

Further, as a method for facilitating the above-described BIST test method, there is another built-in test apparatus described below. The built-in test device has a signal processing circuit inside the LSI and a flip-flop in which the periphery of the signal processing circuit is connected in a chain shape so as to surround each terminal of the LSI. Such a scanning method is called a Boundary Scan method.

Such a built-in test apparatus operates as follows. When the test starts, the state of each flip-flop is externally written and read at high speed by using the function of the flip-flop shift register, and the value of each flip-flop is arbitrarily controlled, observed and scanned. This facilitates generation of a test pattern for a sequential circuit. In this way, a large amount of test patterns can be processed at high speed and with high accuracy.

[0011]

However, in the method of performing the LSI operation test by using the function vector in such a conventional LSI tester, a detailed test can be performed by using the function vector. Since an expensive LSI tester is needed and the test cycle is determined by the LSI tester,
There is an inconvenience that it is difficult to perform a test in the actual operation cycle of the LSI of the actually mounted circuit.

When a detailed test is to be realized by a simple internal operation test, the test circuit added to the LSI becomes complicated and large, and the test vector to be used also becomes huge. Therefore, there is an inconvenience that the cost required for the test increases.

Further, the conventional BIST test method has a signal processing circuit, a test pattern generation section, and an output pattern determination section inside the LSI, and although it can be used for test automation, it does not operate in a certain fixed state. There was the inconvenience that we could not respond unless the test conditions.

In the conventional boundary scan test method, since the test vector is handled as serial data, the test cannot be performed in the actual operation cycle of the LSI and the test time becomes long.

The present invention has been made in view of the above points, and an object thereof is to provide an operation test apparatus for a signal processing circuit capable of performing a simple test in an actual operation cycle of an LSI of an actually mounted circuit. And

[0016]

An operation testing apparatus for a signal processing circuit according to the present invention comprises a test pattern generating means for generating a test pattern for testing the internal operation of the signal processing circuit, and a test pattern for the signal processing circuit based on the test pattern. A test result detecting means for detecting a result of testing the internal operation, and a test timing control means for controlling operation timings of the test pattern generating means and the test result detecting means based on the synchronization signal supplied to the signal processing circuit. , A test mode is set for the signal processing circuit according to any operation setting condition, and the expected value of the operation result of the signal processing circuit with respect to the operation setting condition is compared with the test result of the test result detecting means to compare the signal processing circuit It is designed to test the operation.

According to the present invention, the following operations are performed. When the internal operation test is started, the control signal and the setting data are supplied to the test timing control means in accordance with the operation program under the specified operation condition. The signal processing circuit sets the setting data at the internal setting point. The test timing control means generates a test timing signal based on the sync signal and the control signal supplied from the system. The test timing signal is supplied to the test pattern generating means and the test result detecting means.

The test pattern generating means generates a test pattern based on the test timing signal. The test pattern is supplied to the signal processing circuit instead of the normal signal. The signal processing circuit regards the test pattern as a normal signal and performs the same operation as the normal operation based on the same synchronization signal as the normal operation. However, at this time, the circuit in which the signal processing circuit operates changes depending on the operation setting for the signal processing circuit, and the state of the output signal also changes. The signal output from the signal processing circuit is supplied to the test result detecting means.

The test result detecting means detects the operation status of the signal processing circuit based on the test pattern in accordance with the test timing signal. The test result detecting period of the test result detecting means is one cycle period of the synchronizing signal. The test result detecting means continues the test until the test result detecting period ends. This is because a certain amount of time is required from the start to the end of the test, so that a waiting time is ensured so that the test result can be retrieved reliably. Since the test result from the test result detecting means is integrated for each output signal, the test result for every output signal is taken out.

The expected value obtained in advance is compared with the test result fetched from the test result detecting means to judge whether the internal operation of the signal processing circuit is correct. Since the expected value is uniquely determined by the operating condition at the start of the test, this expected value is compared with the test result for each output signal. Preliminarily obtain a plurality of operation setting conditions for test operation and expected values for those settings, perform an operation test under an arbitrary operation condition, and automatically perform a plurality of operation tests while changing operation settings. As described above, since the operation programs for a plurality of modes are provided, a plurality of test modes may be set under different operating conditions. In this case, the internal operation setting is set to the next test mode, and the previous processing and judgment are repeated. When all the modes are completed, the operation of the test timing control means is stopped, all the internal operation settings of the signal processing circuit are returned to the original settings, and the operation is completed.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION This embodiment will be described below. First, a camera system using the operation testing apparatus for the signal processing circuit of this embodiment will be described. The configuration of the color correction and shading correction unit of the camera system will be described with reference to FIG. The color correction and shading correction unit of the camera system has a filter control section, a shutter control section, a black correction and gain control section, a white correction, a flare correction and a pleni control section.

The filter control section includes a lens 100 and a C
It has a C filter 101 and an ND filter 102. The shutter control unit includes the R CCD 103R and G
It has a CCD 103G, a B CCD 103B, and a timing generator 114. In addition, the black correction and gain control unit includes preamplifiers 104R, 104G, 10
4B and black correction signal adding circuits 105R, 105G, 10
5B, amplifiers 106R, 106G and 106B, trap filters 107R, 107G and 107B, gain amplifiers 108R, 108G and 108B, and a D / A converter 115. The white correction, flare correction, and pliny control units are provided in the gain control amplifiers 109R and 109R, 10R.
9G, 109B and flare correction signal adding circuit 110R,
110G, 110B and level compression circuits 111R, 11
1G, 111B, D / A converter 116, LPF 11
2R, 112G, 112B and A / D converter 113R,
It has 113G and 113B.

The operation of the color correction and shading correction unit of the camera system thus configured will be described. The light B entering from the lens 100 is adjusted in color temperature by the CC filter 101, adjusted in brightness by the ND filter 102, and then decomposed into R, G, B lights by a spectral prism or the like not shown. The light of R, G, B is R
CCD103R, G CCD103G, B CCD1
In 03B, it is converted into a video signal as an electric signal. R
CCD103R, G CCD103G, B CCD10
3B is C made by the timing generator 114.
It operates by the CD drive pulse DP, and the shutter speed is changed by changing the CCD drive pulse DP. CC filter control signal CFC supplied to CC filter 101 and ND filter 102
And ND filter control signal CFC, shutter control signal ST supplied to the timing generator 114
C is supplied from the CPU 138 described later.

R CCD103R, G CCD103
The video signal converted by the G, B CCD 103B is
It is supplied to the preamplifiers 104R, 104G, and 104B. The video signals pre-amplified by the preamplifiers 104R, 104G, and 104B are the black correction signal adding circuits 105R and 1R.
It is supplied to 05G and 105B. Black correction signal addition circuit 1
05R, 105G, and 105B are based on the detection result from the shading detection circuit 120 described later, and the CPU 13
The black shading correction signal BS created by 8 and the black balance correction signal BB are mixed to perform the black correction. The black-corrected video signal is output to the amplifier 106R,
It is supplied to 106G and 106B. Amplifier 106R, 1
06G and 106B adjust the sensitivity of the video signal.

The video signal whose sensitivity has been adjusted is supplied to trap filters 107R, 107G and 107B. Trap filter 107R, 107G, 107B
Removes the unique clock component superimposed on the video signal. The video signal from which the clock component has been removed is supplied to the gain amplifiers 108R, 108G and 108B. The gain amplifiers 108R, 108G, 108B amplify the video signal to a desired gain. Here, the black correction signal adding circuit 10
Black shading correction signal BS and black balance correction signal BB to 5R, 105G and 105B, gain amplifier 1
Gain control signal GC to 08R, 108G, 108B
Is supplied to each circuit after the black correction and gain control signal BGC supplied from the CPU 138 is converted into a digital signal by the D / A converter 115.

The video signal amplified to the desired gain is supplied to the gain control amplifiers 109R, 109G and 109B. Gain control amplifier 109R, 10
9G and 109B are shading detection circuits 1 described later.
Based on the detection result from 20, the white shading correction signal WS created by the CPU 138 and the white balance correction signal WB are mixed to perform white correction. The video signal subjected to the white correction is added to the flare correction signal adding circuit 110.
It is supplied to R, 110G, and 110B. The flare correction signal adding circuits 110R, 110G, and 110B perform flare correction by adding the flare correction signal FL. The video signal after the flare correction is processed by the level compression circuit 111.
It is supplied to R, 111G, and 111B. The level compression circuits 111R, 111G, and 111B compress the high brightness level signal portion. The video signal obtained by compressing the high brightness level signal portion is supplied to the LPFs 112R, 112G and 112B. The LPFs 112R, 112G and 112B remove unnecessary high frequency components. The video signal from which the high frequency components are removed is A / D converter 113R, 113G, 1
13B is supplied. A / D converters 113R and 113
G and 113B convert this video signal into a digital video signal V
Convert to R, VG, VB.

Gain control amplifiers 109R, 109
9G, 109B, flare correction signal adding circuit 110R, 1
10G, 110B and level compression circuits 111R, 11
White shading correction signal WS, white balance correction signal WB, flare correction signal FL added to 1G and 111B,
The pleni control signal PC outputs the white correction, the flare correction and the pleni control signal WFC supplied from the CPU 138.
After being converted into an analog signal by the / A converter 116, it is supplied to each circuit.

Next, the contour correction unit of this camera system will be described with reference to FIG. The contour correction unit has a shading detection section and a contour correction section. The shading detection unit has a shading detection circuit 120. The contour correction unit includes a delay circuit 117R,
117G and 117B and delay circuits 118R and 118G,
It has 118B and a contour correction signal generation circuit 119.
Here, the shading detection circuit 120 is a single LSI.
It is composed of 122. In addition, the delay circuits 117R and 117R
G, 117B and delay circuits 118R, 118G, 118
B and the contour correction signal generation circuit 119 are a single LSI 1
21.

The operation of the contour correction unit of the camera system thus configured will be described below. The digital video signals VR, VG and VB are output to the shading detection circuit 1
20, the delay circuits 117R, 117G, 117B, and the contour correction signal generation circuit 119. The shading detection circuit 120 includes digital video signals VR, VG, VB.
The shading data SD of the
D is supplied to the CPU 138. Delay circuit 117R, 11
7G and 117B are digital video signals VR, VG and V
B is delayed by one horizontal synchronizing signal period (1H) to produce 1H delayed digital video signals DVR, DVG, DVB.
The 1H delayed digital video signals DVR, DVG, DVB are supplied to the delay circuits 118R, 118G, 118B and the contour correction signal generation circuit 119.

Delay circuits 118R, 118G, 118B
Is a 2H delayed digital video signal obtained by further delaying the delayed digital video signals DVR, DVG, DVB by one horizontal synchronization signal period (1H) and by two horizontal synchronization signal periods (2H). The 2H delayed digital video signal delayed by two horizontal synchronizing signal periods (2H) is supplied to the contour correction signal generation circuit 119. Contour correction signal generation circuit 11
9 is a contour correction control signal D supplied from the CPU 138.
Based on T, digital video signals VR, VG, VB,
Various contour correction signals DT are generated from 1H delay digital video signals DVR, DVG, DVB delayed by one horizontal synchronization signal period (1H) and 2H delay digital video signals delayed by two horizontal synchronization signal periods (2H).

Next, the process amplification unit of the camera system will be described with reference to FIG. The process amplification unit has a matrix control unit, a pedestal control unit, a gamma knee control unit, a contour correction control unit, a black and white level control unit, an output rate conversion unit, and an encoder unit. The matrix control unit has an LPF 123 and a linear matrix circuit 124. The pedestal control unit includes pedestal addition circuits 125R, 125G, and 125.
B. The gamma knee control unit includes the black gamma correction circuits 126R, 126G, 126B and the knee correction circuit 1
27R, 127G, 127B and gamma correction circuit 128
R, 128G, 128B. The contour correction control unit includes contour correction signal adding circuits 129R, 129G, and 129.
B. The black and white level control unit is the black and white level control circuit 1.
30R, 130G, 130B and LPF 131R, 13
1G and 131B. The output rate conversion unit includes output rate conversion circuits 132R, 132G, 132B. The encoder unit has an encoder circuit 133 and a D / A conversion circuit 134.

Here, a matrix control section, a pedestal control section, a gamma knee control section, a contour correction control section,
The black and white level control unit is composed of a single LSI 135. The output rate conversion unit is composed of a single LSI 136. The encoder section is composed of a single LSI 137.

The operation of the process amplification unit of the camera system configured as above will be described below. Digital video signal D delayed by one horizontal synchronizing signal period (1H)
VR, DVG, and DVB are supplied to the LPF 123. L
The PF 123 removes unnecessary high frequency components. Digital video signals DVR and DV from which high frequency components have been removed
G and DVB are supplied to the linear matrix circuit 124. The linear matrix circuit 124 has a CPU 138.
Based on the matrix control signal MC supplied from
Adjusts the color reproducibility of digital video signals. The digital video signal whose color reproducibility has been adjusted is supplied to the pedestal adding circuits 125R, 125G and 125B. The pedestal addition circuits 125R, 125G, 125B add a pedestal control signal supplied from the CPU to the digital video signal.

The digital video signal to which the pedestal is added is the black gamma correction circuit 126R, 126G, 1
26B. Black gamma correction circuit 126
The Rs 126G, 126B adjust the gain near the black level based on the black gamma control signal supplied from the CPU 138. The black gamma-corrected digital video signal is supplied to the knee correction circuits 127R, 127G, 12
7B. Knee correction circuits 127R, 127G,
The 127B compresses the high brightness level portion based on the knee control signal supplied from the CPU. The knee-corrected digital video signal is transferred to the gamma correction circuit 128R, 1
It is supplied to 28G and 128B. Gamma correction circuit 128
The R, 128G, and 128B perform gamma correction based on the gamma control signal supplied from the CPU 138.

The gamma-corrected digital video signal is
It is supplied to the contour correction signal adding circuits 129R, 129G, 129B. Contour correction signal adding circuit 129R, 129
G and 129B add a contour correction signal to the digital video signal. The contour-corrected digital video signal is supplied to the black and white level control circuits 130R, 130G, and 130B. Monochrome level control circuits 130R, 130G, 130
B limits the peak level of the white level portion and the black level portion to a prescribed level based on the black and white clip control signal supplied from the CPU 138. The digital video signal whose black and white level is limited is the LPF131R, 131
G, 131B. LPF131R, 131
G and 131B remove unnecessary high frequency components.

The digital video signal from which the high frequency components have been removed outputs the output rate conversion circuits 132R, 132G, 1
32B. Output rate conversion circuit 132R, 1
The 32G and 132B convert the digital video signal into a desired output signal rate. The digital video signal whose output rate has been converted is supplied to the encoder circuit 133.
The encoder circuit 133 sends the digital video signal to the NTS.
It is converted into a signal of C system or PAL system. The converted digital video signal is supplied to the D / A conversion circuit 134. The D / A conversion circuit 134 converts the digital video signal into the analog video signal Vo. Analog video signal Vo
Is supplied to a VTR and monitor in the latter stage not shown,
Recorded or displayed.

Next, the control unit of the camera system will be described with reference to FIG. The control unit has a CPU 138 containing a system operation program. The CPU 138 supplies the CC correction control signal CFC, the ND filter control signal NFC, the shutter control signal STC, the black correction and gain control signal BGC, which are supplied to the color correction and shading correction unit 139.
A color correction and shading correction control unit that generates a white correction, a flare correction, and a prinny control signal WFC;
Contour correction control signal D supplied to the contour correction unit 140
The contour control controller for generating C, and the matrix control signal MC, the pedestal control signal PC, the black gamma control signal BC, the knee control signal NC, the gamma control signal GC, and the black and white clip control signal CC supplied to the process amplification unit 141. Accepts the process amplification control unit to generate and the external input RI by remote control from the outside,
And an external interface unit for outputting the display output DO to the outside. The control unit configured in this way operates as follows. The CPU 138 controls the color correction and shading correction unit 139, the contour correction unit 140, and the process amplification unit 141 based on the operation program of the system. Also, CPU
Reference numeral 138 controls the system based on an external input RI from an external remote control, and a display output DO.
Is output to the outside.

Next, the delay circuits 117R, 117G and 117B of the contour correction unit of the contour correction unit of the camera system shown in FIG. 6 as described above with reference to FIG. 1 and the delay circuits 118R, 118G and 118B and the contours. An example in which the operation test apparatus for the signal processing circuit of this embodiment is applied to the LSI 121 that constitutes the correction signal generation circuit 119 will be described. The operation test device for a signal processing circuit according to this embodiment includes an LSI package 1, a CPU 138, and a memory 10. LS
The I package 1 includes a circuit under test 2, a setting data interface circuit 4, a test timing control circuit 5, a test pattern generation circuit 7, switching circuits 8R, 8G, 8B, and a test result detection circuit 9. The circuit under test 2 has an operation set point 3.
The test timing control circuit 5 has an operation set point 6. Here, the circuit under test 2 is a signal processing circuit, the test pattern generation circuit 7 is a test pattern generation means, the test timing control circuit 5 is a test timing control means, the test result detection circuit 9 is a test result detection means, and the CPU 138 is a control means. Memory 10
Is a storage means, an input unit (not shown) is an input means, and the switching circuits 8R, 8G, and 8B are switching means. The circuit under test 2 is a delay circuit 117R, 117G, 117 of the contour correction unit of the contour correction unit of the camera system.
B, the delay circuits 118R, 118G and 118B, and the contour correction signal generation circuit 119, which corresponds to the signal processing circuit of the LSI 121. The CPU 138 is the CPU shown in FIG.
It is the same as 138.

First, the schematic structure of the operation test apparatus for the signal processing circuit will be described. The test pattern generation circuit 7 is a circuit for generating test patterns TPR, TPG, TPB for testing the internal operation of the circuit under test 2. The test result detection circuit 9 uses test patterns TPR, TPG,
It is a circuit for detecting a test result pattern DP obtained by testing the internal operation of the circuit under test 2 with TPB. The test timing control circuit 5 is a circuit that controls the operation timing of the test pattern generation circuit 7 and the test result detection circuit 9 based on the synchronization signals VD and HD supplied to the circuit under test 2. The CPU 138 sets the test mode according to an arbitrary operation setting condition of the circuit under test 2, and compares the expected value EP of the operation result of the circuit under test 2 with the operation setting condition with the test result DP of the test result detecting circuit 7. Is a control unit for testing the operation of the circuit under test 2. The CPU 138 has expected value setting means, operation setting / test mode setting means, and comparing means.

Next, a detailed configuration of the operation test device for the signal processing circuit will be described. The setting data interface circuit 4 interprets the control signal CS supplied from the CPU 138 based on a predetermined interface standard,
The setting data FD is set to the operation setting point 3 of the circuit under test 2 and the operation setting point 6 of the test timing control circuit 5. In the normal operation, the setting data interface circuit 4 sets the operating condition data for the circuit under test 2 based on the control signal CS supplied from the CPU 138.
A test operation prohibiting instruction is supplied to the test timing control circuit 5. The test timing control circuit 5 stops the generation of the timing signal TS for the test operation, stops the operations of the test pattern generation circuit 7 and the test result detection circuit 9, and stops the digital video signal V.
The switching circuits 8R, 8G, and 8B are switched by the switching signal ES so that R, VG, and VB are supplied to the circuit under test 2.

During the test operation, the setting data interface circuit 4 sets the operating condition setting data FD to the operation setting point 3 of the circuit under test 2 based on the control signal CS supplied from the CPU 138. This operating condition is not a specific operating condition, and can be arbitrarily set at the time of test execution, for example, by an operating program or an external input RI of an external input means. The test may be automatically performed under the operating condition immediately before the test is executed. Further, the setting data interface circuit 4 sets the operating condition setting data FD to the operation setting point 6 of the test timing control circuit 5 based on the control signal CS supplied from the CPU 138.

The test timing control circuit 5 is
The vertical synchronizing signal VD and the synchronizing signals VD and HD such as the horizontal synchronizing signal HD are used to generate the timing signal TS for the test operation, and the test pattern generating circuit 7
And the test result detection circuit 9 is supplied with the tamming signal TS to start the operation, and the digital video signals VR and V are supplied.
The switching circuits 8R and 8R, so that the test patterns TPR, TPG, and TPB are supplied from G and VB to the circuit under test 2.
Switch between 8G and 8B. In this way, the circuit under test 2
The switching of the signal supplied to the digital video signal V
R, VG, VB and test patterns TPR, TPG, TP
Only the B switching is performed, and the vertical synchronizing signal VD and the synchronizing signals VD and HD such as the horizontal synchronizing signal HD are used as they are without switching to the test signal. The reason for this is that, in the video signal processing system, the vertical synchronizing signal VD and the synchronizing signals VD and HD such as the horizontal synchronizing signal HD are used as reference signals. When supplied to the test circuit 2, normal operation of the circuit under test 2 cannot be guaranteed, and there is a risk that the failure detection rate will decrease. To generate the test signal of the synchronization signal system in conformity with the standard. This is because each LSI must have its own synchronization signal generation circuit, which increases the number of circuits for testing.

The test execution time according to the timing signal TS from the test timing control circuit 5 depends on each LS.
The longest operating cycle of I is used as a reference. The reason for this is that each L
This is because the circuits of more components are operated so that the SI is performed in a state suitable for the test operation. For example, a vertical sync signal VD or a field sync signal,
The cycle of the frame synchronization signal etc. is used as the reference test cycle. Therefore, the test timing control circuit 5
Each LSI has a different circuit configuration.

According to the timing signal TS from the test timing control circuit 5, the test pattern generation circuit 7 tests the M-sequence pseudo-random signal according to the number of bits of each digital video signal VR, VG, VB. The patterns TPR, TPG, TPB are generated. At this time, the test pattern generation circuit 7 configures a different M-sequence pseudo random signal generation circuit for each digital video signal VR, VG, VB, or changes the initial setting value of the M-sequence pseudo random signal generation circuit. ,
Different test patterns TPR, TPG, TPB may be generated for each digital video signal VR, VG, VB.

As a configuration example of such a test pattern generation circuit, FIG. 3 shows a 10-bit M-sequence pseudo random signal generation circuit. In FIG. 3, the 10-bit M-sequence pseudo-random signal generating circuit includes ten flip-flops 11, 12, 13, 14, 15, 16, 17, 18, 1.
It has 9 and 20, and an exclusive OR adder 21. 10
Number of flip-flops 11, 12, 13, 14, 15,
The output terminals Q of the flip-flops in the preceding stages of 16, 17, 18, 19, and 20 are sequentially connected to the input terminal D of the flip-flops of the next stage to form a shift register of 10 stages. The output terminal Q of the seventh-stage flip-flop 17 is connected to one input terminal of the exclusive OR adder 21,
The output terminal Q of the 0th stage flip-flop 20 is connected to the other input terminal of the exclusive OR adder 21, and the output terminal of the exclusive OR adder 21 is the input terminal D of the first stage flip-flop 11. Connected to. In addition, ten flip-flops 11, 12, 13, 14, 15, 16, 17,
The clock signal CLK is supplied to the clock input terminals of 18, 19, and 20. The clock signal CLK is the timing signal TS supplied from the test timing control circuit 5.

The 10-bit M-sequence pseudo-random signal generating circuit configured as described above operates as follows. The number of states of the 10-stage shift register is 2 ¹⁰ , but first the flip-flops 11, 12, 13, 1
If the initial values of 4, 15, 16, 17, 18, 19, and 20 are all "0", no change occurs. Some flip-flop 11, 12, 13, 14, 15, 16, 17,
1 If any time "1" is in the 18, 19 and 20, changed every time the clock signal CLK is supplied, (2 ¹⁰ -
Cycle through the different states of 1). As a result, the test pattern TP which is the output signal of this circuit is (2 ¹⁰ −1) = 1
The 023 bit pseudo random signal is repeated. That is, first, the position of the flip-flop containing "1" as the initial value is changed so as to change the initial setting value of the M-sequence pseudo-random signal generating circuit, and each digital video signal VR, VG, VB is changed. Different test patterns TPR, TPG, TPB can be generated.

Returning to FIG. 1, in the circuit under test 2, since the synchronizing signals VD and HD used in the normal operation are used as they are, the test pattern TPR,
The TPG and TPB are regarded as original digital video signals and the same operation as the normal operation is performed. As a result, the digital video signals VR, VG and VB and the contour correction signal DT according to the test patterns TPR, TPG and TBP are output. Therefore, the operating circuit of the circuit under test 2 changes depending on the operation setting of the circuit under test 2 at this time, and
The states of the output digital video signals VR, VG, VB and the contour correction signal DT also change.

The test result detection circuit 9 includes the circuit under test 2
Input the digital video signals VR, VG, VB and the contour correction signal DT output from the test pattern TP.
The operation status of the circuit under test 2 based on R, TPG, TPB is detected according to the timing signal TS from the test timing control circuit 5. The detection of the test result DP is
Instead of a static test result such as one-time data acquisition at a certain timing, each digital video signal VR,
A dynamic test result is obtained by taking in an output signal for a certain fixed period for each of VG, VB and the contour correction signal DT and integrating the data. The "certain fixed period" used here is a period suitable for each LSI, as described in the description of the test timing control circuit 5. For example, in the case of this LSI, one cycle of the vertical synchronizing signal VD is used as the integration period of the test result.

Further, the test result detection circuit 9 determines the test result DP for each output video signal VR, VG, VB, DT as a standard for determining which circuit in the circuit under test 2 is broken. I am trying to output. In this example, the test results DP are separately obtained for the four signals of the digital video signals VR, VG, VB and the contour correction signal DT.
Is being detected.

As a configuration example of such a test result detecting circuit 9, a 10-bit test result detecting circuit is shown in FIG. In FIG. 4, the 10-bit test result detection circuit includes 10 flip-flops 22, 23, 24, 2
5,26,27,28,29,30,31 and 10 adders 32,33,34,35,36,37,38,3
9, 40, 41. 10 flip-flops 22, 23, 24, 25, 26, 27, 28, 29, 3
0, 31 and 10 adders 32, 33, 34, 35, 3
6, 37, 38, 39, 40, 41, the output terminal Q of the flip-flop of the previous stage is connected to one input terminal of the adder of the next stage, and the output terminal of the adder of the next stage is the flip-flop of the next stage. Are sequentially connected to the input terminals D of the amplifiers.

Then, the tenth flip-flop 31
Is connected to one input terminal of the first-stage adder 32, the output terminal of the first-stage adder 32 is connected to the input terminal D of the first-stage flip-flop 22, and 10-bit parallel digital data PD is input to the other input terminal of the adder. 10 adders 32, 3
3,34,35,36,37,38,39,40,41
Of 10-bit parallel digital data PD input to the other input terminal of each of the digital video signals VR, VG, VB output from the circuit under test 2 and the contour correction signal DT. It is PD. Also 10 flip-flops 2
2,23,24,25,26,27,28,29,3
The clock signal CLK is supplied to the clock input terminals of 0 and 31. The clock signal CLK is the timing signal TS supplied from the test timing control circuit 5.

The 10-bit test result detecting circuit configured as described above operates as follows. First, 10-bit parallel data PD of the digital video signal VR
Is 10 adders 32, 33, 34, 35, 36, 3
It is supplied to the other input terminal of 7, 38, 39, 40, 41. The 10-bit parallel data PD of the digital video signal VR is added for each clock signal CLK and output as the test result DP. This operation is the same as the checksum operation. In this example, the carry output of the 10-bit addition output is continuously added to the data of the first bit by further feeding back the addition output as the test result DP. Since the carry data of the bit addition data can be taken into consideration, the fault detection rate can be improved. By thus compressing the output pattern and increasing the error oversight rate, it is possible to easily determine whether the error is correct. The other digital video signals VG and VB and the contour correction signal DT operate similarly.

Returning to FIG. 1, the CPU 138 compares the expected value EP previously obtained by the expected value setting means with the test result DP fetched from the test result detecting circuit 9 by the comparing means, and the circuit under test is compared. It is determined whether the internal operation of 2 is correct, the result is output as a display output DO, and the display output DO is output based on an external input RI from a display device such as a viewfinder or a remote controller for external control. Output and display on a display device such as a personal computer. Therefore, the expected value setting means of the CPU 138 obtains the operation setting data of the circuit under test 2 and the expected value EP corresponding thereto in advance, and stores this value in the memory 10. The expected value EP is obtained by a simulation at the time of designing the circuit under test 2 or an actually measured value when the circuit under test 2 is actually tested.

Further, since the operation setting and test mode setting means of the CPU 138 controls the operation setting of the circuit under test 2, a plurality of operation setting conditions for the test operation and the expected value EP for the setting are obtained in advance. The operation program is stored in the memory 10 so that an operation test can be performed under arbitrary operation conditions, and an operation program can be automatically executed a plurality of times while changing the operation setting of the circuit under test 2. It may be configured to be provided.

Next, the operation of the operation testing apparatus for the signal processing circuit of this embodiment will be described with reference to the flow chart shown in FIG. Start and CPU138 in step S1
Is the control signal C for the LSI internal operation test
It is determined whether S is on. The control signal CS is generated by the CPU 138 based on, for example, a switch provided on the substrate of each unit of the camera system or an external input RI of an external remote controller. In addition, the control signal C is directly sent to the CPU 138.
S may be supplied. The CPU 138 holds the ON or OFF state of the control signal CS for the LSI internal test under test in a register. CPU 13
8 confirms the state of this register.

In step S2, the CPU 138 confirms the test mode. This test mode is
Similar to the control signal CS of the internal operation test, the CPU generates it based on, for example, a switch provided on the substrate of each unit of the camera system or an external input RI of an external remote controller. In addition, directly CPU1
The test mode may be supplied to 38 as a signal. The test mode is information on whether the test is performed under one operating condition, is continuously performed under a plurality of operating conditions, or under which operating condition the test is performed. CP
The U 138 holds the operating condition of the test mode in the register, reads the operating program under the specified operating condition from the memory, and prepares to start the operation.

Next, in step S3, the CPU 138 saves the operation setting of the circuit under test 2 before the start of the test. CP
The U 138 fetches the setting data FD of the operation setting held in the internal register or the setting data FD of the operation setting set at the operation setting point 3 in the circuit under test 2 to obtain the current setting before starting the test. The memory 10 is loaded with the setting data FD of the operation setting of the test circuit 2.
To memorize. In step S4, the CPU 138 changes the setting data FD of the operation setting inside the circuit under test 2 for the test to be started. The CPU 138 sets the operation setting data FD held in the internal register to the operation setting point 3 in the circuit under test 2 in advance according to which operation condition the test is performed.

Next, in step S5, the CPU 138 starts an internal operation test of the circuit under test 2. The CPU 138 supplies the control signal CS to the setting data interface circuit 4 provided in the LSI package 1 according to the operation program according to the specified operation condition. The setting data interface circuit 4 interprets the control signal CS based on the standard of a predetermined interface and supplies the setting data FD to the operation setting point 3 of the circuit under test 2 and the operation setting point 6 of the test timing control circuit 5. Supply to. Circuit under test 2
Sets the setting data FD to the internal operation setting point 3. The test timing control circuit 5 sets the setting data FD at the internal operation setting point 6 and also generates the timing signal TS and the switching signal ES based on the synchronization signals VD, HD and the setting data FD supplied from the camera system. The timing signal TS is supplied to the test pattern generation circuit 7 and the test result detection circuit 9. The switching signal ES is the switching circuits 8R, 8
It is supplied to G and 8B.

The test pattern generation circuit 7 uses the timing signal TS to generate test patterns TPR, TPG, T.
Generate PB. Test patterns TPR, TPG, TP
B is the M-sequence pseudo-random signal shown in FIG. The switching circuits 8R, 8G and 8B are provided with the digital video signal V
Test patterns TPR, TP in place of R, VG, VB
The contacts are switched based on the switching signal ES so that G and TPB are supplied to the circuit under test 2. Circuit under test 2
Performs the same contour correction signal generation operation as the normal operation by regarding the test patterns TPR, TPG, TPB as digital video signals based on the same synchronization signals VD, HD as the normal operation. However, at this time, the operating circuit of the circuit under test 2 changes depending on the operation setting for the circuit under test 2,
The states of the output digital video signals VR, VG, VB and the contour correction signal DT also change. The digital video signals VR, VG, VB and the contour correction signal DT are supplied to the test result detection circuit 9.

The test result detecting circuit 9 detects the operating condition of the circuit under test 2 based on the test patterns TPR, TPG, TPB according to the timing signal TS. The test result detection circuit 9 is, for example, the 10-bit test result detection circuit shown in FIG. In this case, the carry signal of the most significant bit is added to the lower bit again instead of the simple integrator circuit, so that the carry signal can be considered in the test result. This test result detection period is one cycle period of the vertical synchronizing signal VD. CP in step S6
U138 waits until the test result detection period ends. This is because a certain amount of time is required from the start to the end of the test, so that a waiting time is ensured so that the test result can be retrieved reliably. In step S7, the CPU 138 fetches the test result DP from the test result detection circuit 9 and holds it in the internal register. Since the test result is integrated for each output video signal VR, VG, VB and DT, all output video signals VR, VG, VB and D
The test result DP for each T is taken out.

In step S8, the CPU 138 compares the expected value EP obtained in advance with the test result DP fetched from the test result detection circuit 9 to determine whether the internal operation of the circuit under test 2 is correct. To do. Since the expected value EP is uniquely determined by the operating condition at the start of the test, the expected value EP and the output video signals VR, VG, VB and D are set.
The test result DP for each T is compared with each other. In step S9, the CPU 138 displays the result on a display device such as a viewfinder, a remote controller for external control, or a display device such as a personal computer. As a display method, a display for each LSI package 1 such as "** OK" or "** NG" and, in addition to this, "VB NG" or "DT N" only in the case of NG
The output video signal of NG, such as “G”, may be displayed together.

In step S10, the CPU 138 determines whether or not all modes have ended. Since the CPU 138 controls the operation setting of the circuit under test 2, the setting data FD of a plurality of operation setting conditions for the test operation and the expected value EP for the setting are obtained in advance and stored in the memory 10. An operation test can be performed under arbitrary operation conditions, and an operation program of a plurality of modes is provided so as to automatically perform an operation test a plurality of times while changing the setting data FD of the operation setting of the circuit under test 2. are doing. Therefore, a plurality of test modes may be set by changing the operating condition setting data FD. In step S10, the CPU 138
However, if it is determined that all the modes have not ended, the CPU 138 sets the internal operation setting of the circuit under test 2 to the next test mode in step S11, and repeats the processing and determination of steps S5 to S10.

When the CPU 138 determines in step S10 that all the modes have ended, step S12
Then, the CPU 138 sets the internal operation test mode of the circuit under test 2 to OFF and holds it in the internal register. Finally,
In step S13, the CPU 138 returns all the setting data FD of the internal operation setting of the circuit under test 2 to the original setting. CP
The U 138 reads out the original setting data FD of the operation setting of the circuit under test 2 stored in the memory 10 before starting the test and holds the setting data FD of the operation setting in the internal register, or the circuit under test 2 The operation setting point FD is set to the internal operation setting point 3, and the processing is ended.

If the test is performed under only one operating condition, steps S10 to S12 and step S13 are performed.
Then, the test mode of the internal operation of the LSI under test is turned off, the operation of the test timing control circuit 5 is stopped, and the set data F for the internal operation of the circuit under test 2 is set.
Return D to end. This is because by returning the setting data FD stored in the memory 10 to the circuit under test 2 as it is before the start of this test, the circuit under test 2, the LSI package 1 mounting board and the camera system are tested before the test. This is to return to the state. Therefore, if the operation setting of the circuit under test 2 is set to the default state in advance, the operation setting of the circuit under test 2 can always be returned to the default state after the test is completed. This completes a series of internal operation test processing of the circuit under test 2.

In the above example, the expected value E is obtained in step S8.
Although an example in which the comparison result is displayed in step S9 after P and the test result DP are compared has been shown, the comparison result may be displayed after all the test modes are finished in step S10. Further, in the above example, the processing for the internal operation test of one LSI package 1 has been described, but the same internal operation test processing is performed for each LSI package 1 for a plurality of LSI packages 1 having the same function. Multiple LSI packages 1
The internal operation test regarding may be automatically performed.

According to the above example, the internal operation test of the circuit under test 2 can be performed by changing the various operating conditions by using the synchronizing signals VD and HD of the actual operation cycle. Therefore, the detailed circuit under test can be tested. The internal operation test 2 can be automatically performed, and the internal operation test of the LSI package 1 mounted on the substrate can be easily performed without adding a special device to the outside.

Further, in the above example, the delay circuits 117R and 117R of the contour correction section of the contour correction unit of the camera system are used.
G, 117B, delay circuits 118R, 118G, 118B
And the LSI 121 configuring the contour correction signal generation circuit 119
Although the example in which the operation test device for the signal processing circuit of the present embodiment is applied is described above, the LSI 122 configuring the shading detection circuit 120 of another contour correction unit, the matrix control unit, the pedestal control unit, and the gamma knee control of the process amplification unit. Section, contour correction control section, and black and white level control section LSI135, and output rate conversion section L
The operation testing apparatus for the signal processing circuit of this embodiment may be applied to the SI 136 and the LSI 137 that constitutes the encoder unit.

The operation test apparatus for the signal processing circuit of the above example includes the test pattern generation circuit 7 for generating the test patterns TPR, TPG, TBP for testing the internal operation of the circuit under test 2, and the test patterns TPR, TPG, TPB
The test result detection circuit 9 for detecting the test result DP that has tested the internal operation of the circuit under test 2 by the test pattern generation circuit 7 and the test result detection circuit 9 based on the synchronization signals VD, HD supplied to the circuit under test 2. The test timing control circuit 5 for controlling the operation timing of the circuit 9 is provided, and the CPU 138 sets the test mode for the circuit under test 2 under an arbitrary operation setting condition, and the operation result of the circuit under test 2 for the operation setting condition. Expected value EP and test result DP of the test result detection circuit 9
Since the operation of the circuit under test 2 is tested by comparing with, the internal operation test of the circuit under test 2 is performed by changing various operating conditions by using the synchronizing signals VD and HD of the actual operating cycle. Therefore, detailed circuit under test 2
The internal operation test can be automatically performed, and the internal operation test of the LSI package 1 mounted on the substrate can be easily performed without adding a special device to the outside.

In the above, the operation testing apparatus for the signal processing circuit of the invention of the above example stores the setting data FD of the previously set operation setting conditions before testing the operation of the circuit under test 2. However, since the setting data FD of the previous operation setting conditions is restored after the test is completed, the circuit under test 2, the substrate on which the LSI package 1 is mounted, and the L
The camera system having the SI package 1 can be returned to the state before the test. Therefore, the circuit under test 2 is
However, if the operation setting of the default state is set, the operation setting of the circuit under test 2 can always be returned to the default state after the test is completed.

Further, in the above-described operation test apparatus for the signal processing circuit of the invention, the period for testing the operation of the circuit under test 2 is set to be the longest operating cycle of the circuit under test 2 in the above description. Since the test operation is performed in a state suitable for the test circuit 2, it is possible to operate the circuits of more constituent elements of the circuit under test 2, thereby improving the failure detection rate.

Further, the operation testing apparatus for the signal processing circuit according to the invention of the above-described example continuously operates the circuit under test for a plurality of test modes according to the setting data FD of a plurality of operation setting conditions for the circuit under test 2. Since the test is performed in this way, the test can be performed in a plurality of test modes so that the operation test is automatically performed a plurality of times while changing the setting data FD of the operation setting of the circuit under test.

In the above-described operation test apparatus for the signal processing circuit of the invention, the plurality of LSI packages 1 are connected and the operation of each LSI package 1 is continuously tested. The operation of not only the LSI package 1 but also the plurality of LSI packages 1 actually mounted on the substrate can be tested under conditions suitable for the actual operation.

[0073]

According to the operation test apparatus for a signal processing circuit of the present invention, a test pattern generating means for generating a test pattern for testing the internal operation of the signal processing circuit and an internal operation of the signal processing circuit are tested by the test pattern. And a test timing control means for controlling the operation timing of the test pattern generation means and the test result detection means based on the synchronization signal supplied to the signal processing circuit. A test mode is set according to an arbitrary operation setting condition, and the operation of the signal processing circuit is tested by comparing the expected value of the operation result of the signal processing circuit with the operation setting condition and the test result of the test result detecting means. Since this is done, the synchronization signal of the actual operation cycle is used to change the signal under various operating conditions. Since it is possible to perform an internal operation test of the logic circuit, a detailed internal operation test of the signal processing circuit can be automatically performed, and a special device can be used as an external operation test of the signal processing circuit mounted on the board. The effect is that it can be easily performed without adding.

Further, in the above, the operation testing apparatus for the signal processing circuit according to the present invention stores the previously set operation setting conditions before the operation of the signal processing circuit is tested, and the previous operation setting condition is set after the test is completed. Since the operation setting conditions are restored, the system having the signal processing circuit, the board on which the signal processing circuit is mounted, and the signal processing circuit can be returned to the state before the test. Therefore, if the operation setting of the signal processing circuit is set to the default state in advance, the operation setting of the signal processing circuit can always be returned to the default state after the test is completed.

Further, the operation test apparatus for a signal processing circuit according to the present invention is suitable for a signal processing circuit because the period for testing the operation of the signal processing circuit is set to the longest operation cycle of the signal processing circuit in the above description. Since the test operation is performed in this state, it is possible to operate the circuits of more component elements of the signal processing circuit, which has the effect of improving the failure detection rate.

Further, the operation testing apparatus for a signal processing circuit according to the present invention is configured to continuously test the operation of the signal processing circuit in a plurality of test modes according to a plurality of operation setting conditions for the signal processing circuit. Therefore, there is an effect that a test can be performed in a plurality of test modes so that an operation test is automatically performed a plurality of times while changing the operation setting of the signal processing circuit.

Further, in the above-described operation test apparatus for the signal processing circuit of the present invention, since a plurality of signal processing circuits are connected and the operation of each signal processing circuit is continuously tested in the above description, a single signal It is possible to test the operation of not only the processing circuit but also a plurality of signal processing circuits actually mounted on the substrate under conditions suitable for the actual operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an operation test apparatus for a signal processing circuit according to the present invention.

FIG. 2 is a flow chart showing the operation of an embodiment of the operation testing apparatus for the signal processing circuit of the present invention.

FIG. 3 is a circuit diagram of a 10-bit M-sequence pseudo-random signal generation circuit as a test pattern generation circuit of an embodiment of an operation test apparatus for a signal processing circuit according to the present invention.

FIG. 4 is a circuit diagram showing a 10-bit test result detection circuit of an embodiment of an operation test device for a signal processing circuit according to the present invention.

FIG. 5 is a configuration diagram of a color correction and shading correction unit of a camera system using an embodiment of an operation test apparatus for a signal processing circuit according to the present invention.

FIG. 6 is a configuration diagram of a contour correction unit of a camera system using an embodiment of an operation test apparatus for a signal processing circuit according to the present invention.

FIG. 7 is a configuration diagram of a process amplification unit of a camera system using an embodiment of an operation test apparatus for a signal processing circuit according to the present invention.

FIG. 8 is a configuration diagram of a control unit of a camera system using an embodiment of an operation test device for a signal processing circuit according to the present invention.

[Explanation of symbols]

1 LSI package, 2 circuit under test, 3 operation setting points, 4 setting data interface circuit, 5
Test timing control circuit, 6 operation setting points, 7 test pattern generation circuit, 8R, 8G, 9
B switching circuit, 9 test result detection circuit, 10 memory, EP expected value, FD setting data, CS control signal, TPR, TPG, TPB test pattern, TS timing signal, DP test result

Claims (5)

[Claims] 1. A test pattern generating means for generating a test pattern for testing the internal operation of the signal processing circuit, and a test result detecting means for detecting a result of testing the internal operation of the signal processing circuit by the test pattern. A test timing control means for controlling operation timings of the test pattern generation means and the test result detection means based on a synchronization signal supplied to the signal processing circuit, and any operation for the signal processing circuit. The test mode is set according to the setting condition, and the operation value of the signal processing circuit is tested by comparing the expected value of the operation result of the signal processing circuit with the operation setting condition and the test result of the test result detecting means. An operation test device for a signal processing circuit, characterized in that 2. The operation test apparatus for a signal processing circuit according to claim 1, wherein before the operation of the signal processing circuit is tested, previously set operation setting conditions are stored, and after the test, the operation setting condition is set. An operation test device for a signal processing circuit, which is characterized by returning to the previous operation setting condition. 3. The signal processing circuit operation test apparatus according to claim 1, wherein the period during which the operation of the signal processing circuit is tested is set to the longest operation cycle of the signal processing circuit. Processing circuit operation test equipment. 4. The operation test device for a signal processing circuit according to claim 1, wherein the operation of the signal processing circuit is continuously tested for a plurality of test modes under a plurality of operation setting conditions for the signal processing circuit. An operation test device for a signal processing circuit, characterized in that 5. A signal processing circuit operation test apparatus according to claim 1, wherein a plurality of said signal processing circuits are connected and the operation of each signal processing circuit is continuously tested. Processing circuit operation test equipment.