JP2001083212A - Method for inspecting signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for inspecting having no quantizing error at a low cost in a short time. SOLUTION: A signal of a circuit 2 to be inspected is decided to be good or not by preparing a normal circuit 1 for generating a normal signal for comparing with a signal to be inspected, providing a potential difference between a ground of the circuit 2 and a ground of the circuit 1, and comparing an output signal of the circuit 2 with an output signal of the circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal inspection method, and more particularly to a signal inspection method for inspecting an output of an IC device or the like for a liquid crystal display device.

[0002]

2. Description of the Related Art A conventional signal inspection method will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing an example of the prior art. (For example, Japanese Patent Application Laid-Open No. 61-05921 by the present applicant)
No. 1).

[0006] In accordance with the storage program, the controller 211 controls the device under test 12 via the device under test controller 114.
A state of 0 is set. Next, the comparison signal generator 112 is controlled by the control unit 211, and the value of the comparison signal 103 is determined. In the comparator 113, the device under test 1 at that time is
The value of the detected output signal 102 matched by the detector 117 is compared with the value of the comparison signal 103 and converted to a logic level corresponding to the measurement signal at each of the 20 measurement points, and the comparison output signal 104 is generated. . This comparison output signal 104
The control unit 211 calculates a measured value for each comparison output 103 by the storage program based on the stored program, and a value set in the storage program in advance or a value set in the operation unit 115 corresponding to the measurement signal 101. Are compared with each other, and a determination of good or bad is made, and all measured values and determination results are displayed on the display unit 116 at the same time.

In such a method of inspecting an analog output signal waveform of an electronic circuit, a signal under test is A / D converted and taken into a control device, or allowable upper / lower limit data stored in the control device is converted into a D / A signal. The converted output was compared with the signal to be inspected by a comparator. Therefore, an expensive device for A / D conversion of a signal or D / A conversion and output of upper and lower limit data is required. Further, it is necessary to store upper and lower limit data in the control device in advance, and it is necessary to input a huge amount of data for each signal to be inspected. Furthermore, since sampling processing such as A / D conversion and D / A conversion is involved, quantization and sampling errors are affected.

[0006]

The above-mentioned conventional signal inspection method has the following problems.

The first problem is that a comparison signal generator, a device for taking in the output of the comparator, and a control unit for controlling these components are required, resulting in an increase in cost.

A second problem is that it is necessary to change the control data of the comparison signal generator and the good / bad judgment program of the measurement result every time the content of the object to be inspected (test pattern, circuit change, etc.) changes. That is.

A third problem is that, after the data is once taken into the control unit, good / bad judgments are made by a program, so that it takes more time to judge than in hardware processing.

The fourth problem is that the signal to be inspected is compared with the D / A conversion output of the allowable upper and lower limits, so that a D / A conversion quantization error is included. That is, waveform comparison cannot be performed.

[0011]

According to a first aspect of the present invention, there is provided a signal inspection method, comprising preparing a normal circuit (1) for generating a normal signal for comparison with a signal to be inspected. A potential difference is provided between the ground and the ground of the normal circuit (1), and the output signal of the circuit under test (2) is compared with the output signal of the normal circuit (1) so that the signal of the circuit under test (2) is good.・ Perform defect judgment.

A signal inspection method according to a second aspect of the present invention is the signal inspection method according to the first aspect, wherein the control section (14) connects the circuit under test (2) and the normal circuit (1) with k control lines, respectively. The power supply voltage (V) is supplied to the circuit under test (2) by the power supply (3).
1), a procedure of supplying a power supply voltage (V1) to the normal circuit (1) by a power supply (4), and a potential difference between a ground of a power supply (3) and a ground of a power supply (4) by a power supply (5). (ΔV).

The signal inspection method according to a third aspect of the present invention is the signal inspection method according to the first aspect, wherein the multi-input simultaneous comparator (6) including the comparators (6-1) to (6-n) is used. And (2) comparing the signals (1) to (n) of the normal circuit (1).

According to a fourth aspect of the present invention, in the third aspect of the present invention, when the signal level of the normal circuit (1) is higher than the signal level of the circuit under test (2) by the comparator (6) (1). ) Is output, and if it is low, (0) is output.

A signal inspection method according to a fifth aspect of the present invention is the signal inspection method according to the third aspect, wherein the signal of the multi-input simultaneous comparator (6) is received by the NAND (7) and the OR (8), and the latch (9) and the latch (10) are received. ) To output the calculation results.

According to a sixth aspect of the present invention, in the signal inspection method according to the third aspect, when the set (S terminal) becomes 1 once, the latch (9) and the latch (10) are reset to 1 (R terminal).
Once becomes 1 and 0 is held, and the result is output to the output terminal (11) and the output terminal (12).

[0017]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The control unit 14 is connected to the circuit under test 2 and the normal circuit 1 by k control lines. The power supply 3 supplies a power supply voltage V1 to the circuit under test 2. The power supply 4 supplies the power supply voltage V1 to the normal circuit 1. The power supply 5 generates a potential difference ΔV between the ground of the power supply 3 and the ground of the power supply 4. The multi-input simultaneous comparator 6 includes comparators 6-1 to 6-n, and compares signals 1 to n of the circuit under test 2 and the normal circuit 1. The comparator outputs 1 when the signal level of the normal circuit 1 is higher than the signal level of the circuit under test 2 and outputs 0 when the signal level is lower than the signal level of the circuit under test 2. NAND 7 and OR 8 receive the signal of multi-input simultaneous comparator 6 and output the operation result to latch 9 and latch 10 respectively. The latch 9 and the latch 10 reset 1 (R terminal) once the set (S terminal) becomes 1.
Once becomes 1 and outputs 0 to the output terminals 11 and 12. The input terminal 13 is connected to the latch 9 and the latch 1
0 reset (R terminal).

According to the present invention, a normal circuit for generating a normal signal for comparison with a signal under test is prepared. Here, a potential difference is provided between the ground of the circuit under test and the ground of the normal circuit. Comparing the output signal and the output signal of the normal circuit with a comparator,
Perform a defect determination. Since the signal of the normal circuit is used as a criterion for the determination, the signal is A / D converted, or the upper / lower limit data is D / D converted.
No expensive device for A output is required. Further, there is no need to input a huge amount of upper and lower limit data. Further, since there is no sampling, there is no adverse effect of sampling.

In FIG. 1, the control unit 14 controls the circuit under test 2 and the normal circuit 1 to obtain mutually synchronized test pattern signal outputs. Output voltage ΔV of power supply 5
= Α (> 0), when the operation of the circuit under test 2 is abnormal and the signal m of the circuit under test 2 exceeds the level of the signal m of the normal circuit 1, the output of the comparator 6-m becomes 0, NAND7
Is 1, the latch 9 is set. Therefore, when the output terminal 11 becomes 1, it can be understood that the output signal level of the circuit under test has exceeded the normal circuit by α or more in at least one of the signals 1 to n. Circuit under test 2 when output voltage ΔV = −β (<0) of power supply 5
Is abnormal, and the output signal m of the circuit under test 2 falls below the level of the signal 1 of the normal circuit m, the output of the comparator 6-m becomes 1 and the output of the OR8 becomes 1, so the latch 1
0 is set. Therefore, if the output terminal 12 becomes 1, at least one of the signals 1 to n
It can be seen that the signal level of the circuit under test is lower than the normal circuit by β or more.

Next, the operation will be described with reference to FIGS. First, the output voltage ΔV of the power supply 5 is fixed to a positive constant value α, and the terminal 13 is set to 1 and then returned to 0 to clear the latches 9 and 10. The control unit 14 controls the circuit under test 2 and the normal circuit 1 to obtain test pattern signal outputs synchronized with each other. As can be seen from FIG. 2, when the circuit under test 2 performs exactly the same operation as the normal circuit 1, each signal of the normal circuit 1 has a waveform shifted by a ground potential difference ΔV from each signal of the circuit under test. Since the potential difference ΔV is positive, the outputs of the comparators 6-1 to 6-n become 1, and the output of the NAND 7 becomes 0. If the operation of the circuit under test 2 is abnormal and the signal m of the circuit under test 2 exceeds the level of the signal m of the normal circuit 1, the comparator 6-
Since the output of m becomes 0 and the output of NAND 7 becomes 1, the latch 9 is set. Therefore, output terminal 1
If 1 becomes 1, at least one of the signals 1 to n has a signal level of the circuit to be tested that is higher than that of the normal circuit by α.
It turns out that it exceeded above.

Next, the output voltage ΔV of the power supply 5 is fixed to a negative constant value (−β), the terminal 13 is set to 1 once, and then returned to 0 to clear the latches 9 and 10. The control unit 14
The control is performed so that the test pattern signal output synchronized with each other is obtained from the circuit under test 2 and the normal circuit 1. Referring to FIG. 3, when the circuit under test 2 performs exactly the same operation as the normal circuit 1, each signal of the normal circuit 1 has a waveform shifted by a ground potential difference ΔV from each signal of the circuit under test. Since the potential difference ΔV is negative, the comparator 6-1 to the comparator 6-n
Is 0, and the output of OR8 is 0. If the operation of the circuit under test 2 is abnormal and the signal m of the circuit under test 2 falls below the level of the signal 1 of the normal circuit m, the comparator 6-
Since the output of m becomes 1 and the output of OR8 becomes 1, the latch 10 is set. Therefore, when the output terminal 12 becomes 1, it can be understood that the signal level of the circuit under test is lower than the normal circuit by β or more in at least one of the signals 1 to n.

By performing the above two measurements, it is possible to determine whether or not the potential difference between the signals of the circuit under test 2 and the normal circuit 1 is in the range of -α to + α.

[0024]

The signal inspection method of the present invention has the following effects.

The first effect is that an output signal waveform of an electronic circuit can be inspected with an inexpensive hardware configuration.

The reason for this is that there is no need for a system for A / D-converting a signal to be inspected and storing and comparing the data, which is required in the conventional inspection method, or a system for D / A-converting and outputting an allowable upper / lower limit signal. Is unnecessary.

A second effect is that it is not necessary to input allowable upper / lower limit data which is a criterion of good / bad. Therefore, even if the signal waveform changes due to a change in the test pattern or the circuit content, it is not necessary to change the program or input data, so that an inexpensive and highly reliable inspection can be performed.

The reason is that the allowable upper and lower limits can be specified only by the voltage difference from the signal of the normal circuit in the present method.

The third effect is that a good / bad judgment can be made by hardware so that a quick judgment can be made.

The reason for this is that in the conventional inspection method, the data of the signal to be inspected is fetched once, and then the pass / fail judgment is made by the program.

A fourth effect is that the signal waveform can be continuously compared without being affected by the quantization error because the quantization procedure is unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the present invention.

FIG. 3 is a time chart for explaining the operation of the present invention.

FIG. 4 is a block diagram showing an example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Normal circuit 2 Circuit under test 3 Power supply 4 Power supply 5 Power supply 7 NAND 8 OR 9 Latch 10 Latch

Claims (6)

[Claims] 1. A normal circuit (1) for generating a normal signal for comparison with a signal under test is prepared, and a potential difference between the ground of the circuit under test (2) and the ground of the normal circuit (1) is provided. A signal inspection method for comparing the output signal of the circuit under test (2) with the output signal of the normal circuit (1) to determine whether the signal of the circuit under test (2) is good or bad. 2. A circuit under test (2) by a control unit (14).
And k circuits to connect to the normal circuit (1) and the power supply voltage (V1) to the circuit under test (2) by the power supply (3).
The power supply (4) supplies the power supply voltage (V1) to the normal circuit (1); and the power supply (5) supplies the potential difference (ΔV) between the ground of the power supply (3) and the ground of the power supply (4). ). The method according to claim 1, further comprising: 3. A signal (1) between a circuit under test (2) and a normal circuit (1) using a multi-input simultaneous comparator (6) comprising comparators (6-1) to (6-n). 2. The signal inspection method according to claim 1, further comprising: comparing the signals (n). 4. The comparator (6) outputs (1) when the signal level of the normal circuit (1) is higher than the signal level of the circuit under test (2), and outputs (0) when the signal level is lower than the signal level of the circuit under test (2). 3
The signal inspection method described. 5. The signal according to claim 3, wherein a signal of the multi-input simultaneous comparator (6) is received by the NAND (7) and the OR (8), and an operation result is output to each of the latch (9) and the latch (10). Inspection methods. 6. The latch (9) and the latch (10) hold 1 when the set (S terminal) once becomes 1, and hold 0 when the reset (R terminal) once becomes 1, and output the result to the output terminal ( 11. The signal inspection method according to claim 3, wherein the signal is output to an output terminal.