JPH03187505A - Buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the distortion of an output signal wave caused by the VBE-IE characteristic of a transistor by returning the increased/decreased part of an emitter current to flowing to an emitter follower circuit, which executes the impedance conversion of the output signal wave, to the emitter. CONSTITUTION:The emitter of a transistor Q1 is connected to constant current sources I2 and I3 and the collector of the transistor Q1 is connected to the collector and base side of a transistor Q2 on the reference side of a constant current mirror circuit 1 composed of transistors Q2 and Q3. Then, the collector side of the transistor Q3 on the output side of this constant current mirror circuit 1 is connected to the emitter of the transistor Q1. Namely, the increased/ decreased part of the emitter current to flow to the emitter follower circuit is returned to the emitter. Thus, the distortion of the output signal wave caused by the VBE-IE characteristic of the transistor can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer circuit applicable to converting the output impedance of an output voltage of an amplifier or the like.

[Conventional technology]

FIG. 2 is a circuit diagram of a conventional buffer circuit applied as an output impedance conversion circuit of an amplifier. In the figure, (5) is an input terminal into which a signal wave whose output is to be impedance converted is input, and (3) is an input terminal (5).
The base is connected to, and the emitter is a constant current source (4) I
g and the output terminal (6), and the collector is connected to the power supply Vc.
The other terminal of the constant current source (4) Is is grounded.

Next, the operation will be explained. When a signal wave with a certain DC offset is input from the input terminal (5), the emitter follower circuit composed of the transistor (3)Q and the constant current source (4111) A signal wave whose DC voltage has been dropped by the emitter voltage Vat is output to the output terminal (6).

[Problem to be solved by the invention]

Conventional buffer circuits are configured as described above, so if a load is connected to the output terminal, one of which is grounded to a low impedance source, the emitter of transistor Q will be affected by fluctuations in the output voltage. Because the current fluctuates, the output signal wave depends on the base-emitter voltage VSt - emitter current I2 characteristic of the transistor Q, resulting in a problem that distortion occurs in the output signal wave. Ta.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a buffer circuit in which the output signal wave is not distorted due to the influence of the VsE It characteristic.

[Means to solve the problem]

The buffer circuit according to the present invention is configured to return an increase/decrease in emitter current flowing through an emitter follower circuit that performs impedance conversion of an output signal wave to the emitter.

[Effect]

In this invention, as described above, since the structure is configured such that the increase/decrease in the emitter current flowing through the emitter follower circuit is returned to the emitter, the effect of converting the impedance of the output signal wave by the emitter follower circuit, Distortion of the output signal wave due to the VIIEIE characteristic of the transistor can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram showing a buffer circuit.

In the figure, (3) to (6) are the same as those shown in the conventional example of FIG. 2, and therefore their explanation will be omitted. (1) is a constant current mirror circuit, and (2) is a PNP transistor. The emitter of the transistor (3) Ql is connected to the constant current source (4
) I2,■, is connected to. In addition, the collector of transistor f3) Ql is connected to the collector/base side of transistor (2) Qt on the reference side of the constant current mirror circuit (1) constituted by transistors Q, , Q, and this constant current The collector side of the transistor (2) Qs on the output side of the mirror circuit (1) is connected to the emitter of the transistor (3) Ql. Further, the output terminal (6) is the output of this buffer circuit.

Next, the operation will be explained. The voltage of input terminal (5) is V
Assuming that i, when no current flows from the output terminal (6), the current flowing through the emitter of the transistor (31Q+) is I, and this current determines the base-emitter voltage VB! of the transistor (3) Ql, and the output Terminal (6
) voltage V. is expressed as Vo=V+Vsg. On the other hand, when the current △i increases or decreases from the output terminal (6), this increased or decreased current △i is returned to the emitter of the transistor (3) Q + via the constant current mirror circuit (1), and is returned to the emitter of the transistor (3) Q + ) Current feedback is applied to prevent the current flowing through the emitter of Q + from increasing or decreasing.

Note that in the above embodiment, the transistor (2) is of PNP type,
Although the case where the transistor (3) is of NPN type has been described, it goes without saying that the conductivity type of each transistor may be opposite conductivity type.

〔Effect of the invention〕

As described above, according to the buffer circuit according to the present invention,
Since the structure is configured so that the increase/decrease in the emitter current flowing through the emitter follower circuit that converts the impedance of the output signal wave is returned to the emitter, the VsE lt of the transistor
This has the effect of providing a buffer circuit that reduces distortion of the output signal wave due to the characteristics.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a buffer circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional buffer circuit. In the figure, (1) is a constant current mirror circuit, (2), (3
) is a transistor, (4) is a constant current source, (5) is an input terminal, and (6) is an output terminal. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A first transistor of a first conductivity type, whose base has an input terminal into which an input signal wave is input, and whose emitter is connected to the other terminal of a constant current source whose one end is grounded; 2. A constant current mirror circuit composed of a third transistor, whose reference side transistor is connected to the collector of the first transistor, and whose output side is connected to the emitter of the first transistor. A buffer circuit characterized by: