JPH03185927A - A/d converter - Google Patents

Abstract

PURPOSE:To lower the probability generating an inaccurate A/D conversion value due to sudden noise by applying plural numbers of comparison, storing the result to a register and using a majority decision circuit to evaluate the output of each register. CONSTITUTION:A sample signal is at first made active, the level of an input terminal 1 is led to a capacitor 5, then a reference signal is made active and a comparison level depending on a resistor ladder 2 and a switch set 3 is led to the capacitor 5. Then the result of comparison is given to a register 12 to terminate one comparison operation, and the level at a terminal 1 is compared with the comparison level by the similar method again succeedingly and result is given to a register 13. Moreover, the result is given to a register 14 by the similar comparison. The level at the terminal 1 is sampled thrice by the comparison for three times or above and the compared level is constant in the three comparison operations. Then contents of the registers 12-14 are evaluated by a majority decision circuit 18 and the result is given to a final result register 9. Thus, even when disturbance due to noise exists in an input voltage, the probability generating the erroneous result of conversion is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D converter realized on a single semiconductor substrate, and particularly relates to an improvement in its conversion value determination method.

[Conventional technology]

FIG. 2 shows the configuration of a successive approximation type A/D converter built into a microphone computer. In the figure, 1 is the input terminal of the potential to be measured, 2 is the resistance ladder, 3 is the switch set, 4 is the comparator, 5 is the capacitor connected to the input of the comparator 4, 6 and 7 are the input terminals and the resistance ladder, respectively. MOS FET switch that inputs the output potential to capacitor 5, 8 is a 1-bit latch that holds the output of comparator 4, and 9 is a final result register (hereinafter S A ) that holds all bits of the value of the AD conversion result. R: 5uccessi
ve Approximate Register), 10 is a data bus that connects the 5AR9 and the microcomputer, and 1) is a decoder that decodes a signal for controlling the switch set based on the value of the 5AR9.

Next, the operation will be explained.

The potential input from the input terminal 1 is led to the capacitor 5 through the MO3FET 6. At this time, the sample signal is active, and the MOSFET 6 and the bias MO3FET of the comparator 4 are open.

Furthermore, the comparator 4 is biased at the point where the gain of the amplifier is greatest and is in a balanced state. Next, the sample signal is made inactive, the input MO3FF, T6 and the bias MO3FET of the comparator 4 are closed, the reference signal is made active and the comparison voltage selected by the switch set 3 is connected to the output of the resistor ladder 2 through the capacitor through the MOSFET 7. Lead to 5. At this time, the potential at both ends of the capacitor 5 rises and falls at the same time due to the difference between the potential manually applied from the resistor ladder 3 and the potential input from the input terminal 1.

Furthermore, since the comparator 4 is balanced at the point where the gain is greatest, minute changes in the input are amplified and output. The comparison result is then input to the register 8.

The above is one comparison operation, but in a successive approximation type A/D converter, this operation is performed for the number of bits of resolution. Also,
The output of the ladder 2 is performed by controlling the switch set 3 based on the result of the previous comparison operation, and the comparison voltage is gradually driven closer to the input voltage than 172 of VREF. This conversion result is accumulated in 5AR9.

[Problem to be solved by the invention]

Now, let us consider the comparison operation once again.

The input potential of input terminal 1 is when the sample signal is active,
There should be a constant voltage while MOSFET 6 is open. Then, when this potential is compared with the comparison potential obtained from the resistance ladder 3, it can be said that accurate A/D conversion can only be performed.

However, when noise is added to the input potential of input terminal 1 for some reason, or when this coincides with the moment when MOSFET 6 closes, and a potential different from the potential that should be measured is held in capacitor 5, naturally the converted value There was a problem that the code was not correct.

This invention was made to solve the above-mentioned problems, and aims to provide an A/D converter that can reduce the probability that A/D converted values will become inaccurate due to sudden noise. purpose.

[Means to solve the problem]

The A/D converter according to the present invention performs a plurality of comparison operations to obtain a 1-bit comparison result, and stores each result in a register. The outputs of these registers pass through a majority voting circuit and enter the final conversion result register.

[Effect]

Therefore, even if the comparison results happen to be different one time out of multiple times due to noise, the majority circuit will select the larger value as the correct converted value, reducing the probability of outputting an incorrect conversion result. descend.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an A/D converter according to an embodiment of the present invention,
In the figure, 1 to 7 and 9 to 1) are the same as in FIG. 2, so their explanation will be omitted. 12 to 14 are 1-bit registers that hold the output of comparator 4, and 15 to 17 are MOSFETs that connect registers 12 to 14 and comparator 4, respectively.
, 1B is a majority circuit which receives the outputs of the registers 12 to 14 as inputs.

Next, the operation will be explained. First, the sample signal is activated and the potential of the input terminal 1 is introduced to the capacitor 5.

Next, the sample signal is made inactive, the reference signal is made active, the comparison potential determined by the resistor ladder 2 and the switch set 3 is led to the capacitor 5, and the comparison result of these potentials is input into the register 12. This completes one comparison operation. Again, in the same manner as above, the potential of the input terminal 1 is compared with the comparison potential determined by the resistor ladder 2 and switch set 3, and the result is stored in the register 13. Perform the same comparison operation as above once again and store the result in register 1.
Put it in 4. In the above three comparison operations, the potential of the input terminal is sampled three times. On the other hand, the comparison potential determined by the resistance ladder 2 and the switch set 3 is constant during the three comparison operations.

Next, the values in the registers 12 to 14 are evaluated by the majority circuit 18, and the results are entered into 5AR9. For example, register 12.1
When the value of 3 is "1" and the value of the register 14 is "0", the output of the majority circuit 18 is "1". This completes the comparison operation for one bit of the comparison result.

By performing the above operations for the number of bits of resolution, one A
/D conversion operation is completed.

As described above, according to this embodiment, a plurality of comparison operations are performed to obtain the value for one bit of the comparison result of A/D conversion, and the final value is determined by taking a majority vote of the comparison values. As a result, even if the input voltage during the A/D conversion operation is disturbed by noise, noise, etc., the possibility of erroneous conversion results is extremely reduced.

Furthermore, since it is no longer necessary to perform A/D conversion multiple times using microcomputer software and correct the result by calculation, the effective A/D conversion time can be shortened.

In the above embodiment, the comparison operation was performed three times to determine the comparison result of one bit, but the same effect can be obtained by performing the comparison operation an odd number of times, such as three or more.

〔Effect of the invention〕

As described above, according to the A/D converter according to the present invention,
To obtain the value for 1 minute of A/D conversion comparison results, multiple comparison operations are performed, and a majority vote of the comparison values is taken.
Since the final value is determined, even if there is disturbance due to noise or the like at the input terminal during the A/D conversion operation, there is an effect that the probability that the conversion result will be incorrect can be extremely reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the circuit configuration of an A/D converter according to an embodiment of the present invention, and FIG. 2 is a diagram showing the circuit configuration of a conventional A/D converter. In the figure, 1 is the measurement input terminal, 2 is the ladder resistor, 3 is the switch center, 4 is the comparator, 5 is the capacitor, 6, 7
, 15, 16.17 are MOSFETs, 9 is the final result register, 10 is the data bus, 1) is the decoder, 12, 13
．． 14 is a 1-bit register, and 18 is a majority circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A successive approximation type A/D converter includes a comparison circuit that compares the same comparison voltage and input analog voltage multiple times for each bit of resolution, and a register that holds each comparison result for each comparison operation. An A/D converter comprising: a majority circuit that takes a majority vote of the values held in the register; and a final result holding register that holds an output of the majority circuit.