JPH0715337A - One-bit cell and a/d converter - Google Patents
One-bit cell and a/d converterInfo
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- JPH0715337A JPH0715337A JP15326293A JP15326293A JPH0715337A JP H0715337 A JPH0715337 A JP H0715337A JP 15326293 A JP15326293 A JP 15326293A JP 15326293 A JP15326293 A JP 15326293A JP H0715337 A JPH0715337 A JP H0715337A
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- current
- mirror circuit
- circuit
- output
- input
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、アナログ入力電流をデ
ジタル値に変換するアナログ／デジタル変換器に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter for converting an analog input current into a digital value.
【０００２】[0002]
【従来の技術】従来、アナログ入力電流をデジタル値に
変換するアナログ／デジタル変換器（Ａ／Ｄ変換器）に
は、図４に示したものが知られている。2. Description of the Related Art Conventionally, as an analog / digital converter (A / D converter) for converting an analog input current into a digital value, the one shown in FIG. 4 is known.
【０００３】（Journal of Solid-State Circuits vol.
25 No.4 p.997〜1004(1990)）このＡ／Ｄ変換器は、１
ビットセルを直列に接続した構成で、１ビットセルは図
４に示すように、入力電流を２倍にするカレントミラー
と２倍にした入力電流と基準電流を比較する比較器と、
２倍にした入力電流を入力とする電流ミラー回路と比較
器の出力が“１”であればスイッチを閉じて入力電流か
ら基準電流を減算して出力端子から出力し、比較器の出
力が“０”であればスイッチを開いて出力電流として入
力電流の２倍を出力する。比較器の出力がそのまま１ビ
ットセルの出力ビットとなる。(Journal of Solid-State Circuits vol.
25 No.4 p.997-1004 (1990)) This A / D converter
In a configuration in which bit cells are connected in series, a 1-bit cell has a current mirror that doubles an input current, a comparator that compares a doubled input current with a reference current, as shown in FIG.
If the output of the current mirror circuit and the comparator that input the doubled input current is “1”, the switch is closed, the reference current is subtracted from the input current, and the result is output from the output terminal. If it is 0 ", the switch is opened to output twice the input current as the output current. The output of the comparator becomes the output bit of the 1-bit cell as it is.
【０００４】[0004]
【発明が解決しようとする課題】従来のＡ／Ｄ変換器で
は、出力電流を求める電流経路において、入力電流の２
倍の電流から基準電流を減算するときに、Ｍ６−Ｍ９−
Ｍ８とトランジスタを３つ流れる。したがって電源電圧
を低下させたときの下限がＭ６とＭ８の飽和電圧の和と
Ｍ９の電圧降下分できまる。Ｍ９の電圧降下分は、Ｍ９
のオン抵抗と流れる電流の積できまる。電源電圧を低下
させるとトランジスタのオン抵抗は大きくなっていくの
でＭ９での電圧降下も大きくなる。In the conventional A / D converter, in the current path for obtaining the output current, the input current of 2 is input.
When subtracting the reference current from the doubled current, M6-M9-
M3 and three transistors flow. Therefore, the lower limit when the power supply voltage is reduced is the sum of the saturation voltages of M6 and M8 and the voltage drop of M9. The voltage drop of M9 is
It is the product of the on resistance of and the flowing current. When the power supply voltage is lowered, the on-resistance of the transistor increases, and the voltage drop at M9 also increases.
【０００５】それによって低電圧化したときの下限が決
まってくる。As a result, the lower limit when the voltage is lowered is determined.
【０００６】本発明の目的は、低電圧化に適したＡ／Ｄ
変換器を提供することである。An object of the present invention is to provide an A / D suitable for lowering voltage.
It is to provide a converter.
【０００７】[0007]
【課題を解決するための手段】課題を解決するための手
段は、以下の３項に存ずる。[Means for Solving the Problems] Means for solving the problems are included in the following three items.
【０００８】［１］第１の入力端子が電流入力端に接続
され第１及び第２の電流出力端をもつ第１の電流ミラー
回路と、第２の入力端子が電流入力端に接続され、電流
出力端が前記第１の電流ミラー回路の第１の電流出力端
に接続され、前記第１の電流ミラー回路を構成するトラ
ンジスタと異なる導電性のトランジスタで構成された第
２の電流ミラー回路と、前記第１の電流ミラー回路と前
記第２の電流ミラー回路の電流出力端に電流入力端が接
続された第３の電流ミラー回路と、前記第３の電流ミラ
ー回路の電流出力端に電流が流れているか否かを検出す
る検出回路と、電流入力回路を前記第１の電流ミラー回
路の第２の電流出力端に接続された電流入力回路とする
か前記第３の電流ミラー回路の電流入力回路とするかを
切換える手段を備えた第４の電流ミラー回路とから構成
され、前記１ビットセルの第４の電流ミラー回路は、前
記検出回路で電流が検出されれば電流入力回路を前記第
３の電流ミラーの電流入力回路とすると同時に出力ビッ
トとして“１”を出力し、電流が検出されなければ前記
第１の電流ミラー回路の第２の電流出力端に接続された
電流入力回路とすると同時に出力ビットとして“０”を
し、前記第４の電流ミラー回路の電流出力端を１ビット
セルの電流出力端子とすることを特徴とした１ビットセ
ル。[1] A first current mirror circuit having a first input terminal connected to a current input terminal and having first and second current output terminals; and a second input terminal connected to a current input terminal, A second current mirror circuit having a current output terminal connected to the first current output terminal of the first current mirror circuit, the second current mirror circuit including a conductive transistor different from the transistor forming the first current mirror circuit; , A third current mirror circuit having a current input terminal connected to the current output terminals of the first current mirror circuit and the second current mirror circuit, and a current flowing to the current output terminal of the third current mirror circuit. A detection circuit for detecting whether or not it is flowing, and a current input circuit which is a current input circuit connected to a second current output terminal of the first current mirror circuit, or a current input of the third current mirror circuit Equipped with a means to switch between circuits And a fourth current mirror circuit, the fourth current mirror circuit of the 1-bit cell, wherein the current input circuit is the current input circuit of the third current mirror if a current is detected by the detection circuit. At the same time, "1" is output as an output bit, and if no current is detected, the current input circuit is connected to the second current output terminal of the first current mirror circuit, and at the same time, "0" is output as an output bit. A 1-bit cell, wherein the current output terminal of the fourth current mirror circuit is a current output terminal of the 1-bit cell.
【０００９】［２］上記［１］に記載された１ビットセ
ルを、１ビットセルの電流出力端子を次段の１ビットセ
ルの第１の電流入力端に接続して直列に複数個接続し、
初段の１ビットセルの第１の電流入力端子を電流入力端
子とし、初段の第２の入力端子にＩｒ1 の電流を入力
し、２段目以降の第２の入力端子には順次Ｉｒ1 の１／
２ずつになる電流を入力し、１ビットセルの電流ミラー
回路は第３の電流ミラー回路以外はすべて電流ゲインを
１とし、初段の出力ビットを最上位ビットとし、２段目
以降の出力ビットを順次上位からのビットとすることを
特徴としたアナログ／デジタル変換器。[2] A plurality of 1-bit cells described in [1] are connected in series by connecting the current output terminal of the 1-bit cell to the first current input terminal of the 1-bit cell of the next stage.
The first current input terminal of the first-stage 1-bit cell is used as the current input terminal, the current of Ir1 is input to the second input terminal of the first stage, and 1 / Ir of Ir1 is sequentially input to the second input terminals of the second and subsequent stages.
Input the current in increments of 2, set the current gain of all 1-bit cell current mirror circuits to 1 except the third current mirror circuit, set the output bit of the first stage to the most significant bit, and output bits of the second and subsequent stages sequentially. An analog / digital converter characterized by using bits from the higher order.
【００１０】［３］前記［１］に記載された１ビットセ
ルを、１ビットセルの電流出力端子を次段の１ビットセ
ルの第１の入力端子に接続して直列に複数個接続し、す
べての１ビットセルの第２の電流入力端子にはすべて等
しい値の電流を入力し、１ビットセルの第１の電流ミラ
ー回路の電流ゲインは２とし、１ビットセルの第２、第
４の電流ミラー回路の電流ゲインは１とし、初段の出力
ビットを最上位ビットとし、２段目以降の出力ビットを
順次上位からのビットとすることを特徴としたアナログ
／デジタル変換器。[3] The 1-bit cell described in the above [1] is connected in series by connecting the current output terminal of the 1-bit cell to the first input terminal of the 1-bit cell of the next stage, and connecting all the 1-bit cells in series. Currents of the same value are all input to the second current input terminals of the bit cell, the current gain of the first current mirror circuit of the 1-bit cell is 2, and the current gains of the second and fourth current mirror circuits of the 1-bit cell are set. Is 1, the output bit of the first stage is the most significant bit, and the output bits of the second and subsequent stages are sequentially the bits from the higher order.
【００１１】［４］上記［３］に記載されたアナログ／
デジタル変換器において、１ビットセルの第２の電流ミ
ラー回路の電流入力回路を、すべての１ビットセルで共
通にしたことを特徴とするアナログ／デジタル変換器。[4] The analog described in [3] above
In the digital converter, the current input circuit of the second current mirror circuit of 1-bit cells is common to all the 1-bit cells.
【００１２】[0012]
【実施例】本発明の実施例について図面を参照して説明
する。Embodiments of the present invention will be described with reference to the drawings.
【００１３】図１は本発明の第１の実施例の１つであ
る。第１の入力端子１に入力された電流（電流は矢印の
向き）Ｉｉn は、第１の電流ミラー回路３で電流利得Ａ
1 ，Ａ1′倍されてそれぞれ出力端５、１０に出力され
る。FIG. 1 is one of the first embodiments of the present invention. The current (current is in the direction of the arrow) Iin input to the first input terminal 1 is the current gain A in the first current mirror circuit 3.
It is multiplied by 1 and A 1 ′ and output to output terminals 5 and 10, respectively.
【００１４】一方、第２の入力端子２に入力された電流
Ｉｒ1 は第２の電流ミラー回路４でＡ2 倍されて出力端
５に出力される。On the other hand, the current Ir1 input to the second input terminal 2 is multiplied by A2 in the second current mirror circuit 4 and output to the output terminal 5.
【００１５】このときＡ1 Ｉin ＞Ａ2 Ｉr1 であると、
Ａ1 Ｉin −Ａ2 Ｉr1 の電流が第３の電流ミラー回路６
に入力される。したがって電流ミラー回路６の出力端に
は電流が流れる。At this time, if A 1 I in > A 2 I r1 ,
The current of A 1 I in −A 2 I r1 is the third current mirror circuit 6
Entered in. Therefore, a current flows through the output terminal of the current mirror circuit 6.
【００１６】ところがＡ1 Ｉin ＜Ａ2 Ｉr1 であると電
流ミラー回路４の出力にＡ2 Ｉr1の電流を流すことがで
きず出力端５の電位が低下し、電流ミラー回路６には電
流が入力されない。またＡ1 Ｉin ＝Ａ2 Ｉr1のときも
電流ミラー回路３の出力側に流れる電流は電流ミラー回
路４に流れるので電流ミラー回路６には電流が流れな
い。However, if A 1 I in <A 2 I r1 then the current of A 2 I r1 cannot flow to the output of the current mirror circuit 4 and the potential at the output end 5 drops, so that the current mirror circuit 6 receives No current is input. Also, when A 1 I in = A 2 I r1 , the current flowing to the output side of the current mirror circuit 3 flows to the current mirror circuit 4, so that no current flows to the current mirror circuit 6.
【００１７】電流検出回路７は電流ミラー回路６に電流
が流れているか否かを検出する回路である。具体的な例
としては、図１に示したような抵抗とインバータから構
成される。電流ミラー回路６に電流が流れると電流ミラ
ー回路６の出力端と定電圧源の間に接続された抵抗を電
流が流れるのでインバータの入力電位が下がる。それに
よってインバータの出力ｂは高レベルすなわち“１”と
なる。ところが電流ミラー回路６に電流が流れないと抵
抗にも電流が流れないのでインバータの入力電位は高レ
ベルのままでインバータの出力ｂは低レベルすなわち
“０”となる。The current detection circuit 7 is a circuit for detecting whether or not a current is flowing through the current mirror circuit 6. As a specific example, it is composed of a resistor and an inverter as shown in FIG. When a current flows through the current mirror circuit 6, the current flows through a resistor connected between the output terminal of the current mirror circuit 6 and the constant voltage source, so that the input potential of the inverter drops. As a result, the output b of the inverter becomes high level, that is, "1". However, if no current flows through the current mirror circuit 6, no current flows through the resistor either, so that the input potential of the inverter remains at high level and the output b of the inverter becomes low level, that is, "0".
【００１８】このようにして電流検出回路７の出力ｂ
を、電流ミラー回路６に電流が流れていれば“１”、流
れていなければ“０”とすることができる。また、電流
検出回路７において、抵抗Ｒの代わりにトランジスタを
用いても同様な機能を実現できるし、またスイッチを挿
入してダイナミックな回路とすることも容易である。こ
の出力ｂはそのまま１ビットセルの出力ビットとなる。In this way, the output b of the current detection circuit 7
Can be set to "1" if a current is flowing in the current mirror circuit 6 and can be set to "0" if no current is flowing. Also, in the current detection circuit 7, the same function can be realized by using a transistor instead of the resistor R, and it is easy to insert a switch to form a dynamic circuit. This output b becomes the output bit of the 1-bit cell as it is.
【００１９】電流検出回路７の出力ｂに応じて電流ミラ
ー回路８の中のスイッチＳ1 で入力電流回路が切換わ
る。ｂが“０”のときは電流ミラー回路３の第２の出力
端１０に接続された入力電流回路に接続され、ｂが
“１”のときは電流ミラー回路６の電流入力回路に切換
わる。したがって、ｂが“０”のときは電流ミラー回路
８の出力電流は電流ゲインＡ4 とするとＡ4 （Ａ1 ′Ｉ
in ）で、ｂが“１”のときはＡ4 （Ａ1 Ｉin −Ａ2 Ｉ
r1 ）の電流となる。The input current circuit is switched by the switch S 1 in the current mirror circuit 8 according to the output b of the current detection circuit 7. When b is "0", it is connected to the input current circuit connected to the second output terminal 10 of the current mirror circuit 3, and when b is "1", it switches to the current input circuit of the current mirror circuit 6. Therefore, when b is the output current of the current mirror circuit 8 when the "0" and the current gain A4 A 4 (A 1 'I
in ) and b is “1”, A 4 (A 1 I in −A 2 I
The current is r1 ).
【００２０】ここで第２に記載された１ビットセルの直
列接続を考える。第２図にその実施例を示す。このとき
電流ミラー回路の電流ゲインはＡ1 ＝Ａ1 ′＝Ａ2 ＝Ａ
4 ＝１である。したがってこの構成では、１ビットセル
の第１の入力端子に入力される電流をＩ1 、第２の入力
端子に入力される電流をＩ2 とするとＩ1 ＞Ｉ2 であれ
ばｂ＝１、出力電流はＩ1 −Ｉ2 、Ｉ1 ≦Ｉ2 であれば
ｂ＝０、出力電流はＩ1である。ｎ段目のＩ2 をＩrn と
すると２段目以降は順次Ｉｒ1 の１／２ずつになってい
くので Ｉr2 ＝（１／２）Ｉr1 、Ｉr3 ＝（１／２）Ｉr2 ＝
（１／２2）Ｉr1 ，…，Ｉrn ＝（１／２）Ｉr(n-1) ＝
（１／２n-1 ）Ｉr1… (1) である。したがって初段目の第１の入力端子に入力され
る電流をＩｉn とするとｎ段目の入力電流Ｉｎは、 Ｉn＝Ｉin −ｂ1 Ｉr1 −ｂ2 Ｉr2 −…−ｂn-1 Ｉrn-1 ＝Ｉin −ｂ1 Ｉr1 −（１／２）ｂ2Ｉr1 −（１／
２2）ｂ3Ｉr1−…−（１／２n-2 ）ｂn-1Ｉr1…
（２） となる。ただしｂ１ はｉ段目の１ビットセルの出力ビ
ットである。Now, consider the serial connection of the 1-bit cells described in the second. An example thereof is shown in FIG. At this time, the current gain of the current mirror circuit is A 1 = A 1 ′ = A 2 = A
4 = 1. Thus, in this arrangement, the current input to the first input terminal of the bit cell I1, b = 1 if I 1> I 2 When the current input to the second input terminal and I2, the output current If I 1 -I 2 and I 1 ≤I 2 , then b = 0 and the output current is I 1. If I 2 of the n-th stage is set to I rn , 1/2 of the Ir 1 is sequentially obtained in the second and subsequent stages, so that I r2 = (1/2) I r1 and I r3 = (1/2) I r2 =
(1/2 2 ) I r1 , ..., I rn = (1/2) I r (n-1) =
(1/2 n-1 ) I r1 (1) Thus the input current In of the n-th stage when the current to the Iin input to the first input terminal of the first-stage th, I n = I in -b 1 I r1 -b 2 I r2 - ... -b n -1 I rn-1 = I in -b 1 I r1 - (1/2) b 2 I r1 - (1 /
2 2 ) b 3 I r1 -...- (1/2 n-2 ) b n-1 I r1 ...
(2) However, b 1 is the output bit of the 1-bit cell in the i-th stage.
【００２１】(2) であわらわされる電流Ｉn と（１／２
n-1 ）Ｉr1 の大小関係によってｂｎが決まる。この結
果は、よく知られているように、２Ｉr1 をフルスケー
ルとし、ｂ1 を最上位ビットとしｂ2 以下を順次上位か
らのビットとするＡ／Ｄ変換器をあらわす。(2) The current I n and ((1/2)
bn is determined by the magnitude relation of ( n-1 ) I r1 . As is well known, this result represents an A / D converter in which 2I r1 is full scale, b 1 is the most significant bit, and b 2 and less are sequentially bits from the higher order.
【００２２】したがって第２で接続する１ビットセルの
数をｎとすると分解能がｎビットのＡ／Ｄ変換器ができ
る。Therefore, assuming that the number of 1-bit cells connected in the second is n, an A / D converter having a resolution of n bits can be obtained.
【００２３】このＡ／Ｄ変換器において、各１ビットセ
ルの構成で正側電源電圧と負側電源電圧との間の電流経
路中の縦積みトランジスタはＮＭＯＳＦＥＴとＰＭＯＳ
ＦＥＴそれぞれ１個ずつであり、従来技術で述べたトラ
ンジスタ３個より少ない。また電流経路の中にスイッチ
を含まないのでオン抵抗によって制限されない。In this A / D converter, the vertically stacked transistors in the current path between the positive power supply voltage and the negative power supply voltage in each 1-bit cell configuration are NMOSFET and PMOS.
There is one FET each, which is less than the three transistors described in the prior art. Further, since the switch is not included in the current path, it is not limited by the ON resistance.
【００２４】したがって本実施例では従来より低電圧化
に適したＡ／Ｄ変換器を提供することができる。Therefore, in the present embodiment, it is possible to provide an A / D converter more suitable for lowering the voltage than ever before.
【００２５】第３に記載された１ビットセルは、Ａ1 ＝
２、Ａ2 ＝Ａ4 ＝１である。また第２の電流入力端には
等しい電流を入力する。したがって各セルでは第１の入
力電流をＩ1 、第２の入力電流をＩr とすると ２Ｉ1 ＞ Ｉr であれば ｂ＝１ ２Ｉ1 ＜ Ｉr であれば ｂ＝０ である。したがってｎ段目のビットセルの第１の入力端
への電流Ｉｎは初段の第１の入力電流をＩin とすると Ｉｎ＝２Ｉn-1 −ｂn-1 Ｉr ＝２（２Ｉn-2 −ｂn-2 Ｉr ）−ｂn -1 Ｉr ＝２n-1 Ｉin −ｂ1 ２n-2 Ｉr −ｂ2 ２n-3 Ｉr −…
−ｂn-1 Ｉr … (3) (3) 式もよく知られているようにフルスケールをＩrと
したｎビットのアナログ／デジタル変換器をあらわす式
である。(2) 式と(3) 式の違いすなわち第２と第３の実
施例の違いは各ビットセルの比較電流を順次１／２にす
る（第２の実施例のＡ／Ｄ変換器）かわりに入力電流を
２倍にする（第３の実施例のＡ／Ｄ変換器）だけであ
る。したがって第３の実施例のＡ／Ｄ変換器を図面に示
すと第３図のようになり、第２図とは１ビットセルの第
２の入力電流が異なる。また１ビットセルの中の電流ゲ
インは実施例で述べたように異なっている。このＡ／Ｄ
変換器も低電圧化に適しているのは第２で述べたＡ／Ｄ
変換器の場合と同様である。第４で記載されたＡ／Ｄ変
換器は、交換原理は第３で記載したＡ／Ｄ変換器と同一
である。ただし、第３で記載したＡ／Ｄ変換器は、各ビ
ットセルの第２の入力端には等しい値の電流を与えてい
た。図１に示すようにビットセルの第２の入力端は、第
２の電流ミラー回路の電流入力端となっている。したが
って各ビットセルの第２の電流ミラー回路の電流入力回
路を共通にしても変換動作にはまったく影響がない。ま
た共通化することで消費電流を減少させることができ
る。The 1-bit cell described in the third is A 1 =
2, A 2 = A 4 = 1. Further, the same current is input to the second current input terminal. Therefore, in each cell, if the first input current is I 1 and the second input current is I r , b = 1 if 2I 1 > I r , and b = 0 if 2I 1 <I r . Therefore, the current In to the first input terminal of the n-th bit cell is In = 2I n-1 −b n−1 I r = 2 (2I n−2 −), where I in is the first input current of the first stage. b n-2 I r) -b n -1 I r = 2 n-1 I in -b 1 2 n-2 I r -b 2 2 n-3 I r - ...
As well known, −b n−1 I r (3) (3) is also an expression representing an n-bit analog / digital converter in which full scale is I r . The difference between the equations (2) and (3), that is, the difference between the second and third embodiments, is that the comparison current of each bit cell is sequentially halved (A / D converter of the second embodiment). It only doubles the input current (A / D converter of the third embodiment). Therefore, FIG. 3 shows the A / D converter of the third embodiment in the drawing, and the second input current of the 1-bit cell is different from that of FIG. The current gain in the 1-bit cell is different as described in the embodiment. This A / D
The converter is also suitable for lowering the voltage.
It is similar to the case of the converter. The exchange principle of the A / D converter described in the fourth is the same as that of the A / D converter described in the third. However, in the A / D converter described in the third, the current of the same value was applied to the second input terminal of each bit cell. As shown in FIG. 1, the second input end of the bit cell is the current input end of the second current mirror circuit. Therefore, the common operation of the current input circuit of the second current mirror circuit of each bit cell does not affect the conversion operation at all. Further, the common use can reduce the current consumption.
【００２６】[0026]
【発明の効果】以上述べたように本発明では、低い電源
電圧範囲で動作ができ、また電流モードで動作するため
ノイズに強く、かつ消費電流の低いＡ／Ｄ変換器を提供
することができる。As described above, according to the present invention, it is possible to provide an A / D converter that can operate in a low power supply voltage range and operates in a current mode, which is resistant to noise and consumes less current. .
【図１】本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
【図３】本発明の第３の実施例を示す回路図である。FIG. 3 is a circuit diagram showing a third embodiment of the present invention.
【図４】図４は従来技術を示す回路図である。FIG. 4 is a circuit diagram showing a conventional technique.
１ 第１の電流入力端 ２ 第２の電流入力端 ３ 第１の電流ミラー回路 ４ 第２の電流ミラー回路 ５ 第１の電流ミラー回路の第１の電流出力端 ６ 第３の電流ミラー回路 ７ 電流検出回路 ８ 第４の電流ミラー回路 ９ 電流出力端 １０ 第１の電流ミラー回路の第２の電流出力端 １１ 出力ビットの出力端 1 1st current input terminal 2 2nd current input terminal 3 1st current mirror circuit 4 2nd current mirror circuit 5 1st current output terminal of 1st current mirror circuit 6 3rd current mirror circuit 7 Current detection circuit 8 Fourth current mirror circuit 9 Current output terminal 10 Second current output terminal of first current mirror circuit 11 Output terminal of output bit
Claims (4)
ナログ電流をディジタル化する１ビットセルを複数個配
列して構成されるアナログ／デジタル変換器において、 第１の入力端子が電流入力端に接続され第１及び第２の
電流出力端をもつ第１の電流ミラー回路と、 第２の入力端子が電流入力端に接続され、電流出力端が
前記第１の電流ミラー回路の第１の電流出力端に接続さ
れ、前記第１の電流ミラー回路を構成するトランジスタ
と異なる導電性のトランジスタで構成された第２の電流
ミラー回路と、前記第１の電流ミラー回路と前記第２の
電流ミラー回路の電流出力端に電流入力端が接続された
第３の電流ミラー回路と、 前記第３の電流ミラー回路の電流出力端に電流が流れて
いるか否かを検出する検出回路と、 電流入力回路を前記第１の電流ミラー回路の第２の電流
出力端に接続された電流入力回路とするか前記第３の電
流ミラー回路の電流入力回路とするかを切換える手段を
備えた第４の電流ミラー回路とから構成され、 前記１ビットセルの第４の電流ミラー回路は、前記検出
回路で電流が検出されれば電流入力回路を前記第３の電
流ミラーの電流入力回路とすると同時に出力ビットとし
て“１”を出力し、電流が検出されなければ前記第１の
電流ミラー回路の第２の電流出力端に接続された電流入
力回路とすると同時に出力ビットとして“０”をし、 前記第４の電流ミラー回路の電流出力端を１ビットセル
の電流出力端子とすることを特徴とした１ビットセル。1. An analog-to-digital converter comprising a current mirror circuit and the like, wherein a plurality of 1-bit cells for digitizing an analog current are arranged, wherein a first input terminal is connected to a current input terminal. A first current mirror circuit having first and second current output terminals, a second input terminal connected to the current input terminal, and a current output terminal connected to the first current output terminal of the first current mirror circuit. A second current mirror circuit connected to the first current mirror circuit, the second current mirror circuit including a conductive transistor different from the transistor forming the first current mirror circuit; and current outputs of the first current mirror circuit and the second current mirror circuit. A third current mirror circuit having a current input terminal connected to its end; a detection circuit for detecting whether or not a current is flowing to the current output terminal of the third current mirror circuit; And a fourth current mirror circuit having means for switching between a current input circuit connected to the second current output terminal of the first current mirror circuit and a current input circuit of the third current mirror circuit. The fourth current mirror circuit of the 1-bit cell uses the current input circuit as the current input circuit of the third current mirror when a current is detected by the detection circuit, and at the same time outputs "1" as an output bit. If the current is not detected, the current input circuit is connected to the second current output terminal of the first current mirror circuit, and at the same time, the output bit is set to “0”, and the current of the fourth current mirror circuit is changed. A 1-bit cell characterized in that the output terminal is a current output terminal of the 1-bit cell.
１ビットセルの電流出力端子を次段の１ビットセルの第
１の電流入力端に接続して直列に複数個接続し、初段の
１ビットセルの第１の電流入力端子を電流入力端子と
し、初段の第２の入力端子にＩｒ1 の電流を入力し、２
段目以降の第２の入力端子には順次Ｉｒ1 の１／２ずつ
になる電流を入力し、１ビットセルの電流ミラー回路は
第３の電流ミラー回路以外はすべて電流ゲインを１と
し、初段の出力ビットを最上位ビットとし、２段目以降
の出力ビットを順次上位からのビットとすることを特徴
としたアナログ／デジタル変換器。2. The 1-bit cell according to claim 1,
The current output terminal of the 1-bit cell is connected to the first current input terminal of the 1-bit cell of the next stage and connected in series, and the first current input terminal of the 1-bit cell of the first stage is used as the current input terminal. Input the current of Ir1 to the input terminal of 2 and
The second input terminal after the second stage sequentially inputs a current that becomes 1/2 each of Ir1, and the current gain of the 1-bit cell current mirror circuit is 1 except for the third current mirror circuit, and the output of the first stage is set. An analog / digital converter characterized in that the bit is the most significant bit and the output bits of the second and subsequent stages are sequentially the bits from the higher order.
１ビットセルの電流出力端子を次段の１ビットセルの第
１の入力端子に接続して直列に複数個接続し、すべての
１ビットセルの第２の電流入力端子にはすべて等しい値
の電流を入力し、１ビットセルの第１の電流ミラー回路
の電流ゲインは２とし、１ビットセルの第２、第４の電
流ミラー回路の電流ゲインは１とし、初段の出力ビット
を最上位ビットとし、２段目以降の出力ビットを順次上
位からのビットとすることを特徴としたアナログ／デジ
タル変換器。3. The 1-bit cell according to claim 1,
Connect the current output terminal of the 1-bit cell to the first input terminal of the next-stage 1-bit cell and connect a plurality of them in series. Input equal currents to the second current input terminals of all 1-bit cells. The current gain of the first current mirror circuit of the 1-bit cell is 2, the current gain of the second and fourth current mirror circuits of the 1-bit cell is 1, the output bit of the first stage is the most significant bit, and the second and subsequent stages. An analog / digital converter characterized in that the output bits of are sequentially output from the upper bits.
ル変換器において、１ビットセルの第２の電流ミラー回
路の電流入力回路を、すべての１ビットセルで共通にし
たことを特徴とするアナログ／デジタル変換器。4. The analog / digital converter according to claim 3, wherein the current input circuit of the second current mirror circuit of 1-bit cells is common to all 1-bit cells. converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5153262A JP2560980B2 (en) | 1993-06-24 | 1993-06-24 | 1-bit cell and analog / digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5153262A JP2560980B2 (en) | 1993-06-24 | 1993-06-24 | 1-bit cell and analog / digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0715337A true JPH0715337A (en) | 1995-01-17 |
| JP2560980B2 JP2560980B2 (en) | 1996-12-04 |
Family
ID=15558614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5153262A Expired - Lifetime JP2560980B2 (en) | 1993-06-24 | 1993-06-24 | 1-bit cell and analog / digital converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2560980B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5866233A (en) * | 1995-06-12 | 1999-02-02 | Meiwa Gravure Co., Ltd. | Decorative sheet with changeable color or density |
| US6103345A (en) * | 1995-02-12 | 2000-08-15 | Meiwa Gravure Co., Ltd. | Decorative sheet with changeable color or density |
-
1993
- 1993-06-24 JP JP5153262A patent/JP2560980B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6103345A (en) * | 1995-02-12 | 2000-08-15 | Meiwa Gravure Co., Ltd. | Decorative sheet with changeable color or density |
| US5866233A (en) * | 1995-06-12 | 1999-02-02 | Meiwa Gravure Co., Ltd. | Decorative sheet with changeable color or density |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2560980B2 (en) | 1996-12-04 |
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