JPH03185734A - Bipolar transistor - Google Patents

Abstract

PURPOSE:To enhance the reliability of an element and to realize its high-speed operation by a method wherein a specific metal silicide layer is used when an electrode of an impurity diffusion region whose conductivity type is opposite to that of a substrate is extracted and two bipolar elements to be laminated are connected. CONSTITUTION:The surface of a base region 6 is provided with a cobalt silicide layer (CoSi2) layer 8. Regarding the cobalt silicide layer 8, its lattice constant is set to a value close to the lattice constant of silicon, and, at the same time, its resistance value is comparatively low. Thereby, even when a heat treatment is executed to form a silicide, an uneven part is not formed at an interface between the silicide layer 8 and the base region 6 in a bipolar transistor due to the continuity of a crystal. Since the resistance value is low, a collector resistance is reduced and a high speed of an element is achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a bipolar transistor using a metal silicide layer for electrode extraction and connection between elements.

[Summary of the Invention] The present invention provides a bipolar transistor having a structure in which an element is formed on a single crystal silicon substrate or another bipolar transistor element is stacked on a single crystal silicon substrate, in which an impurity of the opposite conductivity type to that of the substrate is formed. By using a metal silicide layer having a lattice constant close to the lattice constant of the single-crystal silicon of the base so that the crystallinity can be substantially continuous, for the electrode extraction of the diffusion region and the connection between the two stacked bipolar transistor elements, The purpose is to improve the reliability of the device and achieve high-speed operation.

(Prior art) As a technique for increasing the speed of bipolar transistors, a technique is known in which a polycrystalline silicon layer is used to take out the base electrode and an emitter is obtained with a self-alignment line (for example, "Nikkei Micro Devices J, 1989 February issue, 43
See pages 55 to 55 (Nikkei BP). ).

In such a bipolar transistor, a polycrystalline silicon layer is used to extract the base t8ii, and the external base region formed on the surface of the silicon substrate is formed from impurity diffusion from the polycrystalline silicon layer. The polycrystalline silicon layer is opened in a region where an emitter is to be formed, and an emitter region having a narrow emitter width is formed in the internal base region in a self-aligned manner between sidewall oxide films formed in the opening.

[Problem N to be solved by the invention] In order to operate a bipolar transistor with such a structure at high speed, the base width should be made as thin as possible, and the contact resistance of the polycrystalline silicon layer for taking out the base electrode should be made as thin as possible. Although it is possible to reduce the base width by adjusting the energy of ion implantation, it is currently difficult to reduce the contact resistance of the polycrystalline silicon layer from which the base electrode is taken out. be.

In order to reduce contact resistance, it is possible to use a high melting point metal or its silicide layer, but when titanium or the like is used, unevenness is likely to occur at the interface with single crystal silicon due to heat treatment.

In addition, three-dimensional structuring is being considered as an attempt to improve the degree of integration, but the crystallinity of bipolar transistors is an important element in terms of device characteristics, and the elements stacked on the substrate are also single-crystal. It is desirable that

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a bipolar transistor having a structure that realizes high-speed operation and has a highly reliable element.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the bipolar transistor of the first invention of the present application has an element isolation region selectively formed in a single crystal silicon substrate of a first conductivity type, and A second conductivity type impurity diffusion region is formed on the surface of the single crystal silicon substrate surrounded by the isolation region, and the second conductivity type impurity diffusion region is interposed between the second conductivity type impurity diffusion region and the single crystal silicon base. A first conductivity type impurity diffusion region is formed in contact with a second conductivity type impurity diffusion region, and a metal silicide layer for taking out an electrode is formed on the surface of the second conductivity type impurity diffusion region. The lattice constant of the substrate is characterized by being close to the lattice constant of single crystal silicon constituting the base so that the crystallinity is substantially continuous.

Moreover, the bipolar transistor of the second invention of the present application is
This is a structure in which another bipolar transistor element is stacked on a first bipolar transistor element, and the first bipolar transistor element is formed on a single crystal silicon substrate, and is in contact with the first bipolar transistor element between the elements. A metal silicide layer is formed to connect the metal silicide layers, and the other bipolar transistor elements are formed on the metal silicide layer. It is characterized by a nearly continuous gender.

As the metal silicide layer used in each of the above inventions, cobalt silicide (CoSi) is used due to the lattice constant of silicon.
), nickel silicide (NiSiz), palladium silicide (PdSi).

Platinum silicide (PtSi) etc. are suitable.

[Function] In the bipolar transistor of the first invention, since the impurity diffusion region of the second conductivity type used as the heath region is formed on the surface of the single crystal silicon substrate, the impurity diffusion region of the second conductivity type is formed on the surface of the single crystal silicon substrate. Made of single crystal silicon. Therefore, even when forming a low-resistance metal silicide layer, if its lattice constant is not close to that of single-crystal silicon, unevenness will occur at the interface between the silicide layer and the silicon substrate, resulting in a highly reliable device. can't get it. Therefore, by selecting the lattice constant of the metal silicide layer to be close to that of the single-crystal silicon substrate, the metal silicide layer can be formed with continuous crystallinity, making it possible to obtain highly reliable devices. It is said that

The bipolar transistor of the second invention has a structure in which other monocrystalline bipolar transistor elements are stacked on the first bipolar transistor element formed of monocrystalline silicon, and each of these bipolar transistor elements By using a metal silicide layer having a lattice constant close to that of the single crystal silicon for connection therebetween, it is possible to maintain good crystallinity of the bipolar transistor element as described above. Therefore, it is advantageous for high-speed operation and can improve the reliability of the device.

(Example) As mentioned above, in the bipolar transistor of the present invention, the selection of the metal silicide layer is important. explain.

(Hereinafter, blank space) Co51z and N15iz are cubic system, PtSi,
PdSi and Ti5iz are orthorhombic, and WSi2 is tetragonal. In the lattice constant, PtSi, PdSi, Ti5iz
, WSi, are data of each a-axis.

As is clear from this table, Co, Ni, Pt, Pd
Each silicide has a lattice constant of single crystal silicon of 5.430
It has a lattice constant close to 35%, and the resistance value shows that Co silicide has a low resistance comparable to Ti silicide.

First Example Next, referring to FIG. 1 and FIGS. 2a to 2f,
The bipolar transistor of this example will be explained.

The bipolar transistor of this example is an example in which a cobalt silicide layer as a metal silicide layer is formed on a mousse region.

In the bipolar transistor of this embodiment, as shown in FIG. 1, an n-type buried layer 2 consisting of an n-type high concentration impurity diffusion region is formed on a p-type silicon substrate 1. An n-type epitaxial layer 3, which is a single crystal silicon substrate, is laminated. This n-type epitaxial layer 3 is element-isolated by a thick silicon oxide film 4 formed by selective oxidation. 3 is separated into an island-like region 5 on the surface of which a base region 6 is formed, and a collector extraction region 7.

The base region 6 is made of a p-type impurity diffusion region, and its crystallinity is single crystal. This base region 6 is formed over substantially the entire surface of the island region 5 surrounded by the thick silicon oxide film 4. The collector extraction region 7 consists of an n° type impurity diffusion region. The bipolar transistor of this embodiment has a cobalt silicide (CoSiz) layer 8 on the surface of the base region 6. This cobalt silicide layer 8 has a lattice constant of 5,365, which is close to the lattice constant of silicon, 5.43035, as described above.
It is said to be human, and at the same time has a relatively low resistance value of 18 to 20 μΩ·0. Therefore, even when silicidation is attempted by heat treatment, the bipolar transistor of this embodiment has a structure in which the silicide layer 8 and the base region 6 are separated from each other due to the continuity of the crystal.
Since there is no problem of unevenness occurring at the interface between the two, and the resistance value is low, the contact resistance can be reduced and the speed of the device can be increased.

A part of the cobalt silicide layer 8 covering the surface of the base region 6 is opened together with the glabella insulating film 9 covering the cobalt silicide layer 8, and the side wall of the opening 19 is made of a silicon oxide film or the like. Sidewall part 10.
10 is formed.

An ivy region 11 made of an n-type epitaxial layer formed by selective epitaxial growth is formed in a region sandwiched between a pair of sidewall portions 10.10.

This emitter region 11 is formed by the same n-type epitaxial layer 3.
is provided through a p-type base region 6 of opposite conductivity type,
and a narrow region between the base region 6 and the sidewall 10.10. Furthermore, a buried tungsten layer 12 is buried above the emitter region 11.

The interlayer insulating film 9 further includes a cobalt silicide layer 8.
A contact hole 13 is formed thereon, and a contact hole 15 is also formed on the cobalt silicide layer 14 above the collector extraction f+I region 7. Then, a base electrode layer 16 is formed in the contact hole 13, an emitter electrode layer 17 is formed connected to the buried tungsten layer 12, and a collector electrode layer 18 is formed in the contact hole 15;
6 (JF[is done. Each of these electrode layers 16.17.1
Each of 8 is made of an aluminum-based wiring layer, and in particular, the base electrode layer 16 is connected to the base region 6 via the low-resistance cobalt silicide layer 8, so its contact resistance is low, and the high-speed operation of the bipolar transistor is achieved. make it possible.

Next, a method for manufacturing the bipolar transistor having the structure shown in FIG. 1 will be described with reference to FIGS. 2a to 2f.

First, as shown in FIG. 2a, an n-type buried layer 2 for collector connection is selectively formed in a region of a p-type silicon substrate 1 where elements are to be formed. After forming the n-type buried layer 2, an n-type epitaxial layer 3 is laminated on the entire surface including the n-type buried layer 2. After laminating the n-type epitaxial layer 3, the epitaxial layer 3 is selectively
is oxidized to form a thick silicon oxide film 4. This thick silicon oxide film 4 separates each element,
Further, an island-like region 5 in which a base region and the like are formed and a collector take-out region 7 for taking out the collector are separated.

Next, as shown in FIG. 2, a shallow p-type impurity diffusion region is formed on the surface of the island region 5, and this p-type impurity diffusion region is used as the base region 6.

Note that the base region 6 formed here may be only an external region, and in that case, the internal base region may be formed at the time of forming the opening in a later step.

Further, n-type impurities are introduced into the collector extraction region 7 at a high concentration.

After the base region 6 is formed on the surface of the single crystal epitaxial layer 3, a cobalt layer is deposited on the entire surface, and the cobalt layer is heat-treated by a method such as IR (infrared M) annealing. Through this heat treatment, as shown in FIG. 2C, a cobalt silicide layer 8 is selectively formed on the exposed silicon surface of the single crystal in a self-aligned manner. At the same time, a cobalt silicide layer 14 is also formed on the surface of the collector extraction region 7. The unreacted cobalt layer is removed by etching, and the cobalt layer on the thick silicon oxide film 4 is also removed. During the above heat treatment, if the lattice constant is not close to that of silicon, such as titanium silicide, the interface between the silicide layer and single crystal silicon will not be flat and unevenness will occur. In a silicide layer whose lattice constant is close to that of silicon, the crystallinity is almost continuous, and the interface between the silicide layer and single crystal silicon remains flat, resulting in improved device reliability. Improves sex.

Next, a glabellar insulating film 9 is formed on the entire surface using, for example, a silicon oxide film. After forming the glabellar insulating film 9 to a predetermined thickness, as shown in FIG. 2d, an opening 19 for forming the ivy area is formed. The opening 19 is formed by forming a selectively exposed and developed resist layer on the glabellar insulating film 9 as a mask, and then performing anisotropic etching such as RIE. This opening 19 opens the interlayer insulating film 9 and the cobalt silicide layer 8, and the surface of the base region 6 is exposed at the bottom thereof. Further, the side wall of this opening 19 has a substantially vertical shape.

Next, a silicon oxide film is deposited on the entire surface including the inside of the opening 19. The silicon oxide film is formed by, for example, a CVD method. Subsequently, the silicon oxide film is etched. Then, the silicon oxide film remains only on the sidewall of the opening 19 as a sidewall portion 10.10. This sidewall 10.10 allows the vines to be formed to be narrow and at the same time provides insulation between the emitter electrode and the base region.

After forming the sidewalls 10.10, an n-type single crystal silicon layer is deposited in the region between the sidewalls 10.10 by selective epitaxial growth. This n-type single-crystal silicon layer becomes the ivy region 11. Here, the n-type single crystal silicon layer is SiH2C containing PO, etc.
It may be formed using 1 g (dichlorosilane) or the like. The reaction formula is: After forming the emitter w4 region II made of such an n-type single crystal silicon layer, gas is continuously supplied to WF6.
(tungsten hexafluoride) + 5iH4 (silane). Then, the buried tungsten layer 12 is continuously stacked on the emitter region 11 within the opening 19. Note that the ratio of WFh to 5iHn gas (sccm) is, for example, about 10/9. By embedding the tungsten layer 12 in the opening 19 in this manner, problems such as breakage in the formation of the emitter electrode can be prevented.

After forming such a buried tungsten layer 12,
As shown in FIG. 2f, contact holes 13 and 15 are formed using photolithography. At the bottom of contact hole 13, cobalt silicide layer 8 on base region 6 is exposed, and at the bottom of contact hole 15, cobalt silicide layer 14 on collector extraction region 7 is exposed. Then, as shown in FIG. 2f, an aluminum-based wiring layer 20 is formed over the entire surface. Thereafter, this aluminum-based wiring layer 20 is patterned into a desired pattern to form an emitter electrode layer 17. as shown in FIG. Heath electrode layer 16. A collector electrode layer 18 is obtained. In this case, since the heath electrode layer 16 is electrically connected to the base region 6 via the cobalt silicide layer 8, the contact resistance can be significantly lowered, allowing high-speed operation of the device.

Second Embodiment The bipolar transistor of this embodiment has a structure in which two bipolar transistor elements are stacked, and forms a differential amplifier that operates at high speed.

First, its structure is shown in FIG. As shown in Figure 3,
In the bipolar transistor of this embodiment, an n-type buried l1i32 consisting of an n-type high concentration impurity diffusion region is formed on a p-type silicon substrate 31, and an n-type buried l1i32 made of an n-type high concentration impurity diffusion region is formed on a p-type silicon substrate 31. Epitaxial layers 33 are stacked.

This n-type epitaxial layer 33 is pre-isolated by a thick silicon oxide film 34 formed by a selective oxidation method, and is surrounded by the thick silicon oxide film 34 that functions as an element isolation region. layer 33
is separated into an island-like region 35 on the surface of which a base region 36 is formed, and a collector extraction region 37.

A heath region 36 made of a p-type impurity diffusion region is formed at a required depth on the surface of the island region 35 , and this hese region 36 is formed on the surface of the island region 35 surrounded by a thick silicon oxide film 34 . It is formed over almost the entire surface. Further, the collector extraction region 37 consists of an n-type impurity diffusion region. These base areas 36. The surface of the collector extraction region 37 is made of cobalt silicide (CoSt).
t) Layers 3B and 39 are formed, respectively. The cobalt silicide layer 38 formed on the surface of the base region 36 is intended to reduce the resistance of the electrode extraction from the base, and because its lattice constant is close to that of silicon constituting the heath region 36, it can be easily removed after heat treatment. However, the interface between the two can be made flat. A tungsten layer 40 is formed on top of the cobalt silicide layer 38, and necessary signals are supplied to the head via an electrode layer (not shown).

This tungsten layer 40 and cobalt silicide layer 38.
A reflowable interlayer insulating film 41 such as PSG is provided on 39 . An opening 47 is formed in the interlayer insulating film 41 in a region where an emitter is to be formed. At the bottom of the opening 47, the cobalt silicide layer 3 is removed to reveal the base region 36. On the side wall of the opening 47,
Sidewall portions 44, 44 made of an insulating material are formed. An emitter region 45 made of an n-type epitaxial layer is formed on the base region 36 between the sidewall portions 44, 44. Further, the interlayer insulating film 41 is also opened above the collector extraction region 37, and the opening 43
A tungsten layer 43 is formed as a collector electrode.

A cobalt silicide layer 46 is provided above the emitter region 45 to electrically connect the two bipolar transistor elements.

Since the lattice constant of this cobalt silicide layer 46 is close to that of the silicon epitaxial layer, the crystallinity of the cobalt silicide layer 46 is continuous across the layers above and below it. An n-type epitaxial layer is formed on top of this cobalt silicide N46, and this n-type epitaxial layer serves as the emitter region 4B of another bipolar transistor element. The surface of this l5 ivy region 48 is covered with a cobalt silicide layer 49, and an electrode is taken out by tungsten Jlii 50 through the cobalt silicide layer 49.

Tungsten layer 43.50. Cobalt silicide layer 49
A glabellar insulating film 51 is formed thereon to cover the entire surface, and the interlayer insulating film 51 has an opening 52 above the emitter region 48 . This opening 52 has a substantially vertical side wall, and a side wall portion 53 is formed on the side wall. Then, in contact with the first area [48] facing between the sidewall portions 53, a p
A mold base region 54 is formed. Since the step of the opening 52 is alleviated by the sidewall portion 53, the heath region 54 is extended to the top of the glabella insulating film 51 in contact with the emitter region 48.

An n-type epitaxial layer is also formed on this base region 54 by selective epitaxial growth. This n-type epitaxial layer is the collector region 55.

Collector area 55. The base regions 54 are each covered with an interlayer insulating film 56, and contact holes 57 and 58 are formed in the glabellar insulating film 56. contact hole 5
A contact hole 7 is opened for contact with the base region 54 extending on the interlayer insulation wA51, and a contact hole 58 is opened for contact with the collector region 55. In each contact hole 57, 58, a cobalt silicide layer 59, 60 is formed, and a tungsten layer 62, 61 is embedded. Then, argonium-based wiring layers 64 and 63 are formed so as to be connected at the upper ends of these tungsten layers 62 and 61.

The bipolar transistor having the structure described above has a structure in which two elements are three-dimensionally stacked. The lower bipolar transistor is an npn type transistor having an n-type collector epitaxial layer 33, a base region 36, and an emitter region 45, and the upper bipolar transistor has an emitter region 48. Base region 54.
It is an npn type transistor consisting of a collector region 55.

These two bipolar transistors are connected using the cobalt silicide layer 46 as a contact point and are stacked in a direction perpendicular to the main surface of the substrate, so that the degree of integration can be increased. The upper bipolar transistor uses a single crystal semiconductor layer that is epitaxially grown in order based on a cobalt silicide layer 46 whose lattice constant is so close to that of silicon that its crystallinity is continuous. Since the , base and collector are each made of single crystal, high-speed operation can be achieved.

FIG. 4 shows a preferable differential amplifier using bipolar transistors capable of high-speed operation. This differential amplifier is used, for example, in a comparator of an A/D converter, and uses bipolar transistors Q, Q, whose emitters are commonly connected on the master side, and bipolar transistors Q whose emitters are commonly connected on the slave side.
s, Q4 is used. Note that resistors R1 to R4 are loads, and transistors Qs and Q= have a resistor R between them and the ground line.
s.

It is a constant current source via R4. In such a differential amplifier, high-speed latching is possible by using the above-mentioned stacked structure for the set of bipolar transistors Q, , Q, on the slave side and the set of bipolar transistors Q, , Q, on the master side. becomes.

Next, with reference to FIGS. 5a to 5, a method for manufacturing the bipolar transistor of this embodiment will also be described.

First, as shown in FIG. 5a, a p-type silicon substrate 31
An n-type buried layer 32 is selectively formed thereon. This n° type buried layer 32 is used for electrical connection of the collector. After forming the n-type buried layer 32, an n-type epitaxial layer 33 is laminated on the entire surface including the n-type buried layer 32. After laminating the n-type epitaxial layer 33, the epitaxial layer 33 is selectively oxidized to form a thick silicon oxide film 34. This thick silicon oxide film 34 separates each element, and further separates an island region 35 in which a base region and the like are formed from a collector extraction region 37 for extracting the collector. N-type impurities are introduced into the collector extraction region 37 at a high concentration.

Furthermore, a shallow p-type impurity diffusion region is formed on the surface of the island region 35, and this p-type impurity diffusion region serves as the base region 36 of the lower bipolar transistor.

Next, as in the first embodiment, a cobalt layer is formed on the entire surface, and cobalt silicide layers 38 and 39 are formed in the self-line by heat treatment such as PTA. A cobalt silicide layer 38 is formed on the surface of the base region 36;
The cobalt silicide layer 39 is the collector extraction region 37
is reflected on the surface of At this time, the unreacted cobalt layer is removed by etching. Subsequently, a tungsten layer 40 for heat extraction is formed to connect to the cobalt silicide layer 38.

After shaping the tungsten layer 40 for taking out the base, a reflowable glabellar insulating film 41 is deposited on the entire surface. Openings 47 and 42 are formed in the interlayer insulating film 41 in a region where an emitter is to be formed and a region where a collector electrode is to be formed. Opening 47 is formed by removing cobalt silicide layer 38 and exposes base region 36 at its bottom. After opening these openings 47, 42, reflow is performed to smooth the shoulders of the openings. Step 5: In the opening 47 opened in the area where the ivy is to be formed, as shown in FIG. Intimidate. The sidewall portion 44 can be obtained, for example, by forming a silicon oxide film over the entire surface and etching it back. Note that a sidewall portion can also be formed on the side of the opening 42, but its illustration is omitted.

After forming the sidewall portions 44.44, as shown in FIG. 5g, an emitter region made of n-type single crystal silicon is formed on the base region 36 facing between the sidewall portions 44.44 by selective epitaxial growth. Form 45. The emitter region 45 is a sidewall portion 44.44
Since it comes into contact with the heath region 36 through the narrow spaces between the two, it becomes minute.

After forming the vine region 45, a cobalt layer 46' is formed on the entire surface, as shown in FIG. 5g. This cobalt layer 46' can be formed by, for example, sputtering.

Next, silicidation is performed by a heat treatment such as PTA, and the cobalt layer 46' is silicided in a region in contact with silicon to become a cobalt silicide layer 46. The other regions are not silicided and remain as an unreacted cobalt layer. By removing this by etching, a cobalt silicide layer 46 remaining only inside the opening 47 can be obtained as shown in FIG. 5d. Here, since the cobalt silicide layer 46 has a lattice constant close to that of silicon, the problem of unevenness occurring at the interface due to the difference in the lattice constant can be prevented even by heat treatment, and the emitter region 45 and cobalt The crystallinity between the silicide layers 46 becomes continuous.

Next, as shown in FIG. 5g, the cobalt silicide layer 4
An emitter region 48 made of an n-type single crystal silicon layer is formed on 6 by selective epitaxial growth. Here, since the cobalt silicide layer 46 has continuous crystallinity with silicon due to its lattice constant, a single crystal silicon layer can also be grown on the cobalt silicide layer 46.

Further, a tungsten layer 43 is formed in the opening 42 . This tungsten layer 43 functions as part of the collector electrode.

Next, as shown in FIG. 5f, a cobalt silicide layer 49 is again formed in a self-aligned manner on the emitter region 48 made of a single crystal silicon layer, and a tungsten layer 50 connected to this cobalt silicide layer 49 is formed. Form. These tungsten layer 50 and cobalt silicide layer 49 can lower the resistance. After forming the tungsten layer 50, an interlayer insulating film 51 is formed on the entire surface. Then, the interlayer insulating film 51 in the region where the base region is to be formed is opened to form an opening 52 so that the emitter region 48 is exposed at the bottom. Then, the emitter region 4 is formed on the side wall of this opening 52.
A sidewall portion 53 is formed to provide insulation between the substrate 8 and the base region.

The emitter region 48 exposed at the bottom of the sidewall portion 53 is made of single crystal as described above. Therefore,
As shown in FIG. 5g, a p-type single-crystal silicon layer and an n-type single-crystal silicon layer are sequentially grown to form a base region 54 made of a p-type single-crystal silicon layer and an n-type single-crystal silicon layer. Collector regions 55 each consisting of a layer can be formed. The base region 54 contacts the emitter region 48 at the bottom of the opening 52 and extends therefrom from the interlayer insulation W! It extends to the top of 51. Collector area 55 is base area 5
4, is disposed at a position shifted from the base region 54, and also extends to above the glabella insulating film 51.

Next, as shown in FIG. 5f, a glabellar insulating film 56 is formed on the entire surface. A contact hole 57 is formed above the base region 54 of the interlayer insulating film 56, and a contact hole 58 is formed above the collector region 55. After forming these contact holes 57, 5B, a cobalt layer as described above is deposited, and a cobalt silicide layer 59, 60 is formed in each contact hole 57, 5B by heat treatment.
Formed at the bottom of 8.

Thereafter, each contact hole 57.5B is filled with a tungsten layer and each electrode layer is formed to complete a bipolar transistor.

In such a bipolar transistor, two stacked transistor elements are connected by the cobalt silicide layer 46, so that crystallinity is continuous due to the lattice constant, and high-speed operation is possible. In addition, a cobalt silicide layer 38° 39.49.59.60 is provided at the lead-out portion of each electrode to reduce resistance, and a tungsten layer 40, 43, 50, etc. is also used to reduce the wiring resistance. Delays in operation due to this will be reduced.

Note that in the second embodiment, the number of stacked transistors is two, but it is also possible to stack three or more transistors. Further, the transistor to be formed may be of the opposite conductivity type, especially the cobalt silicide layer 46.
The silicon layers interconnected via the silicon layers may be of opposite conductivity types. Further, in each of the embodiments, the metal silicon layer formed is not limited to a cobalt silicide layer, but may also be a nickel silicide layer or a palladium silicide layer.

It may also be a platinum silicide layer or the like.

〔Effect of the invention〕

In the bipolar transistor of the present invention, since the lattice constant of the metal silicide layer used is close to that of a single crystal silicon substrate, its crystallinity is continuous. Therefore, it is possible to suppress harmful effects such as the occurrence of unevenness at the interface between single crystal silicon and the metal silicide layer, and improve the reliability of the device. Further, in the case where a metal silicide layer is formed between two stacked bipolar transistor elements, the crystallinity becomes continuous, so that the element can be operated at high speed.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part of an example of a bipolar transistor of the present invention, FIGS. 2a to 2f are process cross-sectional views for explaining the steps of manufacturing the above example, and FIG. 3 is a cross-sectional view of a main part of an example of a bipolar transistor of the present invention FIG. 4 is a circuit diagram of a differential amplifier to which the other example of the above bipolar transistor is applied;
FIGS. 5A to 5D are process sectional views for explaining the process of manufacturing the other example described above. 1.31... P-type silicon substrate 2.32... Buried layer 3.33... Epitaxial layer 4.34... Silicon oxide film 6.36.54... Heath region 7.37. ...Collector extraction region 8.38...Cobalt silicide layer 9.4L 51.56...Interlayer insulating film 10.44.
53... Side wall part 11.45.48... Craft ivy area 55... Collector area

Claims (2)

[Claims] (1) An element isolation region is selectively formed in a single crystal silicon substrate of a first conductivity type, and an impurity diffusion region of a second conductivity type is formed on a surface of the single crystal silicon substrate surrounded by the element isolation region. , the second
A first conductivity type impurity diffusion region is formed in contact with the second conductivity type impurity diffusion region through the conductivity type impurity diffusion region, and a surface of the second conductivity type impurity diffusion region is provided with an electrode extraction region. A bipolar transistor characterized in that a metal silicide layer is formed, and the lattice constant of the metal silicide layer is close to the lattice constant of single crystal silicon constituting the base so that the crystallinity is substantially continuous. (2) A structure in which another bipolar transistor element is stacked on a first bipolar transistor element, wherein the first bipolar transistor element is formed on a single crystal silicon substrate, and the first bipolar transistor element is in contact with the first bipolar transistor element. A metal silicide layer is formed to connect the elements, and the other monocrystalline bipolar transistor element is formed on the metal silicide layer, and the lattice constant of the metal silicide layer is the same as that of the monocrystalline transistor constituting the base. A bipolar transistor characterized by a crystallinity that is almost continuous with the lattice constant of crystalline silicon.