JPH03182951A - Bus decoder circuit - Google Patents

Abstract

PURPOSE:To supply a stable signal to a decoder part even if a bus line in inferior in transient characteristic by receiving a transmitted signal by means of a reference clock in LSI, detecting rise/fall signals and shaping a waveform through the use of the edge signals. CONSTITUTION:Cascade-connected latch circuits 103-105 transmit the output of a latch circuit 102 based on the reference clock CK. An exclusive OR circuit 106 and an AND circuit 108 output the stable rise edge signal G. The output of the exclusive OR circuit 106 is inverted in an inversion circuit 107, is supplied to a NOR circuit 109 and the stable fall edge signal H is detected. The rise edge signal G and the fall edge signal H are supplied to the set input and reset input of a flip flop circuit 113, and the output of the flip flop circuit 113 is supplied to a latch circuit 112. Thus, a decoder input signal obtained by waveform-shaping a signal A and removal of noise can be obtained in an output terminal 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the invention] (Industrial field of application) The present invention is directed to at least one integrated circuit chip (LSI
), the present invention relates to a bus decoder circuit that is used in a bus control method in which these LSIs are controlled by a microcomputer or the like through a bus line, and receives data from the bus inside the LSI.

(Prior Art) FIG. 3 shows the configuration of a conventional system that employs a bus control method. 301 is a microcomputer, and its bus line 313 connects, for example, two LSI
It is connected to 302 and 303. The bus line 313 includes a data line 310 to which addresses and data of control items are transferred, a clock line 310 to which a clock indicating the output timing of data transferred on the data line is transmitted, and an output line for these data. A period line 312 on which a signal indicating a period is transmitted is included.

LSI 302 controlled by signals on bus line 313
．． A decoder that operates using the signal obtained from the clock line 311 as a reference signal is provided inside the clock line 303 .

Based on the decoded output of this decoder, Lsl reads the address and data of the control item and performs internal processing.

However, in recent years, with the development of digital technology, the scale of systems has increased, and the number of LSIs controlled by one microcomputer has also increased.The load on the output signal of the microcomputer has increased, and the transients of the rising and falling edges of the signal have increased. is getting worse. Furthermore, due to the routing of the bus line, noise is likely to enter the bus line, causing malfunction of the decoder circuit.

Conventionally, in order to prevent the above-mentioned malfunction, the manual buffer of an LSI is provided with a hysteresis characteristic as shown in FIG. However, the hysteresis characteristic is caused by analog processing, and there is a problem in that desired characteristics cannot always be obtained due to variations in element performance during the LSI manufacturing process.

(Problems to be Solved by the Invention) As described above, when a signal transmitted through a bus line is guided to a decoder inside an LSI, transients worsen as the circuit scale increases. In order to prevent malfunctions caused by this, decoders are provided with hysteresis characteristics, but there is a problem in that it is difficult to obtain stable and always constant hysteresis characteristics due to variations in element performance.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a stable bus decoder circuit that is relatively unaffected by variations in device performance and can provide accurate decoding operations.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a decoder circuit inside at least one integrated circuit chip controlled by a control circuit through a bus line, in which a signal sent through the bus line is transferred to the integrated circuit. a latch means for receiving a reference signal inside the circuit chip; an edge signal detection means for detecting a rising edge signal and a falling edge signal of the output signal of the latch means; and the rising edge signal and the falling edge signal are supplied, The apparatus further includes synchronization means for introducing into the decoder section a signal that changes in synchronization with the rise or fall of the rising edge signal and the falling edge signal.

(Function) With the above means, the edge signal detection circuit and the synchronization means remove noise from the rising and falling edges of the signal transmitted via the bus line, shape the waveform, and introduce the signal into the decoder section. become.

Therefore, decoding processing is performed stably and malfunctions are prevented.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The input terminal 100 is supplied with a signal (here, for example, a clock signal) transmitted from the microcomputer to the LSI. Since it is a bus control system, the transient of the signal is considerably slower than the operating speed of each LSI (reference clock CK), and since it is wired as a bus line on the set, it contains noise components.

Signal A is received by a buffer circuit 101 inside the LSI. At this time, the level of signal A is
If a noise component exists when passing near the threshold voltage of , impulse-like noise N (see FIG. 2(B)) is generated. For this reason, the output of the knockoff circuit 101 is
The input signal A (FIG. 2(A)) has a waveform as shown in FIG. 2(B).

The output of the buffer circuit 101 is supplied to a circuit inside the LSI that operates based on the reference clock CK.

First, the output of the buffer circuit 101 is latched by the latch circuit 102. At this time, since there is no phase relationship between the reference clock CK and the human input signal of the latch circuit 102, an uncertain portion occurs as shown by diagonal lines in FIG. 2(C).

Next, the output of the latch circuit 102 is transmitted by the vertically connected latch circuits 103, 104, and 105 based on the reference clock CK. Therefore, each latch circuit 103.10
4. The output of 105 is (D), (E), (F) of Kō2 diagram.
become that way.

Output signals E and F of latch circuits 104 and 105 are supplied to exclusive OR circuit 10B. The exclusive OR circuit 10G detects a changing point signal (“L1 to “H” or “H” to “L”) within a clock cycle.
It is supplied to the AND circuit 108 together with the outputs C and DSE of 04. The AND circuit 10g generates a rising edge signal G that is stable at a high level "H" for several clocks (Fig. 2 (G)).
Output.

Further, the output of the exclusive OR circuit 10B is inverted by an inverting circuit 107 and supplied to a NOR circuit 109.

The NOR circuit 109 includes latch circuits 102.103.10.
4 output C5DSE is also provided.

This NOR circuit 109 generates a falling edge signal H that is stable at a low level "L" for several clocks after the human input signal changes.
(Fig. 2 (H))> is detected.

The rising edge signal G and the falling edge signal H are generated by the flip-flop circuit 1 composed of NOR circuits 110 and 111.
13 set manpower and reset manpower are supplied. The output of the flip-flop circuit 113 is supplied to the latch circuit 112. As a result, the output terminal 114 is connected to the output terminal 114 shown in FIG.
As shown in 1), it is possible to waveform-shape the signal A and obtain the decoder input signal I (FIG. 2 (■)) from which noise has been removed.

[Effects of the Invention] As explained above, according to the present invention, the signal transmitted through the bus line is received by the reference clock inside the LSI, the rising and falling edge signals are detected, and the edge signal is used to detect the rising and falling edge signals. By performing waveform shaping, a stable signal can be supplied to the decoder section even if the bus line has poor transients.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart shown to explain the operation of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing an example of a configuration using a bus control method.
FIG. 4 is a diagram showing hysteresis characteristics of a decoder provided inside a conventional LSI. 101--Buffer circuit, 102.103.104.
105.112... Latch circuit, 106... Ita cruship OR circuit, 107... Inverting circuit, 108...
...AND circuit, 109...NOR circuit, II3...
flip-flop circuit.

Claims (1)

[Scope of Claims] In a decoder circuit inside at least one integrated circuit chip controlled by a control circuit through a bus line, a latch means for receiving a signal sent through the bus line as a reference signal inside the integrated circuit chip; edge signal detecting means for detecting a rising edge signal and a falling edge signal of the output signal of the latch means, the rising edge signal and the falling edge signal being supplied, and the rising edge of the rising edge signal and the falling edge signal; or a synchronizing means for introducing a signal that changes in synchronization with a falling edge into the decoder section.