JPH03180934A - Interruption priority control system - Google Patents

Abstract

PURPOSE:To value the initial priority in accordance with interrupting frequency by successively descending the priority levels of interruption request lines whose interruption is to be permitted. CONSTITUTION:An initial value is inputted from a priority initial value setting means 2 to a storage means 1 and a comparing means 4 compares two priority levels in accordance with an interruption request from a request line. When two or more interruption request lines are included, a highest interruption permission signal generating means 5 inputs the results of plural comparing means 4, decides the line having the highest priority level and outputs a determined interruption permission signal. In the case of the interruption line permitted at present, its priority of the interruption level stored in the storage means 1 is reduced by a priority changing means 3 in order to prepare the succeeding interruption. Even in the case of requesting to value the 1st interruption and after also, the system can sufficiently correspond to the request.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method, and particularly to a method for determining and controlling interrupt priorities.

[Conventional technology]

Conventionally, with regard to this type of interrupt priority determination control, the interrupt request line for which interrupts are allowed is the one that is next given the lowest priority, or the one that is given the lowest priority. For example, the priority level is set in the order in which the interrupt request lines are arranged.

[Problem to be solved by the invention]

Among the conventional interrupt priority control methods described above, the first method is extremely simple and unitary, as the interrupt request line for which interrupts are allowed is then placed at the bottom of the line. If you want to respect the priority of the line even after the first interrupt, it has the disadvantage that it cannot be taken into consideration at all.

Second, - once the carrier priority is determined, if the priority is not changed until the next initialization, the priority does not change after the second interrupt; however, interrupt requests for lower priority lines However, a line with a high priority is always selected, and a request for a line with a low priority is easily rejected.

Third, although it is secondary, if the priority is determined only in the order in which the request lines are lined up, there is a drawback that there is no arbitrariness and no degree of freedom.

[Means to solve the problem]

The configuration of the interrupt priority control system of the present invention includes means for storing a priority level for each separate request line, and means for setting an initial value of the priority level for the storing means. means for gradually lowering the priority level of the stored priority level for the interrupt request line for which the interrupt is permitted; means for comparing the priorities of the respective priority levels for each of the interrupt request lines; [Embodiment] Next, the present invention is characterized by comprising means for determining the line with the highest priority among the requested interrupt request lines and outputting the determined interrupt permission signal. The present invention will be explained with reference to the drawings.

FIG. 1 is a schematic block diagram of one embodiment of the present invention, and FIGS. 2 and 3 are first and second embodiments of the structure shown in FIG. 1.

In FIG. 1, 1 is a storage means for storing priority levels, and 2 is a priority initial value setting means for setting an initial value to the storage means 1. At the time of initialization, the priority initial value setting means 2 The ranking level stored in is transferred to the storage means 1. Reference numeral 3 denotes a priority changing means for changing the priority of the ranking level stored in the storage means 1, which makes it possible to lower the priority of a request line for which an interrupt is permitted until the next interrupt. The lowering can be done in stages. 4 is a comparison means for comparing the priorities of each priority level, and by this, it can be determined whether any of the request lines with an arbitrary priority is the line for which an interrupt with a higher priority is requested. . Comparison means 4 is 2
Since only two levels are compared, if there are more than two levels, multiple comparing means 4 are further planned to determine the highest level line and output the determined interrupt enable signals IP1 to IP7. It has permission generation means 5.

The operation shown in FIG. 1 is as follows: First, an initial value is input into the storage means 1 from the priority initial value setting means 2, and in response to an interrupt request from the request line, the two priorities are compared by the comparison means 4. When there are more than one interrupt request line, the highest priority interrupt permission signal generation means inputs the results of the plural comparison means 4, determines the line with the highest priority, and outputs the determined interrupt permission signal. 5. The priority of the interrupt order level in the storage means 1 is lowered by the priority change procedure 3 in preparation for the next interrupt if the interrupt line is currently permitted.

FIG. 2 shows a first embodiment that embodies the configuration diagram of FIG. 1.

Referring to FIG. 1, the parts that require explanation will be mainly explained. Reference numerals 1 and 3 are shift registers, and the priority of the ranking level is changed by shifting the register value. The stored priority is
Only one bit is always “1” and all remaining bits are “1”.
The number of bits shall be equal to or greater than the number of interrupt request lines A, B, C, D, etc. When block 6 receives an interrupt request from the interrupt request line, The corresponding priority stored in the shift register is selected, and if there is no interrupt request, all 0s are output.Block 4 is a circuit that compares the magnitude of the two priorities.
First, it has EXNOR, which compares bits of the same digit.

If the values are the same, it is set as "0", and if they are different, it is set as "'1". It is possible to determine the size of the difference. Considering the upper digits, if they are different, the magnitude can be determined using that bit, so the comparison result of the lower digit bits is set to 0 by the next AND.

All comparison bits of the AND output put together in this manner go into a multi-input OR, and the output 1 is larger. In other words, the bits are compared in order from the most significant digits, and since 1 is larger among the first different bits, all other bits are output as 0 by AND. The AND output is controlled so that the bits lower than the bit where the first different bit appears are set to 0 by the 2NOR output. In other words, 1 from the multi-input OR with higher priority.
is output, and 0 is output from the smaller one.

The comparing means 5 which judges the highest interrupt level receives the result from the comparing means 4, selects with a selector so as to send the ranking level value determined to be high by the comparing means 4 to the next stage, and compares with the comparing means 4. Enter the same block. By comparison means 5,
A highest order can be determined for those with more than two interrupt lines. As a result, the interrupt enable signal I P
Get +~4.

The value of the priority register 1 for the interrupt line enabled at this time is lowered in level by 1/2 by bit shifting.

FIG. 3 shows a second embodiment. This embodiment is simply a result of replacing block 4 in the first embodiment with block 7, but the ALU 9 subtracts the priority levels,
Kiya obtained by this! The J-CY result is used to determine the highest priority level.

〔Effect of the invention〕

As explained above, in the present invention, by gradually lowering the priority level for the interrupt request line for which interrupts are enabled, the initial priority level can be respected according to the number of interrupts, and if the number of interrupts increases, the priority level can be lowered step by step. By making it easier to accept requests for lines with lower priority levels, and by having a means for setting the initial value of the priority level, it is possible to freely and arbitrarily set the priority level for each interrupt line. .

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram of one embodiment of the present invention, Fig. 2 is a diagram for explaining the first embodiment including a specific circuit, and Fig. 3 is a part of the first embodiment. FIG. 4 is a diagram showing a second embodiment in which the . 1... Storage means, 2... Priority initial value setting means, 3... Priority changing means, 4...
・Comparison means, 5゜8...Highest level interrupt permission signal generation means, 6...Circuit that judges the presence or absence of an interrupt request and sends the priority or all pins) O to the next stage, 7. ...Block when ALU subtraction is used for priority comparison 4, 9...ALU that can perform subtraction.

Claims (1)

[Claims] A means for storing a priority level for each interrupt request line, a means for setting an initial value of the priority level for the storing means, and a means for storing a priority level for each interrupt request line for which interrupts are permitted. means for gradually lowering the priority of the priority level of the interrupt request line; means for comparing the priorities of the respective priority levels for each of the interrupt request lines; An interrupt priority control method comprising means for determining the highest line and outputting a determined interrupt permission signal.