JPH0318041A - Electric junction part - Google Patents

Electric junction part

Info

Publication number
JPH0318041A
JPH0318041A JP1150373A JP15037389A JPH0318041A JP H0318041 A JPH0318041 A JP H0318041A JP 1150373 A JP1150373 A JP 1150373A JP 15037389 A JP15037389 A JP 15037389A JP H0318041 A JPH0318041 A JP H0318041A
Authority
JP
Japan
Prior art keywords
solder
electrodes
electrode
grains
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1150373A
Other languages
Japanese (ja)
Other versions
JPH07118498B2 (en
Inventor
Tetsuya Hashimoto
哲也 橋本
Kaoru Omura
馨 大村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP1150373A priority Critical patent/JPH07118498B2/en
Publication of JPH0318041A publication Critical patent/JPH0318041A/en
Publication of JPH07118498B2 publication Critical patent/JPH07118498B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve stability of re-reflow by connecting electrodes therebetween with solder containing a plurality of metal particles so that the melting point of the particle is higher than that of the solder and all or part of the material of the particle contain a different material from that of the solder. CONSTITUTION:A substrate 11 is formed of an electrode 1 provided on an insulator 4, an electrode 2 provided on a chip component 3, the component 3 and the insulator 4 together with the electrode 1. A solder 5 for connecting the electrodes 1, 2 and electrically conducting them, metal particles 6 dispersed in the solder 5, and a support 9 for securing the component 3 to the insulator 4 are provided. The melting point of the particles 6 is higher than that of the solder 5, and all or part of the material of the particle 6 contains a different material from that of the solder 5. Thus, a thin mounting state of high reliability for re-reflow can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁体上に設けられた電極とチップ部品また
はペアチップとの電気的接合に関し、特に生産性および
信頼性に優れた電気的接合部に関するものである。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an electrical connection between an electrode provided on an insulator and a chip component or a pair of chips, and in particular to an electrical connection with excellent productivity and reliability. This is related to the department.

〔従来の技術〕[Conventional technology]

従来、プリント基板等にチップ部品を実装する場合、実
装厚みを薄くするためにモールドパ・ンケジされた部品
を部品挿入用の孔に埋め込みチップ部品のリードとプリ
ント基板の電極をはんだリフロー法により接続していた
。この方法によりチップ部品の実装上の厚みがプリント
基板により一部相殺され通常の表面実装法に比べ薄くで
きるメリットがあった。しかしながらリードがあるため
にこの分が出っぱりとして残り、より薄い実装形熊を得
るには限界があった。
Conventionally, when mounting chip components on a printed circuit board, etc., in order to reduce the mounting thickness, a molded packaged component was embedded in the component insertion hole and the leads of the chip component and the electrodes of the printed circuit board were connected using the solder reflow method. was. This method has the advantage that the mounting thickness of the chip components is partially offset by the printed circuit board, making it thinner than the normal surface mounting method. However, because of the lead, this portion remained as a protrusion, and there was a limit to obtaining a thinner mounted bear.

そこで、外部接続用の電極を表而に設け、リードをなく
したペアチップ部品をプリント基坂に埋め込み、ペアチ
ップとプリント基板上の電極を間一平面に保ちはんだフ
ロー法によって接続することによりリード部の厚みによ
る出っぱりが仰えられ薄く実装することができる。しか
しながら、この方法の場合、ペアチップとプリント基板
上の電極の間にギャップがあるために、通常の共晶系は
んだペーストを使用する場合、ギャップを充分小さくせ
ざるを得す、ペアチップの挿入に高い位置精度が要求さ
れ、しかも接続したものの再リフロ一に対する信頼性は
低い。はんだの代わりに導電性接着剤を用いる方法もあ
るが、接触抵抗、信頼性、更にコストの点で一般にはん
だより劣り適用できる範囲は限定されている。
Therefore, by providing electrodes for external connection on the surface, embedding the paired chip components without leads in the printed circuit board, and keeping the paired chips and the electrodes on the printed circuit board on the same plane, they are connected using the solder flow method. It can be mounted thinly due to its protrusion due to its thickness. However, in this method, there is a gap between the paired chips and the electrodes on the printed circuit board, so if normal eutectic solder paste is used, the gap must be made sufficiently small, and it is expensive to insert the paired chips. Positional accuracy is required, and even if it is connected, it has low reliability when reflowing. Although there is a method of using a conductive adhesive instead of solder, it is generally inferior to solder in terms of contact resistance, reliability, and cost, and its applicability is limited.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のペアチップ実装法では製造条件にシビアな管理が
要求され、再リフローに対する信頼性に劣り、また接触
抵抗、コストなどの点から適用分野に制限を受けていた
Conventional paired chip mounting methods require strict control of manufacturing conditions, have poor reliability against reflow, and are limited in the fields of application due to contact resistance, cost, etc.

本発明の目的は、このような従来の諸欠点を解消し、特
にペアチップの高い位置精度を必要とせず、接触抵抗、
コストが通常のはんだと同等以上の性能をもち、薄くか
つ再リフローに対する信頼性の高い実装形態を実現する
電気的接合部を提供することにある。
The purpose of the present invention is to eliminate such conventional drawbacks, eliminate the need for particularly high positional accuracy of paired chips, reduce contact resistance,
The object of the present invention is to provide an electrical joint that has performance equivalent to or higher than that of ordinary solder, is thin, and realizes a highly reliable mounting form for reflow.

更に、本発明を通常の表面実装法に適用すればはんだ量
のバラツキによる第6図、第7図のようなチップ立ちが
少なくなり、製造条件の管理が容易になり、また接合部
の再リフロー後の信頼性向上が達成されることを見出し
、本発明を完威した。
Furthermore, if the present invention is applied to a normal surface mounting method, chip standing as shown in Figures 6 and 7 due to variations in solder amount will be reduced, manufacturing conditions will be easier to manage, and reflow of the joint will be reduced. It was discovered that subsequent reliability improvements could be achieved, and the present invention was perfected.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、絶縁体上に設けられた複数の電極とチップ部
品上に設けられた複数の電極が独立に電気的に接続され
た電気的接合部において、前記電極間が複数の金属粒を
含むはんだで接続され、かつ前記複数の金属粒の融点が
前記はんだより高く、かつ前記複数の金属粒の構成材質
の全部または一部に前記はんだの構威材質と異なる材質
を含むことを特徴とする電気的接合部である。
The present invention provides an electrical junction in which a plurality of electrodes provided on an insulator and a plurality of electrodes provided on a chip component are independently electrically connected, and a plurality of metal grains are included between the electrodes. The plurality of metal particles are connected by solder, and the melting point of the plurality of metal particles is higher than that of the solder, and all or part of the constituent material of the plurality of metal particles includes a material different from the constituent material of the solder. It is an electrical connection.

本発明に適用されるチップ部品とは、ホール素子、トラ
ンジスタ、ICなどの能動素子や抵抗、コンデンサ、イ
ンダクタなどの受動素子から成り、その外観は外部接続
用の電極を設けたペアチップ形態や主要構成素子をモー
ルド材などでパッケージ化し外部接続用のリード線を設
けた形態などがある。このうち本発明が特に威力を発揮
するのは前者のペアチップ形態であり、その電極ははん
だ付け性の良い材料で構成されており、チップの表面に
平面あるいは曲面的に形成されている。
The chip components applied to the present invention consist of active elements such as Hall elements, transistors, and ICs, and passive elements such as resistors, capacitors, and inductors. There is a form in which the element is packaged with a molding material or the like and lead wires are provided for external connection. Among these, the present invention is particularly effective in the former pair chip form, in which the electrodes are made of a material with good solderability and are formed flat or curved on the surface of the chip.

チップ部品を接続する相手側の電極は、チップ部品の周
囲の回一平面あるいは段差を持った位置やチップ部品と
向かい合う位置に形威されており、かつ樹脂やセラミ・
冫クを含む絶縁体上に形成されている. 接続するはんだ材料は、はんだ中に高融点金属粒を含む
ものである。
The electrode on the other side to which the chip component is connected is formed on a flat surface around the chip component, in a stepped position, or in a position facing the chip component, and is made of resin, ceramic, etc.
It is formed on an insulator that contains chemicals. The connecting solder material contains high melting point metal grains in the solder.

以下、圓面を参照して本発明を詳細に説明する。Hereinafter, the present invention will be described in detail with reference to a circular plane.

第1図は、本発明の電気的接合部の一実施態様を示す断
面図である。第11fiにおいて、lは絶縁体4に設け
られた電極、2はチップ部品3に設けられた電極、3は
チップ部品、4は絶縁体で電極lと共に基板11を形威
している。この基板l1は少なくとも1組の絶縁体4と
電極lを含んでいれば、更に他の層が積層されていても
かまわない。5は電極lと2を接続し電気的に導通させ
るはんだ、6ははんだ5内に分散された金属粒、9はチ
ップ部品3を絶縁体4に固定する支持体を示す.電極!
、2の材質は、はんだ5との濡れ性がよいことが必要で
ある。実際には、電極との濡れ性のよいはんだを選択す
ることにより、銅、銀、金、白金、鉛、錫、鉄、ニッケ
ル、インジウム、アルミニウム、ステンレスが使用でき
るが、−i的には、銅、銀、金が好ましく、経済性の点
からは特に銅が好ましい. 電極lおよび2はいかなる方法によって製造されたもの
であってもよく、電極の個数も2つのみに限らず、3つ
以上であってもよいこと勿論である.加えて、電極lお
よび2の配置形態も、第1図の例にのみ限られるもので
はなく、たとえば第2図(A)〜(D)に示すような種
々の形態にも適用可能である.第2図(D)において、
2′は第3の電極を示す。
FIG. 1 is a cross-sectional view showing one embodiment of the electrical connection part of the present invention. In the 11th fi, l is an electrode provided on the insulator 4, 2 is an electrode provided on the chip component 3, 3 is the chip component, and 4 is an insulator, which forms the substrate 11 together with the electrode l. As long as this substrate l1 includes at least one set of insulator 4 and electrode l, other layers may be laminated thereon. Reference numeral 5 indicates a solder that connects the electrodes 1 and 2 to make them electrically conductive, 6 indicates metal particles dispersed within the solder 5, and 9 indicates a support for fixing the chip component 3 to the insulator 4. electrode!
, 2 need to have good wettability with the solder 5. In reality, copper, silver, gold, platinum, lead, tin, iron, nickel, indium, aluminum, and stainless steel can be used by selecting a solder that has good wettability with the electrode. Copper, silver, and gold are preferred, and copper is particularly preferred from the economic point of view. It goes without saying that the electrodes 1 and 2 may be manufactured by any method, and the number of electrodes is not limited to two, but may be three or more. In addition, the arrangement of the electrodes 1 and 2 is not limited to the example shown in FIG. 1, but can also be applied to various forms as shown in FIGS. 2(A) to 2(D), for example. In Figure 2 (D),
2' indicates the third electrode.

電極1と電極2との間の距離については、電極の形状や
塗布はんだの量などにもよるが、それらの最短距離が、
0.05mm以上、さらには0.1M以上、特に0.3
嗣以上の場合において、本発明はその効果を顕著に発揮
する。
The distance between electrode 1 and electrode 2 depends on the shape of the electrode and the amount of solder applied, but the shortest distance between them is
0.05mm or more, even 0.1M or more, especially 0.3
In the case of more than one child, the present invention exhibits its effects significantly.

なお、接続方向に垂直な方向の電極の寸法(電極幅と定
義する)は、電極間最短V巨離が大きくなるにつれ、そ
の最短距離の4倍以下、さらには2倍以下、特に1倍以
下で本発明の効果を顕著に発揮する。
The dimension of the electrode in the direction perpendicular to the connection direction (defined as electrode width) should be 4 times or less, further 2 times or less, and especially 1 time or less as the shortest V distance between the electrodes increases. The effects of the present invention are significantly exhibited.

はんだ5の材質としては、電極及び金属粒と合金組織を
形戒が可能であれば任意のもので良く共晶系、非共品系
いずれも使用できる。例えば電極及び金属粒が銅の場合
、すずを含む合金、特にSn−Pb合金が接合力も高く
好ましい。また電極が恨の場合にはSn−Pb−Ag合
金も使用可能である。
The material of the solder 5 may be any material as long as it can form an alloy structure with the electrodes and metal grains, and both eutectic and non-eutectic materials can be used. For example, when the electrodes and metal grains are made of copper, alloys containing tin, particularly Sn--Pb alloys, are preferred because of their high bonding strength. Furthermore, if the electrode is not suitable, a Sn-Pb-Ag alloy can also be used.

なお、本発明でいうはんだとは電極及び金属粒と合金組
織を形威可能な金属を含む合金を意味する。
Note that the term "solder" as used in the present invention means an alloy containing a metal that can form an alloy structure with electrodes and metal grains.

金属粒6としては、はんだ5の園相線温度よりも高い融
点を持つことが必要であり、その温度は20゜C以上、
好ましくは35゛C以上、更に好ましくは5 Q ’C
以上である。また、再リフローに対する安定性を確保す
るためには、その再リフロー温度より金属粒6の融点を
高く設定するのが好ましく、更に金属粒の構成材質の全
部または一部にはんだ5の構成材質以外のものを含むこ
ともできる。
The metal particles 6 need to have a melting point higher than the phase line temperature of the solder 5, and the temperature is 20°C or higher,
Preferably 35°C or higher, more preferably 5Q'C
That's all. In addition, in order to ensure stability against reflow, it is preferable to set the melting point of the metal grains 6 higher than the reflow temperature, and furthermore, all or part of the constituent material of the metal grains is made of a material other than the constituent material of the solder 5. It can also include things like

上記の条件を満たし更にはんだ5との濡れ性が良く合金
組織を形戒可能なものとしては、Ag+ Au,Cu,
Pt,Ni,Fe,Aj!,Cd,Zn及び上記1種以
上の金属を含む合金など使用できる。また、上記のうち
いずれかを含む金属で表面を覆った金属粒、ガラス粒、
セラξツク粒、樹脂粒を使用しても良いし、2種以上の
材質の金属粒を同時に使用しても良い。以上のうちでは
、Ag,Au,Cu,Pt,Ni及びCu基合金、Au
g合金、Ag基合金、Ni 75合金、及び上記金属で
表面を覆った金属粒などが好ましく、更にはAu.Ag
.Niの単独または表面をAu,Ag+Ni,Snのう
ちのいずれかの金属あるいは合金で覆った銅粒が好まし
い。
Ag+Au, Cu,
Pt, Ni, Fe, Aj! , Cd, Zn, and alloys containing one or more of the above metals. In addition, metal grains, glass grains whose surfaces are covered with metals containing any of the above,
Ceramic grains or resin grains may be used, or metal grains of two or more materials may be used at the same time. Among the above, Ag, Au, Cu, Pt, Ni and Cu-based alloys, Au
g alloy, Ag-based alloy, Ni 75 alloy, and metal grains whose surfaces are covered with the above-mentioned metals are preferable, and furthermore, Au. Ag
.. Copper grains made of Ni alone or whose surfaces are covered with any metal or alloy of Au, Ag+Ni, and Sn are preferred.

金属粒の粒径は、接合の信頼性、プロセス性などを考え
ると1〜150μm、好ましくは1〜75μm、更に好
ましくは1〜50llm程度である。
The particle size of the metal particles is approximately 1 to 150 μm, preferably 1 to 75 μm, and more preferably 1 to 50 μm, considering bonding reliability and processability.

形状は、球形より不定形の方がはんだとの界面面積が大
きくとれ信頼性上好ましい。
Regarding the shape, an amorphous shape is preferable to a spherical shape because it allows a larger interface area with the solder and is therefore preferable in terms of reliability.

金属粒の量については、多すぎると金属粒間にはんだが
充満できず接続抵抗の上昇や信頼性低下となり、少なす
ぎると接続の歩留まりが劣り、また本発明で接続した部
品等をはんだリフロ一法により別の基板等に接続する際
に、そのリフロー熱によるはんだの再溶融により、接続
部が断線する場合もある。具体的には体積比で、金属粒
/(金属粒+はんだ)の値が0.5 Vol%以上67
%Voffi%以下、2 Vol%以上50Vol%以
下が好ましく、特に5 Vol%以上20VOl%以下
が好ましい。
Regarding the amount of metal particles, if the amount of metal particles is too large, the solder cannot fill between the metal particles, resulting in an increase in connection resistance and a decrease in reliability.If the amount is too small, the yield of the connection will be poor, and the parts connected by the present invention may not be solder reflow solder. When the solder is connected to another board or the like by the method, the solder may be remelted due to the reflow heat, and the connection may be disconnected. Specifically, in terms of volume ratio, the value of metal grains/(metal grains + solder) is 0.5 Vol% or more67
%Voffi% or less, preferably 2 Vol% or more and 50 Vol% or less, particularly preferably 5 Vol% or more and 20 Vol% or less.

上記の金属粒量であれば、接続部のはんだを再溶融させ
てもその中に分散されている金属粒により流動性が抑え
られるため接続が断線することはない。
With the above amount of metal particles, even if the solder at the connection part is remelted, the metal particles dispersed therein will suppress fluidity, so the connection will not break.

第1圓及び第2図に示した電気的接合部を得る方法を第
3図(A) 、(B)および(C)を参照して説明する
A method for obtaining the electrical connections shown in FIG. 1 and FIG. 2 will be explained with reference to FIGS. 3(A), (B) and (C).

工程(1):  第3図(A)に示すように、はんだ粒
5A、金属粒6およびフラックス7を 混合したはんだペーストをスクリーン 印刷法その他の方法によって電極1お よび2の上に、これら電極にまたがる ように被着、すなわち付着または塗布 する。
Step (1): As shown in FIG. 3(A), a solder paste containing a mixture of solder grains 5A, metal grains 6 and flux 7 is applied onto electrodes 1 and 2 by screen printing or other methods. Adhere to, that is, adhere or apply in a straddling manner.

工程(2):  はんだ粒5A園相線未満の温度で予備
加熱した後、はんだ粒5Aの同相線 以上かつ金属粒6の融点未満の温度で、はんだペースト
をリフローさせてから 冷却して凝固させる。この工程によっ て、はんだ粒5Aは熔融して合体して、溶融していない
金属粒6を分散させ、 また、接合部の表面にははんだペース ト中のフラックスから生成された残留 物が残る。このようにリフローしたは んだは冷却凝固して第3図(B)に示すように、電極l
と2との間を電気的に 導通させるはんだ5、金属粒6及びフ ラックス残留物8となる。
Step (2): After preheating at a temperature below the phase line of the solder grains 5A, the solder paste is reflowed at a temperature above the in-phase line of the solder grains 5A and below the melting point of the metal grains 6, and then cooled and solidified. . Through this process, the solder grains 5A melt and coalesce, and the unmelted metal grains 6 are dispersed, and a residue generated from the flux in the solder paste remains on the surface of the joint. The reflowed solder is cooled and solidified to form an electrode as shown in Figure 3(B).
The solder 5, metal grains 6, and flux residue 8 provide electrical continuity between and 2.

工程(3):  その後、第31m(B)に示されるフ
ラックス残留物を除去して第3図(C)に示す如き電気
的接合部を得る。
Step (3): Thereafter, the flux residue shown in No. 31m (B) is removed to obtain an electrical joint as shown in FIG. 3(C).

このようにして得られた電気的接合部は、その製造工程
が簡単であるにもかかわらず、リフロ一時に発生するガ
スやはんだ自体の表面張力による盛り上がりの高さによ
る導通不良を生ずることがなく、電極間を確実に電気的
に接合して両電極間の電気的導通をとることができる。
Although the manufacturing process is simple, the electrical joints obtained in this way do not cause conduction defects due to the height of the swelling caused by the gas generated during reflow or the surface tension of the solder itself. , it is possible to reliably electrically connect the electrodes and establish electrical continuity between the two electrodes.

しかもまた、電極とはんだとの接合強度が高く、また接
合部の比抵抗を著しく低くすることができる.更に従来
のものに較べて再リフローに対する信頼性が高くなる。
Furthermore, the bonding strength between the electrode and the solder is high, and the specific resistance of the bonded portion can be significantly lowered. Furthermore, the reliability with respect to reflow is higher than that of the conventional one.

また、はんだブリッジによる導通は、リフロー工程の初
期のある期間内で少なくとも一部が溶融したはんだが残
りの金属粒同士を合体させることにより起こり、通常の
電極の形状配置の下では、いったん電極間のはんだブリ
ッジが起これば、その後完全にはんだを溶融させた状態
にしても、また、その後に冷却凝固させても、はんだブ
リッジは保たれる。すなわち、電極の寸法や位置関係な
どによる規制はあるものの、基本的には、上述のりフロ
ー温度条件を満足する限り、用いるはんだ粒の固相線一
金属粒の融点間および金属粒の融点以上のいずれの温度
でリフローさせてもよい.はんだ粒5Aの粒径は、はん
だペーストの印刷・塗布性を考慮すると、15μm以下
、さらには7・5μm以下が好ましい。また、粘度偏折
を避けるためには、均一の粒径のものを使用した方が好
ましい。
In addition, conduction due to solder bridges occurs when the solder, which is at least partially melted, coalesces with the remaining metal grains during a certain period at the beginning of the reflow process. Once a solder bridge occurs, the solder bridge will be maintained even if the solder is completely molten or subsequently cooled and solidified. In other words, although there are restrictions depending on the dimensions and positional relationship of the electrodes, basically, as long as the above-mentioned solder flow temperature conditions are satisfied, the temperature between the solidus line of the solder grains used and the melting point of the metal grains and above the melting point of the metal grains is basically the same. It can be reflowed at any temperature. The particle size of the solder particles 5A is preferably 15 μm or less, more preferably 7.5 μm or less, considering the printing and coating properties of the solder paste. Furthermore, in order to avoid viscosity deviation, it is preferable to use particles with a uniform particle size.

フラ・ンクス7としては、樹脂系フラックス、特に活性
化樹脂ブラックスが好ましい。これはロジン系天然樹脂
またはその変性樹脂を主成分とし、これに活性剤・有機
溶剤・粘度調整剤・その他の添加剤が添加されたもので
ある。一般に、変性樹脂には重合ロジン、フェノール樹
脂変性ロジンなと、活性剤には無機系および有機系フラ
ックス、その中でも特にアミン塩酸塩や有機酸系のフラ
ンクス、有機溶剤はカルビトール系、エーテル系のもの
が用いられる.なお、金属粒の種類によっては無機系フ
ラックスを使用してもよい。
As the flux 7, resin-based flux, particularly activated resin blacks, is preferable. The main component is a rosin-based natural resin or a modified resin thereof, to which an activator, an organic solvent, a viscosity modifier, and other additives are added. In general, modified resins include polymerized rosin and phenolic resin-modified rosin, activators include inorganic and organic fluxes, especially amine hydrochloride and organic acid-based fluxes, and organic solvents include carbitol-based and ether-based fluxes. things are used. Note that an inorganic flux may be used depending on the type of metal particles.

フラックス量については、リフローしたはんだ粒問およ
びはんだ粒一金属粒間の一体化を引き起こすのに充分な
量が必要であるが、例えば金属粒が銅の場合には、はん
だ粒の5重量%以上、好ましくは7重量%以上、さらに
は10ml%以上が好ましい。なお、フラックス量は金
属粒量の割合が増すに従って、印刷・塗布性が劣らない
範囲で増やす必要がある。
The amount of flux required is sufficient to cause integration between reflowed solder grains and between solder grains and metal grains, but for example, if the metal grains are copper, the flux should be 5% by weight or more of the solder grains. , preferably 7% by weight or more, more preferably 10ml% or more. Incidentally, as the proportion of metal particles increases, the amount of flux needs to be increased within a range that does not deteriorate printing and coating properties.

上述のはんだ粒5A,金属粒6およびフラックス7で構
成されたはんだペーストは、スクリーン印刷法あるいは
ディスペンサなどを用いた方法により電極部に付着ある
いは塗布される。付着または塗布は第3図(A)に示し
たように、接続しようとする電極1および2のすべての
上にまたがるように行う必要がある. 予備加熱は、リフロー時の急激な温度上昇による基板へ
の熱応力を緩和するためと同時に、フランクス中の揮発
成分を完全に放散させてリフロ時のガス発住を抑える効
果があり、かかる予備加熱を行うことが好ましい。予備
加熱の条件は基板の材質や構造などによって異なるが、
はんだの融点よりも低い温度、より好ましくははんだの
融点よりも20゛C〜60’C低い温度とする。例えば
、Sn: Pb=63:37の組成のはんだ(共品はん
だ)の場合には、温度1 2 0 ’C〜1 6 0 
’Cで予備加熱することが好ましい。これより高すぎる
と、フラックスが硬化し、はんだ付着性が悪くなり、逆
に低すぎると、フランクスの揮発成分の放散が不充分で
ガスの滞留を起こし、はんだ不濡れの原因となる。加熱
時間も基板の熱容量、はんだペーストの量、フラックス
の量や種類、加熱方式などにより異なるが、基板の表面
および内部が規定の温度に達してから1〜3分間程度の
間にわたって予備加熱することが好ましい。
The solder paste composed of the solder particles 5A, metal particles 6, and flux 7 described above is attached or applied to the electrode portion by a screen printing method or a method using a dispenser. As shown in FIG. 3(A), the adhesion or coating must be carried out so as to cover all of the electrodes 1 and 2 to be connected. Preheating is used to alleviate the thermal stress on the substrate due to the rapid temperature rise during reflow, and at the same time has the effect of completely dissipating the volatile components in Franks and suppressing the generation of gas during reflow. It is preferable to do this. Preheating conditions vary depending on the material and structure of the board, but
The temperature is lower than the melting point of the solder, preferably 20°C to 60°C lower than the melting point of the solder. For example, in the case of solder with a composition of Sn:Pb=63:37 (common solder), the temperature is 120'C to 160C.
It is preferable to preheat at 'C. If it is too high, the flux will harden and the solder adhesion will deteriorate, and if it is too low, the volatile components of the flux will not be sufficiently dissipated, causing gas retention and causing solder non-wetting. The heating time also varies depending on the heat capacity of the board, the amount of solder paste, the amount and type of flux, the heating method, etc., but preheating should be performed for about 1 to 3 minutes after the surface and inside of the board reach the specified temperature. is preferred.

フロー温度は、接合強度の点から、はんだの融点よりも
5゜C以上高い温度とする。さらには2o゜C以上高い
温度とするのが好ましい。上限温度は基板の耐熱性によ
って定められるが、あまり高ずぎると、フラックスが炭
化して活性作用がなくなるので、注意が必要である。時
間の設定は予備加熱の場合と同様であるが、数秒以上あ
ればよい。
From the viewpoint of bonding strength, the flow temperature is set to be at least 5°C higher than the melting point of the solder. Furthermore, it is preferable to set the temperature to a temperature higher than 2°C. The upper limit temperature is determined by the heat resistance of the substrate, but care must be taken because if it is too high, the flux will carbonize and lose its activation effect. The time setting is the same as in the case of preheating, but a few seconds or more is sufficient.

加熱方法としては、熱風加熱、赤外線加熱、ペパーフエ
ーズソルダリング、レーザー加熱、ホットプレート、抵
抗加熱、はんだごて加熱などがあるが、より高い導通の
再現性を得るためには、はんだが溶融し始めてから、リ
フローのピーク温度に達するまでの昇温速度は遅い方が
好ましく、熱風加熱や赤外線加熱が特に好ましい。
Heating methods include hot air heating, infrared heating, pepper phase soldering, laser heating, hot plate, resistance heating, and soldering iron heating, but in order to obtain higher continuity reproducibility, it is necessary to melt the solder. The rate of temperature increase from the start of reflow to the peak temperature of reflow is preferably slow, and hot air heating or infrared heating is particularly preferable.

リフロー後、たとえば第3図(B)に示すように、はん
だ5、チップ部品3及び絶縁体4の表面にフラックス残
留物8が生戒されるが、その除去のために、必要に応じ
て洗浄を行う。洗浄剤として、トリクロロトリフルオ口
エタンに代表されるフロン系溶剤や1−l−1 トリク
ロルエタンなどの塩素系溶剤を用いてシャワー洗浄・超
音波洗浄や蒸気洗浄などを行えばよい。
After reflow, flux residue 8 is left on the surfaces of the solder 5, chip component 3, and insulator 4, as shown in FIG. 3(B), but to remove it, cleaning is necessary. I do. Shower cleaning, ultrasonic cleaning, steam cleaning, etc. may be performed using a chlorofluorocarbon solvent such as trichlorotrifluoroethane or a chlorine solvent such as 1-1-1 trichloroethane as a cleaning agent.

〔実施例〕〔Example〕

次に、本発明を実施例により詳述するが、本発明はかか
る実施例にのみ限定されるものではない.実施例l 既知の方法によって、第1図及び第4図に示すように基
板l1にチップ部品3を埋め込み、電極1及びチップ部
品の電極2を同一平面上に形威した(電極l及び2の寸
法は各々0.3mm X 0.3mm X 0.03I
IIIlt、0.2mmX0.2mmX0.03mmt
)。lの値としては250μm、800μmの2通りの
ものを用意した。
Next, the present invention will be explained in detail with reference to examples, but the present invention is not limited only to these examples. Example 1 By a known method, a chip component 3 was embedded in a substrate 11 as shown in FIGS. 1 and 4, and an electrode 1 and an electrode 2 of the chip component were formed on the same plane ( Dimensions are 0.3mm x 0.3mm x 0.03I each
IIIlt, 0.2mmX0.2mmX0.03mmt
). Two values of l were prepared: 250 μm and 800 μm.

次に、メタルマスクを用いたスクリーン印刷法によって
、各々のiのものに対し、下記組成よりなるはんだペー
ストのを2つの電極工および2上に、これら電極にまた
がって塗布した。
Next, by screen printing using a metal mask, a solder paste having the following composition was applied onto the two electrodes and 2 so as to straddle these electrodes.

はんだペーストの はんだ粒材質  Sn/Pb/Ag= 62/36/2
はんだ粒径   最高40μm はんだ粒形状  不定形 金属粒材質   銀 金属粒径    最高40am 金属粒形状   不定形 フラックス   弱活性口ジン 混合比     (体積比) (はんだ粒):(金属粒):(フラックス)=90 :
 10 : 105 その後、1 2 0 ”Cの熱風オーブン中で10分間
予備加熱した後、215゜C熱風オーブン中で3分間リ
フローさせ、ついで1−1−1 }リクロルエタンで超
音波洗浄して表面のフランクス残留物を除去して第3図
(C)の如き電気的接合部を製造した。
Solder grain material of solder paste Sn/Pb/Ag= 62/36/2
Solder particle size Max. 40 μm Solder particle shape Irregular metal particle material Silver metal particle size Max. 40 am Metal particle shape Irregular flux Weakly activated flux Mixing ratio (volume ratio) (Solder particles): (Metal particles): (Flux) = 90 :
10: 105 Thereafter, after preheating in a hot air oven at 120"C for 10 minutes, reflowing in a hot air oven at 215°C for 3 minutes, and then ultrasonically cleaning with 1-1-1} dichloroethane to clean the surface. The Franks residue was removed to produce an electrical joint as shown in FIG. 3(C).

得られた接合部はいずれの電極配置においても、リフロ
ーしたはんだはほぼ100%の収率で第3lm (C)
に示すように2電極間にまたがるようにプリッジされて
おり、接合強度も通常のはんだと比べて何ら遜色はなか
った。また、230″C×30secの条件で再リフロ
ーしたところ接続部の断線の発生はみられなかった。
The resulting joints were reflowed with almost 100% yield in the 3rd lm (C) for both electrode configurations.
As shown in Figure 2, the solder was bridged across two electrodes, and the bonding strength was no inferior to that of normal solder. Further, when reflowing was performed under the conditions of 230″C x 30 seconds, no breakage of the connection portion was observed.

実施例2 既知の方法によって、第5図に示すように基板ll上に
チップ部品3を設置し、電極lとチップ部品の電極2に
150μmの段差を設けた。電極l及び2の寸法は実施
例1と同様であった。
Example 2 By a known method, a chip component 3 was placed on a substrate 11 as shown in FIG. 5, and a step of 150 μm was provided between the electrode 1 and the electrode 2 of the chip component. The dimensions of electrodes 1 and 2 were the same as in Example 1.

次に実施例1で用いた、はんだペーストのを2つの電極
1および2上にまたがるように塗布した.その後、12
0゜Cの熱風オーブン中で10分間予備加熱した後、2
15゜Cの熱風オーブン中で3分間リフローさせ、つい
で1−1−1 }リクロルエタンで超音波洗浄して表面
のフランクス残留物を除去して第21m(A)の如き電
気的接合部を得た。
Next, the solder paste used in Example 1 was applied so as to span over the two electrodes 1 and 2. After that, 12
After preheating in a hot air oven at 0°C for 10 minutes,
It was reflowed in a hot air oven at 15°C for 3 minutes, and then ultrasonically cleaned with 1-1-1}lichloroethane to remove Franks residue on the surface to obtain an electrical joint as shown in No. 21m(A). .

得られた接合部は、リフローしたはんだがほぼ100%
の収率で第2図(A)のように2電極間にまたがるよう
にブリッジされており、接合強度も通常のはんだと比べ
て何ら遜色はなかった。なお、230″CX30sec
の条件で再リフローしたところ接続部の断線の発生はみ
られなかった。
The resulting joint is almost 100% reflowed solder.
As shown in FIG. 2(A), the solder was bridged across the two electrodes with a yield of 100%, and the bonding strength was no inferior to that of ordinary solder. In addition, 230″CX30sec
When reflowed under these conditions, no breakage of the connection was observed.

比較例1 実施例1で使用したはんだペースト■の代わりにSn/
Pb=63/37合金のはんだペースト(千住金属工業
■製、商品名; SPT−55−63)を用いる以外は
、実施例I及び2と全く同様にして電気的接合部を得た
。得られた接合部は2電極間にまたがるようにブリッジ
されているものは、第4図の形態では5%以下、第5図
の形態では0%であった。
Comparative Example 1 Sn/
An electrical joint was obtained in exactly the same manner as in Examples I and 2, except that a solder paste of Pb=63/37 alloy (manufactured by Senju Metal Industry ■, trade name: SPT-55-63) was used. The number of the resulting joints that were bridged so as to span two electrodes was less than 5% in the form of FIG. 4, and 0% in the form of FIG. 5.

実施例3 チップ部品を接続しようとする基板上に配設された4つ
の電極( 0.2mm X 0.2mm X 0.03
+um t)に実施例1で使用したペーストのを塗布し
た。塗布量は4つの電極のうちの1点を他の同じ塗布量
の3点の半分の量に設置した。その後サイズ、位置とも
基板上の電極と同様の電極をもったチップ部品を電極間
が向かい合うようにセットし7た。
Example 3 Four electrodes (0.2 mm x 0.2 mm x 0.03
+um t) of the paste used in Example 1 was applied. The amount of coating was set at one point of the four electrodes to be half the amount of the other three points having the same amount of coating. Thereafter, chip components having electrodes similar in size and position to those on the substrate were set 7 so that the electrodes faced each other.

その後、1 2 0 ”Cの熱風オーブン中で10分間
予備加熱した後、215゜Cの熱風オーブン中で3分間
リフローさせ、ついで14−1}リクロルエタンで超音
波洗浄して表面のフラックス残留物を除去して第2図(
C)の如き電気的接合部を得た。得られた接合部は、リ
フローしたはんだはほぼ100%の収率で第2図(C)
のように2電極間にまたがるようにプリッジされており
、チップ立ちによる断線もなく接合強度も通常のはんだ
と比べて何ら遜色はなかった。
After that, it was preheated in a hot air oven at 120"C for 10 minutes, then reflowed in a hot air oven at 215°C for 3 minutes, and then ultrasonically cleaned with 14-1} dichloroethane to remove the flux residue on the surface. Figure 2 (
An electrical connection as shown in C) was obtained. The resulting joint is shown in Figure 2 (C) with almost 100% yield of reflowed solder.
As shown in the figure, the solder was bridged across two electrodes, and there was no disconnection due to standing chips, and the bonding strength was comparable to that of regular solder.

なお、230゜CX30secの条件で再リフローした
ところ、接続部の断線の発生はみられなかった. 比較例2 実施例3におけるはんだペースト■に代えてSn/Pb
 =63/37合金のはんだペースト(千住金属工業■
製、商品名: SPT−55−63 )を用いる以外は
、実施例3と全く同様にして電気的接合部を形成した。
Furthermore, when reflowing was performed at 230°C for 30 seconds, no breakage of the connection was observed. Comparative Example 2 Sn/Pb was used instead of solder paste ■ in Example 3.
= 63/37 alloy solder paste (Senju Metal Industry ■
An electrical joint was formed in exactly the same manner as in Example 3, except for using SPT-55-63 (trade name: SPT-55-63, manufactured by Mikko Industries, Ltd.).

得られた接合部は第6図のように供給はんだ量の少ない
方でチップ部品3が立ち上がっており、電極1と2のブ
リッジは不可能であった。
In the resulting joint, as shown in FIG. 6, the chip component 3 stood up when the amount of supplied solder was smaller, and it was impossible to bridge the electrodes 1 and 2.

実施例4 下記第1表に示すはんだペースト■〜■を用いる以外は
、実施例1〜3と全く同様にして電気的接合部を形成し
た。なお、各々のペーストのはんだ粒、金属粒の粒径及
び形状、またフラックスの材質ははんだペーストのと同
様であった。
Example 4 Electrical joints were formed in the same manner as in Examples 1 to 3, except that solder pastes 1 to 3 shown in Table 1 below were used. Note that the particle size and shape of the solder grains and metal grains of each paste, and the material of the flux were the same as those of the solder paste.

いずれの電気的接合部においても、リフローしたはんだ
はほぼ100%の収率で2電極間にまたがるようにプリ
ッジされており、接合強度も通常のはんだと比べて何ら
遜色はなかった。また230”CX30secの条件で
再リフロ−し7たところ接続部の断線の発生はなく、そ
の後の信頼性も良好であった。
In all electrical joints, the reflowed solder was bridged across the two electrodes with a yield of almost 100%, and the joint strength was no inferior to that of ordinary solder. Furthermore, after reflowing at 230"CX for 30 seconds, no disconnection occurred at the connection, and the reliability thereafter was also good.

第   1   表 〔発明の効果〕 本発明によれば、従来の共晶系のはんだペーストを使用
した場合に比べてチップ部品上の電極と基板上の電極と
のギャップを広くとれるのでチップ部品の位置決めに高
い精度を必要とせずに、高密度の実装を可能とする。更
に接合部の接触抵抗、信頼性は従来のものと何ら遜色は
なく、しかも再リフロ一に対する安定性は従来のものに
比べてはるかに向上する. また、本発明を通常の表面実装法に適用すればはんだペ
ーストの塗布量のバラッキによるチップ立ちが激減する
他、従来のはんだでは実現不可能であった第2図(A)
の形態も可能となる。
Table 1 [Effects of the Invention] According to the present invention, the gap between the electrode on the chip component and the electrode on the substrate can be made wider than when using a conventional eutectic solder paste, so the positioning of the chip component is easier. Enables high-density packaging without requiring high precision. Furthermore, the contact resistance and reliability of the joint are no different from conventional ones, and the stability against reflow is much improved compared to conventional ones. In addition, if the present invention is applied to a normal surface mounting method, chip standing due to variations in the amount of solder paste applied will be drastically reduced, and as shown in Fig. 2 (A), which was impossible to achieve with conventional solder.
form is also possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明電気的接合部の一実施態様を示す断面図
、第2図(A)〜(D)は本発明の電気的接合部の種々
の実施態様を示す断面図、第3図(八)ないし(C)は
本発明の電気的接合部の製造工程の一実施態様を説明す
る断面図、第4及び5図は本発明実施例における電極を
説明する斜視図、第6及び7図は従来のはんだペースト
を用いて得た電気的接合部の一例を示す断面圓である。
FIG. 1 is a cross-sectional view showing one embodiment of the electrical joint of the present invention, FIGS. 2(A) to (D) are cross-sectional views showing various embodiments of the electrical joint of the present invention, and FIG. (8) to (C) are cross-sectional views illustrating one embodiment of the manufacturing process of the electrical joint of the present invention, 4th and 5th are perspective views illustrating electrodes in the embodiments of the present invention, and 6th and 7th The figure is a cross-sectional circle showing an example of an electrical joint obtained using a conventional solder paste.

Claims (2)

【特許請求の範囲】[Claims] 1.絶縁体上に設けられた複数の電極とチップ部品上に
設けられた複数の電極が独立に電気的に接続された電気
的接合部において,前記電極間が複数の金属粒を含むは
んだで接続され、かつ前記複数の金属粒の融点が前記は
んだより高く、かつ前記複数の金属粒の構成材質の全部
または一部に前記はんだの構成材質と異なる材質を含む
ことを特徴とする電気的接合部。
1. In an electrical joint where a plurality of electrodes provided on an insulator and a plurality of electrodes provided on a chip component are independently electrically connected, the electrodes are connected by solder containing a plurality of metal grains. , and the plurality of metal particles have a higher melting point than the solder, and all or part of the constituent material of the plurality of metal particles includes a material different from the constituent material of the solder.
2.はんだが、すずを含む合金であり、かつ複数の金属
粒がAu,Ag,Niの単独、またはAu,Ag,Ni
,Suのうちいずれかを含む金属あるいは合金で表面を
覆った銅粒である特許請求の範囲第1項に記載の電気的
接合部。
2. The solder is an alloy containing tin, and the plurality of metal particles are Au, Ag, and Ni alone, or Au, Ag, and Ni.
, Su. , or Su.
JP1150373A 1989-06-15 1989-06-15 Electrical junction Expired - Lifetime JPH07118498B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1150373A JPH07118498B2 (en) 1989-06-15 1989-06-15 Electrical junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1150373A JPH07118498B2 (en) 1989-06-15 1989-06-15 Electrical junction

Publications (2)

Publication Number Publication Date
JPH0318041A true JPH0318041A (en) 1991-01-25
JPH07118498B2 JPH07118498B2 (en) 1995-12-18

Family

ID=15495575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1150373A Expired - Lifetime JPH07118498B2 (en) 1989-06-15 1989-06-15 Electrical junction

Country Status (1)

Country Link
JP (1) JPH07118498B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317191A (en) * 1991-08-19 1994-05-31 Mitsubishi Denki Kabushiki Kaisha Low-melting-point junction material having high-melting-point particles uniformly dispersed therein
US5428249A (en) * 1992-07-15 1995-06-27 Canon Kabushiki Kaisha Photovoltaic device with improved collector electrode
JP2002231736A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Method for forming antenna mounting ic chip
JP2007510301A (en) * 2003-10-29 2007-04-19 コンダクティブ・インクジェット・テクノロジー・リミテッド Electrical connection of parts
WO2007096946A1 (en) * 2006-02-21 2007-08-30 Matsushita Electric Industrial Co., Ltd. Package and method for producing same
JP2008534252A (en) * 2005-03-22 2008-08-28 コンダクティブ・インクジェット・テクノロジー・リミテッド Handling of things
JP2009164431A (en) * 2008-01-08 2009-07-23 Fujitsu Microelectronics Ltd Manufacturing method of semiconductor device, cleaning method of semiconductor device, and cleaning device
JP2013258254A (en) * 2012-06-12 2013-12-26 Koki:Kk Method of manufacturing electronic device by laser heating method

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317191A (en) * 1991-08-19 1994-05-31 Mitsubishi Denki Kabushiki Kaisha Low-melting-point junction material having high-melting-point particles uniformly dispersed therein
US5428249A (en) * 1992-07-15 1995-06-27 Canon Kabushiki Kaisha Photovoltaic device with improved collector electrode
US6214636B1 (en) 1992-07-15 2001-04-10 Canon Kabushiki Kaisha Photovoltaic device with improved collector electrode
JP2002231736A (en) * 2001-01-31 2002-08-16 Toppan Forms Co Ltd Method for forming antenna mounting ic chip
JP4666296B2 (en) * 2001-01-31 2011-04-06 トッパン・フォームズ株式会社 Method for forming antenna mounted with IC chip
JP2007510301A (en) * 2003-10-29 2007-04-19 コンダクティブ・インクジェット・テクノロジー・リミテッド Electrical connection of parts
JP2008534252A (en) * 2005-03-22 2008-08-28 コンダクティブ・インクジェット・テクノロジー・リミテッド Handling of things
JPWO2007096946A1 (en) * 2006-02-21 2009-07-09 パナソニック株式会社 Mounted body and manufacturing method thereof
US7713787B2 (en) 2006-02-21 2010-05-11 Panasonic Corporation Mounted body and method for manufacturing the same
WO2007096946A1 (en) * 2006-02-21 2007-08-30 Matsushita Electric Industrial Co., Ltd. Package and method for producing same
US8039307B2 (en) 2006-02-21 2011-10-18 Panasonic Corporation Mounted body and method for manufacturing the same
JP5085932B2 (en) * 2006-02-21 2012-11-28 パナソニック株式会社 Mounted body and manufacturing method thereof
JP2009164431A (en) * 2008-01-08 2009-07-23 Fujitsu Microelectronics Ltd Manufacturing method of semiconductor device, cleaning method of semiconductor device, and cleaning device
JP2013258254A (en) * 2012-06-12 2013-12-26 Koki:Kk Method of manufacturing electronic device by laser heating method

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